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kvm: x86, powerpc: do not allow clearing largepages debugfs entry
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
20c8ccb1 1// SPDX-License-Identifier: GPL-2.0-only
043405e1
CO		 2/*
3 * Kernel-based Virtual Machine driver for Linux
4 *
5 * derived from drivers/kvm/kvm_main.c
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 8 * Copyright (C) 2008 Qumranet, Inc.
9 * Copyright IBM Corporation, 2008
9611c187 10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 11 *
12 * Authors:
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 15 * Amit Shah <amit.shah@qumranet.com>
16 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 17 */
18
edf88417 19#include <linux/kvm_host.h>
313a3dc7 20#include "irq.h"
1d737c8a 21#include "mmu.h"
7837699f 22#include "i8254.h"
37817f29 23#include "tss.h"
5fdbf976 24#include "kvm_cache_regs.h"
26eef70c 25#include "x86.h"
00b27a3e 26#include "cpuid.h"
474a5bb9 27#include "pmu.h"
e83d5887 28#include "hyperv.h"
313a3dc7 29
18068523 30#include <linux/clocksource.h>
4d5c5d0f 31#include <linux/interrupt.h>
313a3dc7
CO		 32#include <linux/kvm.h>
33#include <linux/fs.h>
34#include <linux/vmalloc.h>
1767e931
PG		 35#include <linux/export.h>
36#include <linux/moduleparam.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
16e8d74d
MT		 49#include <linux/timekeeper_internal.h>
50#include <linux/pvclock_gtod.h>
87276880
FW		 51#include <linux/kvm_irqfd.h>
52#include <linux/irqbypass.h>
3905f9ad 53#include <linux/sched/stat.h>
0c5f81da 54#include <linux/sched/isolation.h>
d0ec49d4 55#include <linux/mem_encrypt.h>
3905f9ad 56
aec51dc4 57#include <trace/events/kvm.h>
2ed152af 58
24f1e32c 59#include <asm/debugreg.h>
d825ed0a 60#include <asm/msr.h>
a5f61300 61#include <asm/desc.h>
890ca9ae 62#include <asm/mce.h>
f89e32e0 63#include <linux/kernel_stat.h>
78f7f1e5 64#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 65#include <asm/pvclock.h>
217fc9cf 66#include <asm/div64.h>
efc64404 67#include <asm/irq_remapping.h>
b0c39dc6 68#include <asm/mshyperv.h>
0092e434 69#include <asm/hypervisor.h>
bf8c55d8 70#include <asm/intel_pt.h>
dd2cb348 71#include <clocksource/hyperv_timer.h>
043405e1 72
d1898b73
DH		 73#define CREATE_TRACE_POINTS
74#include "trace.h"
75
313a3dc7 76#define MAX_IO_MSRS 256
890ca9ae 77#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 78u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
79EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 80
0f65dd70
AK		 81#define emul_to_vcpu(ctxt) \
82 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
83
50a37eb4
JR		 84/* EFER defaults:
85 * - enable syscall per default because its emulated by KVM
86 * - enable LME and LMA per default on 64 bit KVM
87 */
88#ifdef CONFIG_X86_64
1260edbe
LJ		 89static
90u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 91#else
1260edbe 92static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 93#endif
313a3dc7 94
833b45de
PB		 95#define VM_STAT(x, ...) offsetof(struct kvm, stat.x), KVM_STAT_VM, ## __VA_ARGS__
96#define VCPU_STAT(x, ...) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU, ## __VA_ARGS__
417bc304 97
c519265f
RK		 98#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
99 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 100
cb142eb7 101static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 102static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 103static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 104static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
01643c51
KH		 105static void store_regs(struct kvm_vcpu *vcpu);
106static int sync_regs(struct kvm_vcpu *vcpu);
674eea0f 107
893590c7 108struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 109EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 110
893590c7 111static bool __read_mostly ignore_msrs = 0;
476bc001 112module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 113
fab0aa3b
EM		 114static bool __read_mostly report_ignored_msrs = true;
115module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
116
4c27625b 117unsigned int min_timer_period_us = 200;
9ed96e87
MT		 118module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
119
630994b3
MT		 120static bool __read_mostly kvmclock_periodic_sync = true;
121module_param(kvmclock_periodic_sync, bool, S_IRUGO);
122
893590c7 123bool __read_mostly kvm_has_tsc_control;
92a1f12d 124EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 125u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 126EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 127u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
128EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
129u64 __read_mostly kvm_max_tsc_scaling_ratio;
130EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 131u64 __read_mostly kvm_default_tsc_scaling_ratio;
132EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 133
cc578287 134/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 135static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 136module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
137
c3941d9e
SC		 138/*
139 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables
140 * adaptive tuning starting from default advancment of 1000ns. '0' disables
141 * advancement entirely. Any other value is used as-is and disables adaptive
142 * tuning, i.e. allows priveleged userspace to set an exact advancement time.
143 */
144static int __read_mostly lapic_timer_advance_ns = -1;
0e6edceb 145module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR);
d0659d94 146
52004014
FW		 147static bool __read_mostly vector_hashing = true;
148module_param(vector_hashing, bool, S_IRUGO);
149
c4ae60e4
LA		 150bool __read_mostly enable_vmware_backdoor = false;
151module_param(enable_vmware_backdoor, bool, S_IRUGO);
152EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
153
6c86eedc
WL		 154static bool __read_mostly force_emulation_prefix = false;
155module_param(force_emulation_prefix, bool, S_IRUGO);
156
0c5f81da
WL		 157int __read_mostly pi_inject_timer = -1;
158module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR);
159
18863bdd
AK		 160#define KVM_NR_SHARED_MSRS 16
161
162struct kvm_shared_msrs_global {
163 int nr;
2bf78fa7 164 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 165};
166
167struct kvm_shared_msrs {
168 struct user_return_notifier urn;
169 bool registered;
2bf78fa7
SY		 170 struct kvm_shared_msr_values {
171 u64 host;
172 u64 curr;
173 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 174};
175
176static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 177static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 178
417bc304 179struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 180 { "pf_fixed", VCPU_STAT(pf_fixed) },
181 { "pf_guest", VCPU_STAT(pf_guest) },
182 { "tlb_flush", VCPU_STAT(tlb_flush) },
183 { "invlpg", VCPU_STAT(invlpg) },
184 { "exits", VCPU_STAT(exits) },
185 { "io_exits", VCPU_STAT(io_exits) },
186 { "mmio_exits", VCPU_STAT(mmio_exits) },
187 { "signal_exits", VCPU_STAT(signal_exits) },
188 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 189 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 190 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 191 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 192 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 193 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 194 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 195 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 196 { "request_irq", VCPU_STAT(request_irq_exits) },
197 { "irq_exits", VCPU_STAT(irq_exits) },
198 { "host_state_reload", VCPU_STAT(host_state_reload) },
ba1389b7
AK		 199 { "fpu_reload", VCPU_STAT(fpu_reload) },
200 { "insn_emulation", VCPU_STAT(insn_emulation) },
201 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 202 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 203 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 204 { "req_event", VCPU_STAT(req_event) },
c595ceee 205 { "l1d_flush", VCPU_STAT(l1d_flush) },
4cee5764
AK		 206 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
207 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
208 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
209 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
210 { "mmu_flooded", VM_STAT(mmu_flooded) },
211 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 212 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 213 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 214 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
833b45de 215 { "largepages", VM_STAT(lpages, .mode = 0444) },
f3414bc7
DM		 216 { "max_mmu_page_hash_collisions",
217 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 218 { NULL }
219};
220
2acf923e
DC		 221u64 __read_mostly host_xcr0;
222
b666a4b6
MO		 223struct kmem_cache *x86_fpu_cache;
224EXPORT_SYMBOL_GPL(x86_fpu_cache);
225
b6785def 226static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 227
af585b92
GN		 228static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
229{
230 int i;
231 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
232 vcpu->arch.apf.gfns[i] = ~0;
233}
234
18863bdd
AK		 235static void kvm_on_user_return(struct user_return_notifier *urn)
236{
237 unsigned slot;
18863bdd
AK		 238 struct kvm_shared_msrs *locals
239 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 240 struct kvm_shared_msr_values *values;
1650b4eb
IA		 241 unsigned long flags;
242
243 /*
244 * Disabling irqs at this point since the following code could be
245 * interrupted and executed through kvm_arch_hardware_disable()
246 */
247 local_irq_save(flags);
248 if (locals->registered) {
249 locals->registered = false;
250 user_return_notifier_unregister(urn);
251 }
252 local_irq_restore(flags);
18863bdd 253 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 254 values = &locals->values[slot];
255 if (values->host != values->curr) {
256 wrmsrl(shared_msrs_global.msrs[slot], values->host);
257 values->curr = values->host;
18863bdd
AK		 258 }
259 }
18863bdd
AK		 260}
261
2bf78fa7 262static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 263{
18863bdd 264 u64 value;
013f6a5d
MT		 265 unsigned int cpu = smp_processor_id();
266 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 267
2bf78fa7
SY		 268 /* only read, and nobody should modify it at this time,
269 * so don't need lock */
270 if (slot >= shared_msrs_global.nr) {
271 printk(KERN_ERR "kvm: invalid MSR slot!");
272 return;
273 }
274 rdmsrl_safe(msr, &value);
275 smsr->values[slot].host = value;
276 smsr->values[slot].curr = value;
277}
278
279void kvm_define_shared_msr(unsigned slot, u32 msr)
280{
0123be42 281 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 282 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 283 if (slot >= shared_msrs_global.nr)
284 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 285}
286EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
287
288static void kvm_shared_msr_cpu_online(void)
289{
290 unsigned i;
18863bdd
AK		 291
292 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 293 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 294}
295
8b3c3104 296int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 297{
013f6a5d
MT		 298 unsigned int cpu = smp_processor_id();
299 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 300 int err;
18863bdd 301
2bf78fa7 302 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 303 return 0;
2bf78fa7 304 smsr->values[slot].curr = value;
8b3c3104
AH		 305 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
306 if (err)
307 return 1;
308
18863bdd
AK		 309 if (!smsr->registered) {
310 smsr->urn.on_user_return = kvm_on_user_return;
311 user_return_notifier_register(&smsr->urn);
312 smsr->registered = true;
313 }
8b3c3104 314 return 0;
18863bdd
AK		 315}
316EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
317
13a34e06 318static void drop_user_return_notifiers(void)
3548bab5 319{
013f6a5d
MT		 320 unsigned int cpu = smp_processor_id();
321 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 322
323 if (smsr->registered)
324 kvm_on_user_return(&smsr->urn);
325}
326
6866b83e
CO		 327u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
328{
8a5a87d9 329 return vcpu->arch.apic_base;
6866b83e
CO		 330}
331EXPORT_SYMBOL_GPL(kvm_get_apic_base);
332
58871649
JM		 333enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
334{
335 return kvm_apic_mode(kvm_get_apic_base(vcpu));
336}
337EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
338
58cb628d
JK		 339int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
340{
58871649
JM		 341 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
342 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
d6321d49
RK		 343 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
344 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
58cb628d 345
58871649 346 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
58cb628d 347 return 1;
58871649
JM		 348 if (!msr_info->host_initiated) {
349 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
350 return 1;
351 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
352 return 1;
353 }
58cb628d
JK		 354
355 kvm_lapic_set_base(vcpu, msr_info->data);
356 return 0;
6866b83e
CO		 357}
358EXPORT_SYMBOL_GPL(kvm_set_apic_base);
359
2605fc21 360asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 361{
362 /* Fault while not rebooting. We want the trace. */
4b526de5
SC		 363 if (!kvm_rebooting)
364 BUG();
e3ba45b8
GL		 365}
366EXPORT_SYMBOL_GPL(kvm_spurious_fault);
367
3fd28fce
ED		 368#define EXCPT_BENIGN 0
369#define EXCPT_CONTRIBUTORY 1
370#define EXCPT_PF 2
371
372static int exception_class(int vector)
373{
374 switch (vector) {
375 case PF_VECTOR:
376 return EXCPT_PF;
377 case DE_VECTOR:
378 case TS_VECTOR:
379 case NP_VECTOR:
380 case SS_VECTOR:
381 case GP_VECTOR:
382 return EXCPT_CONTRIBUTORY;
383 default:
384 break;
385 }
386 return EXCPT_BENIGN;
387}
388
d6e8c854
NA		 389#define EXCPT_FAULT 0
390#define EXCPT_TRAP 1
391#define EXCPT_ABORT 2
392#define EXCPT_INTERRUPT 3
393
394static int exception_type(int vector)
395{
396 unsigned int mask;
397
398 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
399 return EXCPT_INTERRUPT;
400
401 mask = 1 << vector;
402
403 /* #DB is trap, as instruction watchpoints are handled elsewhere */
404 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
405 return EXCPT_TRAP;
406
407 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
408 return EXCPT_ABORT;
409
410 /* Reserved exceptions will result in fault */
411 return EXCPT_FAULT;
412}
413
da998b46
JM		 414void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
415{
416 unsigned nr = vcpu->arch.exception.nr;
417 bool has_payload = vcpu->arch.exception.has_payload;
418 unsigned long payload = vcpu->arch.exception.payload;
419
420 if (!has_payload)
421 return;
422
423 switch (nr) {
f10c729f
JM		 424 case DB_VECTOR:
425 /*
426 * "Certain debug exceptions may clear bit 0-3. The
427 * remaining contents of the DR6 register are never
428 * cleared by the processor".
429 */
430 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
431 /*
432 * DR6.RTM is set by all #DB exceptions that don't clear it.
433 */
434 vcpu->arch.dr6 |= DR6_RTM;
435 vcpu->arch.dr6 |= payload;
436 /*
437 * Bit 16 should be set in the payload whenever the #DB
438 * exception should clear DR6.RTM. This makes the payload
439 * compatible with the pending debug exceptions under VMX.
440 * Though not currently documented in the SDM, this also
441 * makes the payload compatible with the exit qualification
442 * for #DB exceptions under VMX.
443 */
444 vcpu->arch.dr6 ^= payload & DR6_RTM;
445 break;
da998b46
JM		 446 case PF_VECTOR:
447 vcpu->arch.cr2 = payload;
448 break;
449 }
450
451 vcpu->arch.exception.has_payload = false;
452 vcpu->arch.exception.payload = 0;
453}
454EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
455
3fd28fce 456static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4 457 unsigned nr, bool has_error, u32 error_code,
91e86d22 458 bool has_payload, unsigned long payload, bool reinject)
3fd28fce
ED		 459{
460 u32 prev_nr;
461 int class1, class2;
462
3842d135
AK		 463 kvm_make_request(KVM_REQ_EVENT, vcpu);
464
664f8e26 465 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
3fd28fce 466 queue:
3ffb2468
NA		 467 if (has_error && !is_protmode(vcpu))
468 has_error = false;
664f8e26
WL		 469 if (reinject) {
470 /*
471 * On vmentry, vcpu->arch.exception.pending is only
472 * true if an event injection was blocked by
473 * nested_run_pending. In that case, however,
474 * vcpu_enter_guest requests an immediate exit,
475 * and the guest shouldn't proceed far enough to
476 * need reinjection.
477 */
478 WARN_ON_ONCE(vcpu->arch.exception.pending);
479 vcpu->arch.exception.injected = true;
91e86d22
JM		 480 if (WARN_ON_ONCE(has_payload)) {
481 /*
482 * A reinjected event has already
483 * delivered its payload.
484 */
485 has_payload = false;
486 payload = 0;
487 }
664f8e26
WL		 488 } else {
489 vcpu->arch.exception.pending = true;
490 vcpu->arch.exception.injected = false;
491 }
3fd28fce
ED		 492 vcpu->arch.exception.has_error_code = has_error;
493 vcpu->arch.exception.nr = nr;
494 vcpu->arch.exception.error_code = error_code;
91e86d22
JM		 495 vcpu->arch.exception.has_payload = has_payload;
496 vcpu->arch.exception.payload = payload;
da998b46
JM		 497 /*
498 * In guest mode, payload delivery should be deferred,
499 * so that the L1 hypervisor can intercept #PF before
f10c729f
JM		 500 * CR2 is modified (or intercept #DB before DR6 is
501 * modified under nVMX). However, for ABI
502 * compatibility with KVM_GET_VCPU_EVENTS and
503 * KVM_SET_VCPU_EVENTS, we can't delay payload
504 * delivery unless userspace has enabled this
505 * functionality via the per-VM capability,
506 * KVM_CAP_EXCEPTION_PAYLOAD.
da998b46
JM		 507 */
508 if (!vcpu->kvm->arch.exception_payload_enabled ||
509 !is_guest_mode(vcpu))
510 kvm_deliver_exception_payload(vcpu);
3fd28fce
ED		 511 return;
512 }
513
514 /* to check exception */
515 prev_nr = vcpu->arch.exception.nr;
516 if (prev_nr == DF_VECTOR) {
517 /* triple fault -> shutdown */
a8eeb04a 518 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 519 return;
520 }
521 class1 = exception_class(prev_nr);
522 class2 = exception_class(nr);
523 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
524 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
664f8e26
WL		 525 /*
526 * Generate double fault per SDM Table 5-5. Set
527 * exception.pending = true so that the double fault
528 * can trigger a nested vmexit.
529 */
3fd28fce 530 vcpu->arch.exception.pending = true;
664f8e26 531 vcpu->arch.exception.injected = false;
3fd28fce
ED		 532 vcpu->arch.exception.has_error_code = true;
533 vcpu->arch.exception.nr = DF_VECTOR;
534 vcpu->arch.exception.error_code = 0;
c851436a
JM		 535 vcpu->arch.exception.has_payload = false;
536 vcpu->arch.exception.payload = 0;
3fd28fce
ED		 537 } else
538 /* replace previous exception with a new one in a hope
539 that instruction re-execution will regenerate lost
540 exception */
541 goto queue;
542}
543
298101da
AK		 544void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
545{
91e86d22 546 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
298101da
AK		 547}
548EXPORT_SYMBOL_GPL(kvm_queue_exception);
549
ce7ddec4
JR		 550void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
551{
91e86d22 552 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
ce7ddec4
JR		 553}
554EXPORT_SYMBOL_GPL(kvm_requeue_exception);
555
f10c729f
JM		 556static void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
557 unsigned long payload)
558{
559 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
560}
561
da998b46
JM		 562static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
563 u32 error_code, unsigned long payload)
564{
565 kvm_multiple_exception(vcpu, nr, true, error_code,
566 true, payload, false);
567}
568
6affcbed 569int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 570{
db8fcefa
AP		 571 if (err)
572 kvm_inject_gp(vcpu, 0);
573 else
6affcbed
KH		 574 return kvm_skip_emulated_instruction(vcpu);
575
576 return 1;
db8fcefa
AP		 577}
578EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 579
6389ee94 580void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 581{
582 ++vcpu->stat.pf_guest;
adfe20fb
WL		 583 vcpu->arch.exception.nested_apf =
584 is_guest_mode(vcpu) && fault->async_page_fault;
da998b46 585 if (vcpu->arch.exception.nested_apf) {
adfe20fb 586 vcpu->arch.apf.nested_apf_token = fault->address;
da998b46
JM		 587 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
588 } else {
589 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
590 fault->address);
591 }
c3c91fee 592}
27d6c865 593EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 594
ef54bcfe 595static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 596{
6389ee94
AK		 597 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
598 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 599 else
44dd3ffa 600 vcpu->arch.mmu->inject_page_fault(vcpu, fault);
ef54bcfe
PB		 601
602 return fault->nested_page_fault;
d4f8cf66
JR		 603}
604
3419ffc8
SY		 605void kvm_inject_nmi(struct kvm_vcpu *vcpu)
606{
7460fb4a
AK		 607 atomic_inc(&vcpu->arch.nmi_queued);
608 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 609}
610EXPORT_SYMBOL_GPL(kvm_inject_nmi);
611
298101da
AK		 612void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
613{
91e86d22 614 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
298101da
AK		 615}
616EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
617
ce7ddec4
JR		 618void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
619{
91e86d22 620 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
ce7ddec4
JR		 621}
622EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
623
0a79b009
AK		 624/*
625 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
626 * a #GP and return false.
627 */
628bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 629{
0a79b009
AK		 630 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
631 return true;
632 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
633 return false;
298101da 634}
0a79b009 635EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 636
16f8a6f9
NA		 637bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
638{
639 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
640 return true;
641
642 kvm_queue_exception(vcpu, UD_VECTOR);
643 return false;
644}
645EXPORT_SYMBOL_GPL(kvm_require_dr);
646
ec92fe44
JR		 647/*
648 * This function will be used to read from the physical memory of the currently
54bf36aa 649 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 650 * can read from guest physical or from the guest's guest physical memory.
651 */
652int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
653 gfn_t ngfn, void *data, int offset, int len,
654 u32 access)
655{
54987b7a 656 struct x86_exception exception;
ec92fe44
JR		 657 gfn_t real_gfn;
658 gpa_t ngpa;
659
660 ngpa = gfn_to_gpa(ngfn);
54987b7a 661 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 662 if (real_gfn == UNMAPPED_GVA)
663 return -EFAULT;
664
665 real_gfn = gpa_to_gfn(real_gfn);
666
54bf36aa 667 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 668}
669EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
670
69b0049a 671static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 672 void *data, int offset, int len, u32 access)
673{
674 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
675 data, offset, len, access);
676}
677
16cfacc8
SC		 678static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu)
679{
680 return rsvd_bits(cpuid_maxphyaddr(vcpu), 63) | rsvd_bits(5, 8) |
681 rsvd_bits(1, 2);
682}
683
a03490ed 684/*
16cfacc8 685 * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise.
a03490ed 686 */
ff03a073 687int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 688{
689 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
690 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
691 int i;
692 int ret;
ff03a073 693 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 694
ff03a073
JR		 695 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
696 offset * sizeof(u64), sizeof(pdpte),
697 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 698 if (ret < 0) {
699 ret = 0;
700 goto out;
701 }
702 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 703 if ((pdpte[i] & PT_PRESENT_MASK) &&
16cfacc8 704 (pdpte[i] & pdptr_rsvd_bits(vcpu))) {
a03490ed
CO		 705 ret = 0;
706 goto out;
707 }
708 }
709 ret = 1;
710
ff03a073 711 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 712 __set_bit(VCPU_EXREG_PDPTR,
713 (unsigned long *)&vcpu->arch.regs_avail);
714 __set_bit(VCPU_EXREG_PDPTR,
715 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 716out:
a03490ed
CO		 717
718 return ret;
719}
cc4b6871 720EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 721
9ed38ffa 722bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 723{
ff03a073 724 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 725 bool changed = true;
3d06b8bf
JR		 726 int offset;
727 gfn_t gfn;
d835dfec
AK		 728 int r;
729
bf03d4f9 730 if (!is_pae_paging(vcpu))
d835dfec
AK		 731 return false;
732
6de4f3ad
AK		 733 if (!test_bit(VCPU_EXREG_PDPTR,
734 (unsigned long *)&vcpu->arch.regs_avail))
735 return true;
736
a512177e
PB		 737 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
738 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
3d06b8bf
JR		 739 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
740 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 741 if (r < 0)
742 goto out;
ff03a073 743 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 744out:
d835dfec
AK		 745
746 return changed;
747}
9ed38ffa 748EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 749
49a9b07e 750int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 751{
aad82703 752 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 753 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 754
f9a48e6a
AK		 755 cr0 |= X86_CR0_ET;
756
ab344828 757#ifdef CONFIG_X86_64
0f12244f
GN		 758 if (cr0 & 0xffffffff00000000UL)
759 return 1;
ab344828
GN		 760#endif
761
762 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 763
0f12244f
GN		 764 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
765 return 1;
a03490ed 766
0f12244f
GN		 767 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
768 return 1;
a03490ed
CO		 769
770 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
771#ifdef CONFIG_X86_64
f6801dff 772 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 773 int cs_db, cs_l;
774
0f12244f
GN		 775 if (!is_pae(vcpu))
776 return 1;
a03490ed 777 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 778 if (cs_l)
779 return 1;
a03490ed
CO		 780 } else
781#endif
ff03a073 782 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 783 kvm_read_cr3(vcpu)))
0f12244f 784 return 1;
a03490ed
CO		 785 }
786
ad756a16
MJ		 787 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
788 return 1;
789
a03490ed 790 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 791
d170c419 792 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 793 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 794 kvm_async_pf_hash_reset(vcpu);
795 }
e5f3f027 796
aad82703
SY		 797 if ((cr0 ^ old_cr0) & update_bits)
798 kvm_mmu_reset_context(vcpu);
b18d5431 799
879ae188
LE		 800 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
801 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
802 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 803 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
804
0f12244f
GN		 805 return 0;
806}
2d3ad1f4 807EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 808
2d3ad1f4 809void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 810{
49a9b07e 811 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 812}
2d3ad1f4 813EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 814
1811d979 815void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
42bdf991
MT		 816{
817 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
818 !vcpu->guest_xcr0_loaded) {
819 /* kvm_set_xcr() also depends on this */
476b7ada
PB		 820 if (vcpu->arch.xcr0 != host_xcr0)
821 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
42bdf991
MT		 822 vcpu->guest_xcr0_loaded = 1;
823 }
824}
1811d979 825EXPORT_SYMBOL_GPL(kvm_load_guest_xcr0);
42bdf991 826
1811d979 827void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
42bdf991
MT		 828{
829 if (vcpu->guest_xcr0_loaded) {
830 if (vcpu->arch.xcr0 != host_xcr0)
831 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
832 vcpu->guest_xcr0_loaded = 0;
833 }
834}
1811d979 835EXPORT_SYMBOL_GPL(kvm_put_guest_xcr0);
42bdf991 836
69b0049a 837static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 838{
56c103ec
LJ		 839 u64 xcr0 = xcr;
840 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 841 u64 valid_bits;
2acf923e
DC		 842
843 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
844 if (index != XCR_XFEATURE_ENABLED_MASK)
845 return 1;
d91cab78 846 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 847 return 1;
d91cab78 848 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 849 return 1;
46c34cb0
PB		 850
851 /*
852 * Do not allow the guest to set bits that we do not support
853 * saving. However, xcr0 bit 0 is always set, even if the
854 * emulated CPU does not support XSAVE (see fx_init).
855 */
d91cab78 856 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 857 if (xcr0 & ~valid_bits)
2acf923e 858 return 1;
46c34cb0 859
d91cab78
DH		 860 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
861 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 862 return 1;
863
d91cab78
DH		 864 if (xcr0 & XFEATURE_MASK_AVX512) {
865 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 866 return 1;
d91cab78 867 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 868 return 1;
869 }
2acf923e 870 vcpu->arch.xcr0 = xcr0;
56c103ec 871
d91cab78 872 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 873 kvm_update_cpuid(vcpu);
2acf923e
DC		 874 return 0;
875}
876
877int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
878{
764bcbc5
Z		 879 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
880 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 881 kvm_inject_gp(vcpu, 0);
882 return 1;
883 }
884 return 0;
885}
886EXPORT_SYMBOL_GPL(kvm_set_xcr);
887
3ca94192 888static int kvm_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 889{
0f12244f 890 if (cr4 & CR4_RESERVED_BITS)
3ca94192 891 return -EINVAL;
a03490ed 892
d6321d49 893 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
3ca94192 894 return -EINVAL;
2acf923e 895
d6321d49 896 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
3ca94192 897 return -EINVAL;
2acf923e 898
d6321d49 899 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
3ca94192 900 return -EINVAL;
c68b734f 901
d6321d49 902 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
3ca94192 903 return -EINVAL;
97ec8c06 904
d6321d49 905 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
3ca94192 906 return -EINVAL;
74dc2b4f 907
fd8cb433 908 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
3ca94192 909 return -EINVAL;
b9baba86 910
ae3e61e1 911 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
3ca94192
WL		 912 return -EINVAL;
913
914 return 0;
915}
916
917int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
918{
919 unsigned long old_cr4 = kvm_read_cr4(vcpu);
920 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
921 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
922
923 if (kvm_valid_cr4(vcpu, cr4))
ae3e61e1
PB		 924 return 1;
925
a03490ed 926 if (is_long_mode(vcpu)) {
0f12244f
GN		 927 if (!(cr4 & X86_CR4_PAE))
928 return 1;
a2edf57f
AK		 929 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
930 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 931 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
932 kvm_read_cr3(vcpu)))
0f12244f
GN		 933 return 1;
934
ad756a16 935 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
d6321d49 936 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
ad756a16
MJ		 937 return 1;
938
939 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
940 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
941 return 1;
942 }
943
5e1746d6 944 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 945 return 1;
a03490ed 946
ad756a16
MJ		 947 if (((cr4 ^ old_cr4) & pdptr_bits) ||
948 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 949 kvm_mmu_reset_context(vcpu);
0f12244f 950
b9baba86 951 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 952 kvm_update_cpuid(vcpu);
2acf923e 953
0f12244f
GN		 954 return 0;
955}
2d3ad1f4 956EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 957
2390218b 958int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 959{
ade61e28 960 bool skip_tlb_flush = false;
ac146235 961#ifdef CONFIG_X86_64
c19986fe
JS		 962 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
963
ade61e28 964 if (pcid_enabled) {
208320ba
JS		 965 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
966 cr3 &= ~X86_CR3_PCID_NOFLUSH;
ade61e28 967 }
ac146235 968#endif
9d88fca7 969
9f8fe504 970 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
956bf353
JS		 971 if (!skip_tlb_flush) {
972 kvm_mmu_sync_roots(vcpu);
ade61e28 973 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
956bf353 974 }
0f12244f 975 return 0;
d835dfec
AK		 976 }
977
d1cd3ce9 978 if (is_long_mode(vcpu) &&
a780a3ea 979 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
d1cd3ce9 980 return 1;
bf03d4f9
PB		 981 else if (is_pae_paging(vcpu) &&
982 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 983 return 1;
a03490ed 984
ade61e28 985 kvm_mmu_new_cr3(vcpu, cr3, skip_tlb_flush);
0f12244f 986 vcpu->arch.cr3 = cr3;
aff48baa 987 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
7c390d35 988
0f12244f
GN		 989 return 0;
990}
2d3ad1f4 991EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 992
eea1cff9 993int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 994{
0f12244f
GN		 995 if (cr8 & CR8_RESERVED_BITS)
996 return 1;
35754c98 997 if (lapic_in_kernel(vcpu))
a03490ed
CO		 998 kvm_lapic_set_tpr(vcpu, cr8);
999 else
ad312c7c 1000 vcpu->arch.cr8 = cr8;
0f12244f
GN		 1001 return 0;
1002}
2d3ad1f4 1003EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 1004
2d3ad1f4 1005unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 1006{
35754c98 1007 if (lapic_in_kernel(vcpu))
a03490ed
CO		 1008 return kvm_lapic_get_cr8(vcpu);
1009 else
ad312c7c 1010 return vcpu->arch.cr8;
a03490ed 1011}
2d3ad1f4 1012EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 1013
ae561ede
NA		 1014static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
1015{
1016 int i;
1017
1018 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1019 for (i = 0; i < KVM_NR_DB_REGS; i++)
1020 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1021 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
1022 }
1023}
1024
73aaf249
JK		 1025static void kvm_update_dr6(struct kvm_vcpu *vcpu)
1026{
1027 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1028 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
1029}
1030
c8639010
JK		 1031static void kvm_update_dr7(struct kvm_vcpu *vcpu)
1032{
1033 unsigned long dr7;
1034
1035 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1036 dr7 = vcpu->arch.guest_debug_dr7;
1037 else
1038 dr7 = vcpu->arch.dr7;
1039 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 1040 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1041 if (dr7 & DR7_BP_EN_MASK)
1042 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 1043}
1044
6f43ed01
NA		 1045static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1046{
1047 u64 fixed = DR6_FIXED_1;
1048
d6321d49 1049 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
6f43ed01
NA		 1050 fixed |= DR6_RTM;
1051 return fixed;
1052}
1053
338dbc97 1054static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 1055{
1056 switch (dr) {
1057 case 0 ... 3:
1058 vcpu->arch.db[dr] = val;
1059 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1060 vcpu->arch.eff_db[dr] = val;
1061 break;
1062 case 4:
020df079
GN		 1063 /* fall through */
1064 case 6:
338dbc97
GN		 1065 if (val & 0xffffffff00000000ULL)
1066 return -1; /* #GP */
6f43ed01 1067 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 1068 kvm_update_dr6(vcpu);
020df079
GN		 1069 break;
1070 case 5:
020df079
GN		 1071 /* fall through */
1072 default: /* 7 */
338dbc97
GN		 1073 if (val & 0xffffffff00000000ULL)
1074 return -1; /* #GP */
020df079 1075 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 1076 kvm_update_dr7(vcpu);
020df079
GN		 1077 break;
1078 }
1079
1080 return 0;
1081}
338dbc97
GN		 1082
1083int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1084{
16f8a6f9 1085 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 1086 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 1087 return 1;
1088 }
1089 return 0;
338dbc97 1090}
020df079
GN		 1091EXPORT_SYMBOL_GPL(kvm_set_dr);
1092
16f8a6f9 1093int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 1094{
1095 switch (dr) {
1096 case 0 ... 3:
1097 *val = vcpu->arch.db[dr];
1098 break;
1099 case 4:
020df079
GN		 1100 /* fall through */
1101 case 6:
73aaf249
JK		 1102 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1103 *val = vcpu->arch.dr6;
1104 else
1105 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 1106 break;
1107 case 5:
020df079
GN		 1108 /* fall through */
1109 default: /* 7 */
1110 *val = vcpu->arch.dr7;
1111 break;
1112 }
338dbc97
GN		 1113 return 0;
1114}
020df079
GN		 1115EXPORT_SYMBOL_GPL(kvm_get_dr);
1116
022cd0e8
AK		 1117bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1118{
de3cd117 1119 u32 ecx = kvm_rcx_read(vcpu);
022cd0e8
AK		 1120 u64 data;
1121 int err;
1122
c6702c9d 1123 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 1124 if (err)
1125 return err;
de3cd117
SC		 1126 kvm_rax_write(vcpu, (u32)data);
1127 kvm_rdx_write(vcpu, data >> 32);
022cd0e8
AK		 1128 return err;
1129}
1130EXPORT_SYMBOL_GPL(kvm_rdpmc);
1131
043405e1
CO		 1132/*
1133 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1134 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1135 *
1136 * This list is modified at module load time to reflect the
e3267cbb 1137 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 1138 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1139 * may depend on host virtualization features rather than host cpu features.
043405e1 1140 */
e3267cbb 1141
043405e1
CO		 1142static u32 msrs_to_save[] = {
1143 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 1144 MSR_STAR,
043405e1
CO		 1145#ifdef CONFIG_X86_64
1146 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1147#endif
b3897a49 1148 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 1149 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
2bdb76c0 1150 MSR_IA32_SPEC_CTRL,
bf8c55d8
CP		 1151 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1152 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1153 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1154 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1155 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1156 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
6e3ba4ab
TX		 1157 MSR_IA32_UMWAIT_CONTROL,
1158
e2ada66e
JM		 1159 MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1,
1160 MSR_ARCH_PERFMON_FIXED_CTR0 + 2, MSR_ARCH_PERFMON_FIXED_CTR0 + 3,
1161 MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS,
1162 MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1163 MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1,
1164 MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3,
1165 MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5,
1166 MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7,
1167 MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9,
1168 MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11,
1169 MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13,
1170 MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15,
1171 MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17,
1172 MSR_ARCH_PERFMON_PERFCTR0 + 18, MSR_ARCH_PERFMON_PERFCTR0 + 19,
1173 MSR_ARCH_PERFMON_PERFCTR0 + 20, MSR_ARCH_PERFMON_PERFCTR0 + 21,
1174 MSR_ARCH_PERFMON_PERFCTR0 + 22, MSR_ARCH_PERFMON_PERFCTR0 + 23,
1175 MSR_ARCH_PERFMON_PERFCTR0 + 24, MSR_ARCH_PERFMON_PERFCTR0 + 25,
1176 MSR_ARCH_PERFMON_PERFCTR0 + 26, MSR_ARCH_PERFMON_PERFCTR0 + 27,
1177 MSR_ARCH_PERFMON_PERFCTR0 + 28, MSR_ARCH_PERFMON_PERFCTR0 + 29,
1178 MSR_ARCH_PERFMON_PERFCTR0 + 30, MSR_ARCH_PERFMON_PERFCTR0 + 31,
1179 MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1,
1180 MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3,
1181 MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5,
1182 MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7,
1183 MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9,
1184 MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11,
1185 MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13,
1186 MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15,
1187 MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17,
1188 MSR_ARCH_PERFMON_EVENTSEL0 + 18, MSR_ARCH_PERFMON_EVENTSEL0 + 19,
1189 MSR_ARCH_PERFMON_EVENTSEL0 + 20, MSR_ARCH_PERFMON_EVENTSEL0 + 21,
1190 MSR_ARCH_PERFMON_EVENTSEL0 + 22, MSR_ARCH_PERFMON_EVENTSEL0 + 23,
1191 MSR_ARCH_PERFMON_EVENTSEL0 + 24, MSR_ARCH_PERFMON_EVENTSEL0 + 25,
1192 MSR_ARCH_PERFMON_EVENTSEL0 + 26, MSR_ARCH_PERFMON_EVENTSEL0 + 27,
1193 MSR_ARCH_PERFMON_EVENTSEL0 + 28, MSR_ARCH_PERFMON_EVENTSEL0 + 29,
1194 MSR_ARCH_PERFMON_EVENTSEL0 + 30, MSR_ARCH_PERFMON_EVENTSEL0 + 31,
043405e1
CO		 1195};
1196
1197static unsigned num_msrs_to_save;
1198
62ef68bb
PB		 1199static u32 emulated_msrs[] = {
1200 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1201 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1202 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1203 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
72c139ba 1204 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
e7d9513b
AS		 1205 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1206 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 1207 HV_X64_MSR_RESET,
11c4b1ca 1208 HV_X64_MSR_VP_INDEX,
9eec50b8 1209 HV_X64_MSR_VP_RUNTIME,
5c919412 1210 HV_X64_MSR_SCONTROL,
1f4b34f8 1211 HV_X64_MSR_STIMER0_CONFIG,
d4abc577 1212 HV_X64_MSR_VP_ASSIST_PAGE,
a2e164e7
VK		 1213 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1214 HV_X64_MSR_TSC_EMULATION_STATUS,
1215
1216 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
62ef68bb
PB		 1217 MSR_KVM_PV_EOI_EN,
1218
ba904635 1219 MSR_IA32_TSC_ADJUST,
a3e06bbe 1220 MSR_IA32_TSCDEADLINE,
2bdb76c0 1221 MSR_IA32_ARCH_CAPABILITIES,
043405e1 1222 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1223 MSR_IA32_MCG_STATUS,
1224 MSR_IA32_MCG_CTL,
c45dcc71 1225 MSR_IA32_MCG_EXT_CTL,
64d60670 1226 MSR_IA32_SMBASE,
52797bf9 1227 MSR_SMI_COUNT,
db2336a8
KH		 1228 MSR_PLATFORM_INFO,
1229 MSR_MISC_FEATURES_ENABLES,
bc226f07 1230 MSR_AMD64_VIRT_SPEC_CTRL,
6c6a2ab9 1231 MSR_IA32_POWER_CTL,
191c8137 1232
95c5c7c7
PB		 1233 /*
1234 * The following list leaves out MSRs whose values are determined
1235 * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs.
1236 * We always support the "true" VMX control MSRs, even if the host
1237 * processor does not, so I am putting these registers here rather
1238 * than in msrs_to_save.
1239 */
1240 MSR_IA32_VMX_BASIC,
1241 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1242 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1243 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1244 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1245 MSR_IA32_VMX_MISC,
1246 MSR_IA32_VMX_CR0_FIXED0,
1247 MSR_IA32_VMX_CR4_FIXED0,
1248 MSR_IA32_VMX_VMCS_ENUM,
1249 MSR_IA32_VMX_PROCBASED_CTLS2,
1250 MSR_IA32_VMX_EPT_VPID_CAP,
1251 MSR_IA32_VMX_VMFUNC,
1252
191c8137 1253 MSR_K7_HWCR,
2d5ba19b 1254 MSR_KVM_POLL_CONTROL,
043405e1
CO		 1255};
1256
62ef68bb
PB		 1257static unsigned num_emulated_msrs;
1258
801e459a
TL		 1259/*
1260 * List of msr numbers which are used to expose MSR-based features that
1261 * can be used by a hypervisor to validate requested CPU features.
1262 */
1263static u32 msr_based_features[] = {
1389309c
PB		 1264 MSR_IA32_VMX_BASIC,
1265 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1266 MSR_IA32_VMX_PINBASED_CTLS,
1267 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1268 MSR_IA32_VMX_PROCBASED_CTLS,
1269 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1270 MSR_IA32_VMX_EXIT_CTLS,
1271 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1272 MSR_IA32_VMX_ENTRY_CTLS,
1273 MSR_IA32_VMX_MISC,
1274 MSR_IA32_VMX_CR0_FIXED0,
1275 MSR_IA32_VMX_CR0_FIXED1,
1276 MSR_IA32_VMX_CR4_FIXED0,
1277 MSR_IA32_VMX_CR4_FIXED1,
1278 MSR_IA32_VMX_VMCS_ENUM,
1279 MSR_IA32_VMX_PROCBASED_CTLS2,
1280 MSR_IA32_VMX_EPT_VPID_CAP,
1281 MSR_IA32_VMX_VMFUNC,
1282
d1d93fa9 1283 MSR_F10H_DECFG,
518e7b94 1284 MSR_IA32_UCODE_REV,
cd283252 1285 MSR_IA32_ARCH_CAPABILITIES,
801e459a
TL		 1286};
1287
1288static unsigned int num_msr_based_features;
1289
4d22c17c 1290static u64 kvm_get_arch_capabilities(void)
5b76a3cf 1291{
4d22c17c 1292 u64 data = 0;
5b76a3cf 1293
4d22c17c
XL		 1294 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1295 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data);
5b76a3cf
PB		 1296
1297 /*
1298 * If we're doing cache flushes (either "always" or "cond")
1299 * we will do one whenever the guest does a vmlaunch/vmresume.
1300 * If an outer hypervisor is doing the cache flush for us
1301 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1302 * capability to the guest too, and if EPT is disabled we're not
1303 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1304 * require a nested hypervisor to do a flush of its own.
1305 */
1306 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1307 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1308
0c54914d
PB		 1309 if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN))
1310 data |= ARCH_CAP_RDCL_NO;
1311 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1312 data |= ARCH_CAP_SSB_NO;
1313 if (!boot_cpu_has_bug(X86_BUG_MDS))
1314 data |= ARCH_CAP_MDS_NO;
1315
5b76a3cf
PB		 1316 return data;
1317}
5b76a3cf 1318
66421c1e
WL		 1319static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1320{
1321 switch (msr->index) {
cd283252 1322 case MSR_IA32_ARCH_CAPABILITIES:
5b76a3cf
PB		 1323 msr->data = kvm_get_arch_capabilities();
1324 break;
1325 case MSR_IA32_UCODE_REV:
cd283252 1326 rdmsrl_safe(msr->index, &msr->data);
518e7b94 1327 break;
66421c1e
WL		 1328 default:
1329 if (kvm_x86_ops->get_msr_feature(msr))
1330 return 1;
1331 }
1332 return 0;
1333}
1334
801e459a
TL		 1335static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1336{
1337 struct kvm_msr_entry msr;
66421c1e 1338 int r;
801e459a
TL		 1339
1340 msr.index = index;
66421c1e
WL		 1341 r = kvm_get_msr_feature(&msr);
1342 if (r)
1343 return r;
801e459a
TL		 1344
1345 *data = msr.data;
1346
1347 return 0;
1348}
1349
11988499 1350static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1351{
1b4d56b8 1352 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
11988499 1353 return false;
1b2fd70c 1354
1b4d56b8 1355 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
11988499 1356 return false;
d8017474 1357
0a629563
SC		 1358 if (efer & (EFER_LME | EFER_LMA) &&
1359 !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1360 return false;
1361
1362 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1363 return false;
d8017474 1364
384bb783 1365 return true;
11988499
SC		 1366
1367}
1368bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1369{
1370 if (efer & efer_reserved_bits)
1371 return false;
1372
1373 return __kvm_valid_efer(vcpu, efer);
384bb783
JK		 1374}
1375EXPORT_SYMBOL_GPL(kvm_valid_efer);
1376
11988499 1377static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
384bb783
JK		 1378{
1379 u64 old_efer = vcpu->arch.efer;
11988499 1380 u64 efer = msr_info->data;
384bb783 1381
11988499 1382 if (efer & efer_reserved_bits)
66f61c92 1383 return 1;
384bb783 1384
11988499
SC		 1385 if (!msr_info->host_initiated) {
1386 if (!__kvm_valid_efer(vcpu, efer))
1387 return 1;
1388
1389 if (is_paging(vcpu) &&
1390 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1391 return 1;
1392 }
384bb783 1393
15c4a640 1394 efer &= ~EFER_LMA;
f6801dff 1395 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1396
a3d204e2
SY		 1397 kvm_x86_ops->set_efer(vcpu, efer);
1398
aad82703
SY		 1399 /* Update reserved bits */
1400 if ((efer ^ old_efer) & EFER_NX)
1401 kvm_mmu_reset_context(vcpu);
1402
b69e8cae 1403 return 0;
15c4a640
CO		 1404}
1405
f2b4b7dd
JR		 1406void kvm_enable_efer_bits(u64 mask)
1407{
1408 efer_reserved_bits &= ~mask;
1409}
1410EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1411
15c4a640 1412/*
f20935d8
SC		 1413 * Write @data into the MSR specified by @index. Select MSR specific fault
1414 * checks are bypassed if @host_initiated is %true.
15c4a640
CO		 1415 * Returns 0 on success, non-0 otherwise.
1416 * Assumes vcpu_load() was already called.
1417 */
f20935d8
SC		 1418static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data,
1419 bool host_initiated)
15c4a640 1420{
f20935d8
SC		 1421 struct msr_data msr;
1422
1423 switch (index) {
854e8bb1
NA		 1424 case MSR_FS_BASE:
1425 case MSR_GS_BASE:
1426 case MSR_KERNEL_GS_BASE:
1427 case MSR_CSTAR:
1428 case MSR_LSTAR:
f20935d8 1429 if (is_noncanonical_address(data, vcpu))
854e8bb1
NA		 1430 return 1;
1431 break;
1432 case MSR_IA32_SYSENTER_EIP:
1433 case MSR_IA32_SYSENTER_ESP:
1434 /*
1435 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1436 * non-canonical address is written on Intel but not on
1437 * AMD (which ignores the top 32-bits, because it does
1438 * not implement 64-bit SYSENTER).
1439 *
1440 * 64-bit code should hence be able to write a non-canonical
1441 * value on AMD. Making the address canonical ensures that
1442 * vmentry does not fail on Intel after writing a non-canonical
1443 * value, and that something deterministic happens if the guest
1444 * invokes 64-bit SYSENTER.
1445 */
f20935d8 1446 data = get_canonical(data, vcpu_virt_addr_bits(vcpu));
854e8bb1 1447 }
f20935d8
SC		 1448
1449 msr.data = data;
1450 msr.index = index;
1451 msr.host_initiated = host_initiated;
1452
1453 return kvm_x86_ops->set_msr(vcpu, &msr);
15c4a640
CO		 1454}
1455
313a3dc7 1456/*
f20935d8
SC		 1457 * Read the MSR specified by @index into @data. Select MSR specific fault
1458 * checks are bypassed if @host_initiated is %true.
1459 * Returns 0 on success, non-0 otherwise.
1460 * Assumes vcpu_load() was already called.
313a3dc7 1461 */
f20935d8
SC		 1462static int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data,
1463 bool host_initiated)
609e36d3
PB		 1464{
1465 struct msr_data msr;
f20935d8 1466 int ret;
609e36d3
PB		 1467
1468 msr.index = index;
f20935d8 1469 msr.host_initiated = host_initiated;
609e36d3 1470
f20935d8
SC		 1471 ret = kvm_x86_ops->get_msr(vcpu, &msr);
1472 if (!ret)
1473 *data = msr.data;
1474 return ret;
609e36d3
PB		 1475}
1476
f20935d8 1477int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data)
313a3dc7 1478{
f20935d8
SC		 1479 return __kvm_get_msr(vcpu, index, data, false);
1480}
1481EXPORT_SYMBOL_GPL(kvm_get_msr);
8fe8ab46 1482
f20935d8
SC		 1483int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data)
1484{
1485 return __kvm_set_msr(vcpu, index, data, false);
1486}
1487EXPORT_SYMBOL_GPL(kvm_set_msr);
1488
1edce0a9
SC		 1489int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu)
1490{
1491 u32 ecx = kvm_rcx_read(vcpu);
1492 u64 data;
1493
1494 if (kvm_get_msr(vcpu, ecx, &data)) {
1495 trace_kvm_msr_read_ex(ecx);
1496 kvm_inject_gp(vcpu, 0);
1497 return 1;
1498 }
1499
1500 trace_kvm_msr_read(ecx, data);
1501
1502 kvm_rax_write(vcpu, data & -1u);
1503 kvm_rdx_write(vcpu, (data >> 32) & -1u);
1504 return kvm_skip_emulated_instruction(vcpu);
1505}
1506EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr);
1507
1508int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu)
1509{
1510 u32 ecx = kvm_rcx_read(vcpu);
1511 u64 data = kvm_read_edx_eax(vcpu);
1512
1513 if (kvm_set_msr(vcpu, ecx, data)) {
1514 trace_kvm_msr_write_ex(ecx, data);
1515 kvm_inject_gp(vcpu, 0);
1516 return 1;
1517 }
1518
1519 trace_kvm_msr_write(ecx, data);
1520 return kvm_skip_emulated_instruction(vcpu);
1521}
1522EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr);
1523
f20935d8
SC		 1524/*
1525 * Adapt set_msr() to msr_io()'s calling convention
1526 */
1527static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1528{
1529 return __kvm_get_msr(vcpu, index, data, true);
1530}
1531
1532static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1533{
1534 return __kvm_set_msr(vcpu, index, *data, true);
313a3dc7
CO		 1535}
1536
16e8d74d
MT		 1537#ifdef CONFIG_X86_64
1538struct pvclock_gtod_data {
1539 seqcount_t seq;
1540
1541 struct { /* extract of a clocksource struct */
1542 int vclock_mode;
a5a1d1c2
TG		 1543 u64 cycle_last;
1544 u64 mask;
16e8d74d
MT		 1545 u32 mult;
1546 u32 shift;
1547 } clock;
1548
cbcf2dd3
TG		 1549 u64 boot_ns;
1550 u64 nsec_base;
55dd00a7 1551 u64 wall_time_sec;
16e8d74d
MT		 1552};
1553
1554static struct pvclock_gtod_data pvclock_gtod_data;
1555
1556static void update_pvclock_gtod(struct timekeeper *tk)
1557{
1558 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1559 u64 boot_ns;
1560
876e7881 1561 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1562
1563 write_seqcount_begin(&vdata->seq);
1564
1565 /* copy pvclock gtod data */
876e7881
PZ		 1566 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1567 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1568 vdata->clock.mask = tk->tkr_mono.mask;
1569 vdata->clock.mult = tk->tkr_mono.mult;
1570 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1571
cbcf2dd3 1572 vdata->boot_ns = boot_ns;
876e7881 1573 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1574
55dd00a7
MT		 1575 vdata->wall_time_sec = tk->xtime_sec;
1576
16e8d74d
MT		 1577 write_seqcount_end(&vdata->seq);
1578}
1579#endif
1580
bab5bb39
NK		 1581void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1582{
bab5bb39 1583 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
4d151bf3 1584 kvm_vcpu_kick(vcpu);
bab5bb39 1585}
16e8d74d 1586
18068523
GOC		 1587static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1588{
9ed3c444
AK		 1589 int version;
1590 int r;
50d0a0f9 1591 struct pvclock_wall_clock wc;
87aeb54f 1592 struct timespec64 boot;
18068523
GOC		 1593
1594 if (!wall_clock)
1595 return;
1596
9ed3c444
AK		 1597 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1598 if (r)
1599 return;
1600
1601 if (version & 1)
1602 ++version; /* first time write, random junk */
1603
1604 ++version;
18068523 1605
1dab1345
NK		 1606 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1607 return;
18068523 1608
50d0a0f9
GH		 1609 /*
1610 * The guest calculates current wall clock time by adding
34c238a1 1611 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1612 * wall clock specified here. guest system time equals host
1613 * system time for us, thus we must fill in host boot time here.
1614 */
87aeb54f 1615 getboottime64(&boot);
50d0a0f9 1616
4b648665 1617 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1618 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1619 boot = timespec64_sub(boot, ts);
4b648665 1620 }
87aeb54f 1621 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1622 wc.nsec = boot.tv_nsec;
1623 wc.version = version;
18068523
GOC		 1624
1625 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1626
1627 version++;
1628 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1629}
1630
50d0a0f9
GH		 1631static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1632{
b51012de
PB		 1633 do_shl32_div32(dividend, divisor);
1634 return dividend;
50d0a0f9
GH		 1635}
1636
3ae13faa 1637static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1638 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1639{
5f4e3f88 1640 uint64_t scaled64;
50d0a0f9
GH		 1641 int32_t shift = 0;
1642 uint64_t tps64;
1643 uint32_t tps32;
1644
3ae13faa
PB		 1645 tps64 = base_hz;
1646 scaled64 = scaled_hz;
50933623 1647 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1648 tps64 >>= 1;
1649 shift--;
1650 }
1651
1652 tps32 = (uint32_t)tps64;
50933623
JK		 1653 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1654 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1655 scaled64 >>= 1;
1656 else
1657 tps32 <<= 1;
50d0a0f9
GH		 1658 shift++;
1659 }
1660
5f4e3f88
ZA		 1661 *pshift = shift;
1662 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9
GH		 1663}
1664
d828199e 1665#ifdef CONFIG_X86_64
16e8d74d 1666static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1667#endif
16e8d74d 1668
c8076604 1669static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1670static unsigned long max_tsc_khz;
c8076604 1671
cc578287 1672static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1673{
cc578287
ZA		 1674 u64 v = (u64)khz * (1000000 + ppm);
1675 do_div(v, 1000000);
1676 return v;
1e993611
JR		 1677}
1678
381d585c
HZ		 1679static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1680{
1681 u64 ratio;
1682
1683 /* Guest TSC same frequency as host TSC? */
1684 if (!scale) {
1685 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1686 return 0;
1687 }
1688
1689 /* TSC scaling supported? */
1690 if (!kvm_has_tsc_control) {
1691 if (user_tsc_khz > tsc_khz) {
1692 vcpu->arch.tsc_catchup = 1;
1693 vcpu->arch.tsc_always_catchup = 1;
1694 return 0;
1695 } else {
3f16a5c3 1696 pr_warn_ratelimited("user requested TSC rate below hardware speed\n");
381d585c
HZ		 1697 return -1;
1698 }
1699 }
1700
1701 /* TSC scaling required - calculate ratio */
1702 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1703 user_tsc_khz, tsc_khz);
1704
1705 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
3f16a5c3
PB		 1706 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1707 user_tsc_khz);
381d585c
HZ		 1708 return -1;
1709 }
1710
1711 vcpu->arch.tsc_scaling_ratio = ratio;
1712 return 0;
1713}
1714
4941b8cb 1715static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1716{
cc578287
ZA		 1717 u32 thresh_lo, thresh_hi;
1718 int use_scaling = 0;
217fc9cf 1719
03ba32ca 1720 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1721 if (user_tsc_khz == 0) {
ad721883
HZ		 1722 /* set tsc_scaling_ratio to a safe value */
1723 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1724 return -1;
ad721883 1725 }
03ba32ca 1726
c285545f 1727 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1728 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1729 &vcpu->arch.virtual_tsc_shift,
1730 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1731 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1732
1733 /*
1734 * Compute the variation in TSC rate which is acceptable
1735 * within the range of tolerance and decide if the
1736 * rate being applied is within that bounds of the hardware
1737 * rate. If so, no scaling or compensation need be done.
1738 */
1739 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1740 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1741 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1742 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1743 use_scaling = 1;
1744 }
4941b8cb 1745 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1746}
1747
1748static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1749{
e26101b1 1750 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1751 vcpu->arch.virtual_tsc_mult,
1752 vcpu->arch.virtual_tsc_shift);
e26101b1 1753 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1754 return tsc;
1755}
1756
b0c39dc6
VK		 1757static inline int gtod_is_based_on_tsc(int mode)
1758{
1759 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1760}
1761
69b0049a 1762static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1763{
1764#ifdef CONFIG_X86_64
1765 bool vcpus_matched;
b48aa97e
MT		 1766 struct kvm_arch *ka = &vcpu->kvm->arch;
1767 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1768
1769 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1770 atomic_read(&vcpu->kvm->online_vcpus));
1771
7f187922
MT		 1772 /*
1773 * Once the masterclock is enabled, always perform request in
1774 * order to update it.
1775 *
1776 * In order to enable masterclock, the host clocksource must be TSC
1777 * and the vcpus need to have matched TSCs. When that happens,
1778 * perform request to enable masterclock.
1779 */
1780 if (ka->use_master_clock ||
b0c39dc6 1781 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
b48aa97e
MT		 1782 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1783
1784 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1785 atomic_read(&vcpu->kvm->online_vcpus),
1786 ka->use_master_clock, gtod->clock.vclock_mode);
1787#endif
1788}
1789
ba904635
WA		 1790static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1791{
e79f245d 1792 u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
ba904635
WA		 1793 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1794}
1795
35181e86
HZ		 1796/*
1797 * Multiply tsc by a fixed point number represented by ratio.
1798 *
1799 * The most significant 64-N bits (mult) of ratio represent the
1800 * integral part of the fixed point number; the remaining N bits
1801 * (frac) represent the fractional part, ie. ratio represents a fixed
1802 * point number (mult + frac * 2^(-N)).
1803 *
1804 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1805 */
1806static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1807{
1808 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1809}
1810
1811u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1812{
1813 u64 _tsc = tsc;
1814 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1815
1816 if (ratio != kvm_default_tsc_scaling_ratio)
1817 _tsc = __scale_tsc(ratio, tsc);
1818
1819 return _tsc;
1820}
1821EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1822
07c1419a
HZ		 1823static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1824{
1825 u64 tsc;
1826
1827 tsc = kvm_scale_tsc(vcpu, rdtsc());
1828
1829 return target_tsc - tsc;
1830}
1831
4ba76538
HZ		 1832u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1833{
e79f245d
KA		 1834 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1835
1836 return tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1837}
1838EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1839
a545ab6a
LC		 1840static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1841{
326e7425 1842 vcpu->arch.tsc_offset = kvm_x86_ops->write_l1_tsc_offset(vcpu, offset);
a545ab6a
LC		 1843}
1844
b0c39dc6
VK		 1845static inline bool kvm_check_tsc_unstable(void)
1846{
1847#ifdef CONFIG_X86_64
1848 /*
1849 * TSC is marked unstable when we're running on Hyper-V,
1850 * 'TSC page' clocksource is good.
1851 */
1852 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1853 return false;
1854#endif
1855 return check_tsc_unstable();
1856}
1857
8fe8ab46 1858void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1859{
1860 struct kvm *kvm = vcpu->kvm;
f38e098f 1861 u64 offset, ns, elapsed;
99e3e30a 1862 unsigned long flags;
b48aa97e 1863 bool matched;
0d3da0d2 1864 bool already_matched;
8fe8ab46 1865 u64 data = msr->data;
c5e8ec8e 1866 bool synchronizing = false;
99e3e30a 1867
038f8c11 1868 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1869 offset = kvm_compute_tsc_offset(vcpu, data);
9285ec4c 1870 ns = ktime_get_boottime_ns();
f38e098f 1871 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1872
03ba32ca 1873 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1874 if (data == 0 && msr->host_initiated) {
1875 /*
1876 * detection of vcpu initialization -- need to sync
1877 * with other vCPUs. This particularly helps to keep
1878 * kvm_clock stable after CPU hotplug
1879 */
1880 synchronizing = true;
1881 } else {
1882 u64 tsc_exp = kvm->arch.last_tsc_write +
1883 nsec_to_cycles(vcpu, elapsed);
1884 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1885 /*
1886 * Special case: TSC write with a small delta (1 second)
1887 * of virtual cycle time against real time is
1888 * interpreted as an attempt to synchronize the CPU.
1889 */
1890 synchronizing = data < tsc_exp + tsc_hz &&
1891 data + tsc_hz > tsc_exp;
1892 }
c5e8ec8e 1893 }
f38e098f
ZA		 1894
1895 /*
5d3cb0f6
ZA		 1896 * For a reliable TSC, we can match TSC offsets, and for an unstable
1897 * TSC, we add elapsed time in this computation. We could let the
1898 * compensation code attempt to catch up if we fall behind, but
1899 * it's better to try to match offsets from the beginning.
1900 */
c5e8ec8e 1901 if (synchronizing &&
5d3cb0f6 1902 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
b0c39dc6 1903 if (!kvm_check_tsc_unstable()) {
e26101b1 1904 offset = kvm->arch.cur_tsc_offset;
f38e098f 1905 } else {
857e4099 1906 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1907 data += delta;
07c1419a 1908 offset = kvm_compute_tsc_offset(vcpu, data);
f38e098f 1909 }
b48aa97e 1910 matched = true;
0d3da0d2 1911 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1912 } else {
1913 /*
1914 * We split periods of matched TSC writes into generations.
1915 * For each generation, we track the original measured
1916 * nanosecond time, offset, and write, so if TSCs are in
1917 * sync, we can match exact offset, and if not, we can match
4a969980 1918 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1919 *
1920 * These values are tracked in kvm->arch.cur_xxx variables.
1921 */
1922 kvm->arch.cur_tsc_generation++;
1923 kvm->arch.cur_tsc_nsec = ns;
1924 kvm->arch.cur_tsc_write = data;
1925 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1926 matched = false;
f38e098f 1927 }
e26101b1
ZA		 1928
1929 /*
1930 * We also track th most recent recorded KHZ, write and time to
1931 * allow the matching interval to be extended at each write.
1932 */
f38e098f
ZA		 1933 kvm->arch.last_tsc_nsec = ns;
1934 kvm->arch.last_tsc_write = data;
5d3cb0f6 1935 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1936
b183aa58 1937 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1938
1939 /* Keep track of which generation this VCPU has synchronized to */
1940 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1941 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1942 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1943
d6321d49 1944 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
ba904635 1945 update_ia32_tsc_adjust_msr(vcpu, offset);
d6321d49 1946
a545ab6a 1947 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1948 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1949
1950 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1951 if (!matched) {
b48aa97e 1952 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1953 } else if (!already_matched) {
1954 kvm->arch.nr_vcpus_matched_tsc++;
1955 }
b48aa97e
MT		 1956
1957 kvm_track_tsc_matching(vcpu);
1958 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1959}
e26101b1 1960
99e3e30a
ZA		 1961EXPORT_SYMBOL_GPL(kvm_write_tsc);
1962
58ea6767
HZ		 1963static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1964 s64 adjustment)
1965{
326e7425
LS		 1966 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1967 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
58ea6767
HZ		 1968}
1969
1970static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1971{
1972 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1973 WARN_ON(adjustment < 0);
1974 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1975 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1976}
1977
d828199e
MT		 1978#ifdef CONFIG_X86_64
1979
a5a1d1c2 1980static u64 read_tsc(void)
d828199e 1981{
a5a1d1c2 1982 u64 ret = (u64)rdtsc_ordered();
03b9730b 1983 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1984
1985 if (likely(ret >= last))
1986 return ret;
1987
1988 /*
1989 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1990 * predictable (it's just a function of time and the likely is
d828199e
MT		 1991 * very likely) and there's a data dependence, so force GCC
1992 * to generate a branch instead. I don't barrier() because
1993 * we don't actually need a barrier, and if this function
1994 * ever gets inlined it will generate worse code.
1995 */
1996 asm volatile ("");
1997 return last;
1998}
1999
b0c39dc6 2000static inline u64 vgettsc(u64 *tsc_timestamp, int *mode)
d828199e
MT		 2001{
2002 long v;
2003 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
b0c39dc6
VK		 2004 u64 tsc_pg_val;
2005
2006 switch (gtod->clock.vclock_mode) {
2007 case VCLOCK_HVCLOCK:
2008 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
2009 tsc_timestamp);
2010 if (tsc_pg_val != U64_MAX) {
2011 /* TSC page valid */
2012 *mode = VCLOCK_HVCLOCK;
2013 v = (tsc_pg_val - gtod->clock.cycle_last) &
2014 gtod->clock.mask;
2015 } else {
2016 /* TSC page invalid */
2017 *mode = VCLOCK_NONE;
2018 }
2019 break;
2020 case VCLOCK_TSC:
2021 *mode = VCLOCK_TSC;
2022 *tsc_timestamp = read_tsc();
2023 v = (*tsc_timestamp - gtod->clock.cycle_last) &
2024 gtod->clock.mask;
2025 break;
2026 default:
2027 *mode = VCLOCK_NONE;
2028 }
d828199e 2029
b0c39dc6
VK		 2030 if (*mode == VCLOCK_NONE)
2031 *tsc_timestamp = v = 0;
d828199e 2032
d828199e
MT		 2033 return v * gtod->clock.mult;
2034}
2035
b0c39dc6 2036static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp)
d828199e 2037{
cbcf2dd3 2038 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 2039 unsigned long seq;
d828199e 2040 int mode;
cbcf2dd3 2041 u64 ns;
d828199e 2042
d828199e
MT		 2043 do {
2044 seq = read_seqcount_begin(&gtod->seq);
cbcf2dd3 2045 ns = gtod->nsec_base;
b0c39dc6 2046 ns += vgettsc(tsc_timestamp, &mode);
d828199e 2047 ns >>= gtod->clock.shift;
cbcf2dd3 2048 ns += gtod->boot_ns;
d828199e 2049 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 2050 *t = ns;
d828199e
MT		 2051
2052 return mode;
2053}
2054
899a31f5 2055static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
55dd00a7
MT		 2056{
2057 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2058 unsigned long seq;
2059 int mode;
2060 u64 ns;
2061
2062 do {
2063 seq = read_seqcount_begin(&gtod->seq);
55dd00a7
MT		 2064 ts->tv_sec = gtod->wall_time_sec;
2065 ns = gtod->nsec_base;
b0c39dc6 2066 ns += vgettsc(tsc_timestamp, &mode);
55dd00a7
MT		 2067 ns >>= gtod->clock.shift;
2068 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
2069
2070 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
2071 ts->tv_nsec = ns;
2072
2073 return mode;
2074}
2075
b0c39dc6
VK		 2076/* returns true if host is using TSC based clocksource */
2077static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
d828199e 2078{
d828199e 2079 /* checked again under seqlock below */
b0c39dc6 2080 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
d828199e
MT		 2081 return false;
2082
b0c39dc6
VK		 2083 return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns,
2084 tsc_timestamp));
d828199e 2085}
55dd00a7 2086
b0c39dc6 2087/* returns true if host is using TSC based clocksource */
899a31f5 2088static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
b0c39dc6 2089 u64 *tsc_timestamp)
55dd00a7
MT		 2090{
2091 /* checked again under seqlock below */
b0c39dc6 2092 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
55dd00a7
MT		 2093 return false;
2094
b0c39dc6 2095 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
55dd00a7 2096}
d828199e
MT		 2097#endif
2098
2099/*
2100 *
b48aa97e
MT		 2101 * Assuming a stable TSC across physical CPUS, and a stable TSC
2102 * across virtual CPUs, the following condition is possible.
2103 * Each numbered line represents an event visible to both
d828199e
MT		 2104 * CPUs at the next numbered event.
2105 *
2106 * "timespecX" represents host monotonic time. "tscX" represents
2107 * RDTSC value.
2108 *
2109 * VCPU0 on CPU0 | VCPU1 on CPU1
2110 *
2111 * 1. read timespec0,tsc0
2112 * 2. | timespec1 = timespec0 + N
2113 * | tsc1 = tsc0 + M
2114 * 3. transition to guest | transition to guest
2115 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
2116 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
2117 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
2118 *
2119 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
2120 *
2121 * - ret0 < ret1
2122 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
2123 * ...
2124 * - 0 < N - M => M < N
2125 *
2126 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
2127 * always the case (the difference between two distinct xtime instances
2128 * might be smaller then the difference between corresponding TSC reads,
2129 * when updating guest vcpus pvclock areas).
2130 *
2131 * To avoid that problem, do not allow visibility of distinct
2132 * system_timestamp/tsc_timestamp values simultaneously: use a master
2133 * copy of host monotonic time values. Update that master copy
2134 * in lockstep.
2135 *
b48aa97e 2136 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 2137 *
2138 */
2139
2140static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
2141{
2142#ifdef CONFIG_X86_64
2143 struct kvm_arch *ka = &kvm->arch;
2144 int vclock_mode;
b48aa97e
MT		 2145 bool host_tsc_clocksource, vcpus_matched;
2146
2147 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2148 atomic_read(&kvm->online_vcpus));
d828199e
MT		 2149
2150 /*
2151 * If the host uses TSC clock, then passthrough TSC as stable
2152 * to the guest.
2153 */
b48aa97e 2154 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 2155 &ka->master_kernel_ns,
2156 &ka->master_cycle_now);
2157
16a96021 2158 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
a826faf1 2159 && !ka->backwards_tsc_observed
54750f2c 2160 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 2161
d828199e
MT		 2162 if (ka->use_master_clock)
2163 atomic_set(&kvm_guest_has_master_clock, 1);
2164
2165 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 2166 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2167 vcpus_matched);
d828199e
MT		 2168#endif
2169}
2170
2860c4b1
PB		 2171void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2172{
2173 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2174}
2175
2e762ff7
MT		 2176static void kvm_gen_update_masterclock(struct kvm *kvm)
2177{
2178#ifdef CONFIG_X86_64
2179 int i;
2180 struct kvm_vcpu *vcpu;
2181 struct kvm_arch *ka = &kvm->arch;
2182
2183 spin_lock(&ka->pvclock_gtod_sync_lock);
2184 kvm_make_mclock_inprogress_request(kvm);
2185 /* no guest entries from this point */
2186 pvclock_update_vm_gtod_copy(kvm);
2187
2188 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 2189 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 2190
2191 /* guest entries allowed */
2192 kvm_for_each_vcpu(i, vcpu, kvm)
72875d8a 2193 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2e762ff7
MT		 2194
2195 spin_unlock(&ka->pvclock_gtod_sync_lock);
2196#endif
2197}
2198
e891a32e 2199u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 2200{
108b249c 2201 struct kvm_arch *ka = &kvm->arch;
8b953440 2202 struct pvclock_vcpu_time_info hv_clock;
e2c2206a 2203 u64 ret;
108b249c 2204
8b953440
PB		 2205 spin_lock(&ka->pvclock_gtod_sync_lock);
2206 if (!ka->use_master_clock) {
2207 spin_unlock(&ka->pvclock_gtod_sync_lock);
9285ec4c 2208 return ktime_get_boottime_ns() + ka->kvmclock_offset;
108b249c
PB		 2209 }
2210
8b953440
PB		 2211 hv_clock.tsc_timestamp = ka->master_cycle_now;
2212 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2213 spin_unlock(&ka->pvclock_gtod_sync_lock);
2214
e2c2206a
WL		 2215 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2216 get_cpu();
2217
e70b57a6
WL		 2218 if (__this_cpu_read(cpu_tsc_khz)) {
2219 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2220 &hv_clock.tsc_shift,
2221 &hv_clock.tsc_to_system_mul);
2222 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
2223 } else
9285ec4c 2224 ret = ktime_get_boottime_ns() + ka->kvmclock_offset;
e2c2206a
WL		 2225
2226 put_cpu();
2227
2228 return ret;
108b249c
PB		 2229}
2230
0d6dd2ff
PB		 2231static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
2232{
2233 struct kvm_vcpu_arch *vcpu = &v->arch;
2234 struct pvclock_vcpu_time_info guest_hv_clock;
2235
4e335d9e 2236 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
0d6dd2ff
PB		 2237 &guest_hv_clock, sizeof(guest_hv_clock))))
2238 return;
2239
2240 /* This VCPU is paused, but it's legal for a guest to read another
2241 * VCPU's kvmclock, so we really have to follow the specification where
2242 * it says that version is odd if data is being modified, and even after
2243 * it is consistent.
2244 *
2245 * Version field updates must be kept separate. This is because
2246 * kvm_write_guest_cached might use a "rep movs" instruction, and
2247 * writes within a string instruction are weakly ordered. So there
2248 * are three writes overall.
2249 *
2250 * As a small optimization, only write the version field in the first
2251 * and third write. The vcpu->pv_time cache is still valid, because the
2252 * version field is the first in the struct.
2253 */
2254 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2255
51c4b8bb
LA		 2256 if (guest_hv_clock.version & 1)
2257 ++guest_hv_clock.version; /* first time write, random junk */
2258
0d6dd2ff 2259 vcpu->hv_clock.version = guest_hv_clock.version + 1;
4e335d9e
PB		 2260 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2261 &vcpu->hv_clock,
2262 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 2263
2264 smp_wmb();
2265
2266 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
2267 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
2268
2269 if (vcpu->pvclock_set_guest_stopped_request) {
2270 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
2271 vcpu->pvclock_set_guest_stopped_request = false;
2272 }
2273
2274 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
2275
4e335d9e
PB		 2276 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2277 &vcpu->hv_clock,
2278 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 2279
2280 smp_wmb();
2281
2282 vcpu->hv_clock.version++;
4e335d9e
PB		 2283 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2284 &vcpu->hv_clock,
2285 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 2286}
2287
34c238a1 2288static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 2289{
78db6a50 2290 unsigned long flags, tgt_tsc_khz;
18068523 2291 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 2292 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 2293 s64 kernel_ns;
d828199e 2294 u64 tsc_timestamp, host_tsc;
51d59c6b 2295 u8 pvclock_flags;
d828199e
MT		 2296 bool use_master_clock;
2297
2298 kernel_ns = 0;
2299 host_tsc = 0;
18068523 2300
d828199e
MT		 2301 /*
2302 * If the host uses TSC clock, then passthrough TSC as stable
2303 * to the guest.
2304 */
2305 spin_lock(&ka->pvclock_gtod_sync_lock);
2306 use_master_clock = ka->use_master_clock;
2307 if (use_master_clock) {
2308 host_tsc = ka->master_cycle_now;
2309 kernel_ns = ka->master_kernel_ns;
2310 }
2311 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 2312
2313 /* Keep irq disabled to prevent changes to the clock */
2314 local_irq_save(flags);
78db6a50
PB		 2315 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2316 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 2317 local_irq_restore(flags);
2318 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2319 return 1;
2320 }
d828199e 2321 if (!use_master_clock) {
4ea1636b 2322 host_tsc = rdtsc();
9285ec4c 2323 kernel_ns = ktime_get_boottime_ns();
d828199e
MT		 2324 }
2325
4ba76538 2326 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 2327
c285545f
ZA		 2328 /*
2329 * We may have to catch up the TSC to match elapsed wall clock
2330 * time for two reasons, even if kvmclock is used.
2331 * 1) CPU could have been running below the maximum TSC rate
2332 * 2) Broken TSC compensation resets the base at each VCPU
2333 * entry to avoid unknown leaps of TSC even when running
2334 * again on the same CPU. This may cause apparent elapsed
2335 * time to disappear, and the guest to stand still or run
2336 * very slowly.
2337 */
2338 if (vcpu->tsc_catchup) {
2339 u64 tsc = compute_guest_tsc(v, kernel_ns);
2340 if (tsc > tsc_timestamp) {
f1e2b260 2341 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 2342 tsc_timestamp = tsc;
2343 }
50d0a0f9
GH		 2344 }
2345
18068523
GOC		 2346 local_irq_restore(flags);
2347
0d6dd2ff 2348 /* With all the info we got, fill in the values */
18068523 2349
78db6a50
PB		 2350 if (kvm_has_tsc_control)
2351 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2352
2353 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 2354 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 2355 &vcpu->hv_clock.tsc_shift,
2356 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 2357 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 2358 }
2359
1d5f066e 2360 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 2361 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 2362 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 2363
d828199e 2364 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 2365 pvclock_flags = 0;
d828199e
MT		 2366 if (use_master_clock)
2367 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2368
78c0337a
MT		 2369 vcpu->hv_clock.flags = pvclock_flags;
2370
095cf55d
PB		 2371 if (vcpu->pv_time_enabled)
2372 kvm_setup_pvclock_page(v);
2373 if (v == kvm_get_vcpu(v->kvm, 0))
2374 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 2375 return 0;
c8076604
GH		 2376}
2377
0061d53d
MT		 2378/*
2379 * kvmclock updates which are isolated to a given vcpu, such as
2380 * vcpu->cpu migration, should not allow system_timestamp from
2381 * the rest of the vcpus to remain static. Otherwise ntp frequency
2382 * correction applies to one vcpu's system_timestamp but not
2383 * the others.
2384 *
2385 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 2386 * We need to rate-limit these requests though, as they can
2387 * considerably slow guests that have a large number of vcpus.
2388 * The time for a remote vcpu to update its kvmclock is bound
2389 * by the delay we use to rate-limit the updates.
0061d53d
MT		 2390 */
2391
7e44e449
AJ		 2392#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2393
2394static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 2395{
2396 int i;
7e44e449
AJ		 2397 struct delayed_work *dwork = to_delayed_work(work);
2398 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2399 kvmclock_update_work);
2400 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 2401 struct kvm_vcpu *vcpu;
2402
2403 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 2404 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 2405 kvm_vcpu_kick(vcpu);
2406 }
2407}
2408
7e44e449
AJ		 2409static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2410{
2411 struct kvm *kvm = v->kvm;
2412
105b21bb 2413 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 2414 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2415 KVMCLOCK_UPDATE_DELAY);
2416}
2417
332967a3
AJ		 2418#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2419
2420static void kvmclock_sync_fn(struct work_struct *work)
2421{
2422 struct delayed_work *dwork = to_delayed_work(work);
2423 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2424 kvmclock_sync_work);
2425 struct kvm *kvm = container_of(ka, struct kvm, arch);
2426
630994b3
MT		 2427 if (!kvmclock_periodic_sync)
2428 return;
2429
332967a3
AJ		 2430 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2431 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2432 KVMCLOCK_SYNC_PERIOD);
2433}
2434
191c8137
BP		 2435/*
2436 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
2437 */
2438static bool can_set_mci_status(struct kvm_vcpu *vcpu)
2439{
2440 /* McStatusWrEn enabled? */
2441 if (guest_cpuid_is_amd(vcpu))
2442 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
2443
2444 return false;
2445}
2446
9ffd986c 2447static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2448{
890ca9ae
HY		 2449 u64 mcg_cap = vcpu->arch.mcg_cap;
2450 unsigned bank_num = mcg_cap & 0xff;
9ffd986c
WL		 2451 u32 msr = msr_info->index;
2452 u64 data = msr_info->data;
890ca9ae 2453
15c4a640 2454 switch (msr) {
15c4a640 2455 case MSR_IA32_MCG_STATUS:
890ca9ae 2456 vcpu->arch.mcg_status = data;
15c4a640 2457 break;
c7ac679c 2458 case MSR_IA32_MCG_CTL:
44883f01
PB		 2459 if (!(mcg_cap & MCG_CTL_P) &&
2460 (data || !msr_info->host_initiated))
890ca9ae
HY		 2461 return 1;
2462 if (data != 0 && data != ~(u64)0)
44883f01 2463 return 1;
890ca9ae
HY		 2464 vcpu->arch.mcg_ctl = data;
2465 break;
2466 default:
2467 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2468 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2469 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2470 /* only 0 or all 1s can be written to IA32_MCi_CTL
2471 * some Linux kernels though clear bit 10 in bank 4 to
2472 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2473 * this to avoid an uncatched #GP in the guest
2474 */
890ca9ae 2475 if ((offset & 0x3) == 0 &&
114be429 2476 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae 2477 return -1;
191c8137
BP		 2478
2479 /* MCi_STATUS */
9ffd986c 2480 if (!msr_info->host_initiated &&
191c8137
BP		 2481 (offset & 0x3) == 1 && data != 0) {
2482 if (!can_set_mci_status(vcpu))
2483 return -1;
2484 }
2485
890ca9ae
HY		 2486 vcpu->arch.mce_banks[offset] = data;
2487 break;
2488 }
2489 return 1;
2490 }
2491 return 0;
2492}
2493
ffde22ac
ES		 2494static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2495{
2496 struct kvm *kvm = vcpu->kvm;
2497 int lm = is_long_mode(vcpu);
2498 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2499 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2500 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2501 : kvm->arch.xen_hvm_config.blob_size_32;
2502 u32 page_num = data & ~PAGE_MASK;
2503 u64 page_addr = data & PAGE_MASK;
2504 u8 *page;
2505 int r;
2506
2507 r = -E2BIG;
2508 if (page_num >= blob_size)
2509 goto out;
2510 r = -ENOMEM;
ff5c2c03
SL		 2511 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2512 if (IS_ERR(page)) {
2513 r = PTR_ERR(page);
ffde22ac 2514 goto out;
ff5c2c03 2515 }
54bf36aa 2516 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2517 goto out_free;
2518 r = 0;
2519out_free:
2520 kfree(page);
2521out:
2522 return r;
2523}
2524
344d9588
GN		 2525static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2526{
2527 gpa_t gpa = data & ~0x3f;
2528
52a5c155
WL		 2529 /* Bits 3:5 are reserved, Should be zero */
2530 if (data & 0x38)
344d9588
GN		 2531 return 1;
2532
2533 vcpu->arch.apf.msr_val = data;
2534
2535 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2536 kvm_clear_async_pf_completion_queue(vcpu);
2537 kvm_async_pf_hash_reset(vcpu);
2538 return 0;
2539 }
2540
4e335d9e 2541 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
8f964525 2542 sizeof(u32)))
344d9588
GN		 2543 return 1;
2544
6adba527 2545 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
52a5c155 2546 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
344d9588
GN		 2547 kvm_async_pf_wakeup_all(vcpu);
2548 return 0;
2549}
2550
12f9a48f
GC		 2551static void kvmclock_reset(struct kvm_vcpu *vcpu)
2552{
0b79459b 2553 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2554}
2555
f38a7b75
WL		 2556static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2557{
2558 ++vcpu->stat.tlb_flush;
2559 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2560}
2561
c9aaa895
GC		 2562static void record_steal_time(struct kvm_vcpu *vcpu)
2563{
2564 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2565 return;
2566
4e335d9e 2567 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2568 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2569 return;
2570
f38a7b75
WL		 2571 /*
2572 * Doing a TLB flush here, on the guest's behalf, can avoid
2573 * expensive IPIs.
2574 */
b382f44e
WL		 2575 trace_kvm_pv_tlb_flush(vcpu->vcpu_id,
2576 vcpu->arch.st.steal.preempted & KVM_VCPU_FLUSH_TLB);
f38a7b75
WL		 2577 if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB)
2578 kvm_vcpu_flush_tlb(vcpu, false);
0b9f6c46 2579
35f3fae1
WL		 2580 if (vcpu->arch.st.steal.version & 1)
2581 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2582
2583 vcpu->arch.st.steal.version += 1;
2584
4e335d9e 2585 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2586 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2587
2588 smp_wmb();
2589
c54cdf14
LC		 2590 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2591 vcpu->arch.st.last_steal;
2592 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2593
4e335d9e 2594 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2595 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2596
2597 smp_wmb();
2598
2599 vcpu->arch.st.steal.version += 1;
c9aaa895 2600
4e335d9e 2601 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2602 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2603}
2604
8fe8ab46 2605int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2606{
5753785f 2607 bool pr = false;
8fe8ab46
WA		 2608 u32 msr = msr_info->index;
2609 u64 data = msr_info->data;
5753785f 2610
15c4a640 2611 switch (msr) {
2e32b719 2612 case MSR_AMD64_NB_CFG:
2e32b719
BP		 2613 case MSR_IA32_UCODE_WRITE:
2614 case MSR_VM_HSAVE_PA:
2615 case MSR_AMD64_PATCH_LOADER:
2616 case MSR_AMD64_BU_CFG2:
405a353a 2617 case MSR_AMD64_DC_CFG:
0e1b869f 2618 case MSR_F15H_EX_CFG:
2e32b719
BP		 2619 break;
2620
518e7b94
WL		 2621 case MSR_IA32_UCODE_REV:
2622 if (msr_info->host_initiated)
2623 vcpu->arch.microcode_version = data;
2624 break;
0cf9135b
SC		 2625 case MSR_IA32_ARCH_CAPABILITIES:
2626 if (!msr_info->host_initiated)
2627 return 1;
2628 vcpu->arch.arch_capabilities = data;
2629 break;
15c4a640 2630 case MSR_EFER:
11988499 2631 return set_efer(vcpu, msr_info);
8f1589d9
AP		 2632 case MSR_K7_HWCR:
2633 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2634 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2635 data &= ~(u64)0x8; /* ignore TLB cache disable */
191c8137
BP		 2636
2637 /* Handle McStatusWrEn */
2638 if (data == BIT_ULL(18)) {
2639 vcpu->arch.msr_hwcr = data;
2640 } else if (data != 0) {
a737f256
CD		 2641 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2642 data);
8f1589d9
AP		 2643 return 1;
2644 }
15c4a640 2645 break;
f7c6d140
AP		 2646 case MSR_FAM10H_MMIO_CONF_BASE:
2647 if (data != 0) {
a737f256
CD		 2648 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2649 "0x%llx\n", data);
f7c6d140
AP		 2650 return 1;
2651 }
15c4a640 2652 break;
b5e2fec0
AG		 2653 case MSR_IA32_DEBUGCTLMSR:
2654 if (!data) {
2655 /* We support the non-activated case already */
2656 break;
2657 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2658 /* Values other than LBR and BTF are vendor-specific,
2659 thus reserved and should throw a #GP */
2660 return 1;
2661 }
a737f256
CD		 2662 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2663 __func__, data);
b5e2fec0 2664 break;
9ba075a6 2665 case 0x200 ... 0x2ff:
ff53604b 2666 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2667 case MSR_IA32_APICBASE:
58cb628d 2668 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2669 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2670 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2671 case MSR_IA32_TSCDEADLINE:
2672 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2673 break;
ba904635 2674 case MSR_IA32_TSC_ADJUST:
d6321d49 2675 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
ba904635 2676 if (!msr_info->host_initiated) {
d913b904 2677 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2678 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2679 }
2680 vcpu->arch.ia32_tsc_adjust_msr = data;
2681 }
2682 break;
15c4a640 2683 case MSR_IA32_MISC_ENABLE:
511a8556
WL		 2684 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
2685 ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) {
2686 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
2687 return 1;
2688 vcpu->arch.ia32_misc_enable_msr = data;
2689 kvm_update_cpuid(vcpu);
2690 } else {
2691 vcpu->arch.ia32_misc_enable_msr = data;
2692 }
15c4a640 2693 break;
64d60670
PB		 2694 case MSR_IA32_SMBASE:
2695 if (!msr_info->host_initiated)
2696 return 1;
2697 vcpu->arch.smbase = data;
2698 break;
73f624f4
PB		 2699 case MSR_IA32_POWER_CTL:
2700 vcpu->arch.msr_ia32_power_ctl = data;
2701 break;
dd259935
PB		 2702 case MSR_IA32_TSC:
2703 kvm_write_tsc(vcpu, msr_info);
2704 break;
52797bf9
LA		 2705 case MSR_SMI_COUNT:
2706 if (!msr_info->host_initiated)
2707 return 1;
2708 vcpu->arch.smi_count = data;
2709 break;
11c6bffa 2710 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2711 case MSR_KVM_WALL_CLOCK:
2712 vcpu->kvm->arch.wall_clock = data;
2713 kvm_write_wall_clock(vcpu->kvm, data);
2714 break;
11c6bffa 2715 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2716 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2717 struct kvm_arch *ka = &vcpu->kvm->arch;
2718
12f9a48f 2719 kvmclock_reset(vcpu);
18068523 2720
54750f2c
MT		 2721 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2722 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2723
2724 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
1bd2009e 2725 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
54750f2c
MT		 2726
2727 ka->boot_vcpu_runs_old_kvmclock = tmp;
2728 }
2729
18068523 2730 vcpu->arch.time = data;
0061d53d 2731 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2732
2733 /* we verify if the enable bit is set... */
2734 if (!(data & 1))
2735 break;
2736
4e335d9e 2737 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2738 &vcpu->arch.pv_time, data & ~1ULL,
2739 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2740 vcpu->arch.pv_time_enabled = false;
2741 else
2742 vcpu->arch.pv_time_enabled = true;
32cad84f 2743
18068523
GOC		 2744 break;
2745 }
344d9588
GN		 2746 case MSR_KVM_ASYNC_PF_EN:
2747 if (kvm_pv_enable_async_pf(vcpu, data))
2748 return 1;
2749 break;
c9aaa895
GC		 2750 case MSR_KVM_STEAL_TIME:
2751
2752 if (unlikely(!sched_info_on()))
2753 return 1;
2754
2755 if (data & KVM_STEAL_RESERVED_MASK)
2756 return 1;
2757
4e335d9e 2758 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2759 data & KVM_STEAL_VALID_BITS,
2760 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2761 return 1;
2762
2763 vcpu->arch.st.msr_val = data;
2764
2765 if (!(data & KVM_MSR_ENABLED))
2766 break;
2767
c9aaa895
GC		 2768 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2769
2770 break;
ae7a2a3f 2771 case MSR_KVM_PV_EOI_EN:
72bbf935 2772 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8)))
ae7a2a3f
MT		 2773 return 1;
2774 break;
c9aaa895 2775
2d5ba19b
MT		 2776 case MSR_KVM_POLL_CONTROL:
2777 /* only enable bit supported */
2778 if (data & (-1ULL << 1))
2779 return 1;
2780
2781 vcpu->arch.msr_kvm_poll_control = data;
2782 break;
2783
890ca9ae
HY		 2784 case MSR_IA32_MCG_CTL:
2785 case MSR_IA32_MCG_STATUS:
81760dcc 2786 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
9ffd986c 2787 return set_msr_mce(vcpu, msr_info);
71db6023 2788
6912ac32
WH		 2789 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2790 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2791 pr = true; /* fall through */
2792 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2793 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2794 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2795 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2796
2797 if (pr || data != 0)
a737f256
CD		 2798 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2799 "0x%x data 0x%llx\n", msr, data);
5753785f 2800 break;
84e0cefa
JS		 2801 case MSR_K7_CLK_CTL:
2802 /*
2803 * Ignore all writes to this no longer documented MSR.
2804 * Writes are only relevant for old K7 processors,
2805 * all pre-dating SVM, but a recommended workaround from
4a969980 2806 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2807 * affected processor models on the command line, hence
2808 * the need to ignore the workaround.
2809 */
2810 break;
55cd8e5a 2811 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2812 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2813 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2814 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2815 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2816 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2817 case HV_X64_MSR_TSC_EMULATION_STATUS:
e7d9513b
AS		 2818 return kvm_hv_set_msr_common(vcpu, msr, data,
2819 msr_info->host_initiated);
91c9c3ed 2820 case MSR_IA32_BBL_CR_CTL3:
2821 /* Drop writes to this legacy MSR -- see rdmsr
2822 * counterpart for further detail.
2823 */
fab0aa3b
EM		 2824 if (report_ignored_msrs)
2825 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2826 msr, data);
91c9c3ed 2827 break;
2b036c6b 2828 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2829 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2830 return 1;
2831 vcpu->arch.osvw.length = data;
2832 break;
2833 case MSR_AMD64_OSVW_STATUS:
d6321d49 2834 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2835 return 1;
2836 vcpu->arch.osvw.status = data;
2837 break;
db2336a8
KH		 2838 case MSR_PLATFORM_INFO:
2839 if (!msr_info->host_initiated ||
db2336a8
KH		 2840 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2841 cpuid_fault_enabled(vcpu)))
2842 return 1;
2843 vcpu->arch.msr_platform_info = data;
2844 break;
2845 case MSR_MISC_FEATURES_ENABLES:
2846 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2847 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2848 !supports_cpuid_fault(vcpu)))
2849 return 1;
2850 vcpu->arch.msr_misc_features_enables = data;
2851 break;
15c4a640 2852 default:
ffde22ac
ES		 2853 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2854 return xen_hvm_config(vcpu, data);
c6702c9d 2855 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2856 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2857 if (!ignore_msrs) {
ae0f5499 2858 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2859 msr, data);
ed85c068
AP		 2860 return 1;
2861 } else {
fab0aa3b
EM		 2862 if (report_ignored_msrs)
2863 vcpu_unimpl(vcpu,
2864 "ignored wrmsr: 0x%x data 0x%llx\n",
2865 msr, data);
ed85c068
AP		 2866 break;
2867 }
15c4a640
CO		 2868 }
2869 return 0;
2870}
2871EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2872
44883f01 2873static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
15c4a640
CO		 2874{
2875 u64 data;
890ca9ae
HY		 2876 u64 mcg_cap = vcpu->arch.mcg_cap;
2877 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2878
2879 switch (msr) {
15c4a640
CO		 2880 case MSR_IA32_P5_MC_ADDR:
2881 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2882 data = 0;
2883 break;
15c4a640 2884 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2885 data = vcpu->arch.mcg_cap;
2886 break;
c7ac679c 2887 case MSR_IA32_MCG_CTL:
44883f01 2888 if (!(mcg_cap & MCG_CTL_P) && !host)
890ca9ae
HY		 2889 return 1;
2890 data = vcpu->arch.mcg_ctl;
2891 break;
2892 case MSR_IA32_MCG_STATUS:
2893 data = vcpu->arch.mcg_status;
2894 break;
2895 default:
2896 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2897 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2898 u32 offset = msr - MSR_IA32_MC0_CTL;
2899 data = vcpu->arch.mce_banks[offset];
2900 break;
2901 }
2902 return 1;
2903 }
2904 *pdata = data;
2905 return 0;
2906}
2907
609e36d3 2908int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2909{
609e36d3 2910 switch (msr_info->index) {
890ca9ae 2911 case MSR_IA32_PLATFORM_ID:
15c4a640 2912 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2913 case MSR_IA32_DEBUGCTLMSR:
2914 case MSR_IA32_LASTBRANCHFROMIP:
2915 case MSR_IA32_LASTBRANCHTOIP:
2916 case MSR_IA32_LASTINTFROMIP:
2917 case MSR_IA32_LASTINTTOIP:
60af2ecd 2918 case MSR_K8_SYSCFG:
3afb1121
PB		 2919 case MSR_K8_TSEG_ADDR:
2920 case MSR_K8_TSEG_MASK:
61a6bd67 2921 case MSR_VM_HSAVE_PA:
1fdbd48c 2922 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2923 case MSR_AMD64_NB_CFG:
f7c6d140 2924 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2925 case MSR_AMD64_BU_CFG2:
0c2df2a1 2926 case MSR_IA32_PERF_CTL:
405a353a 2927 case MSR_AMD64_DC_CFG:
0e1b869f 2928 case MSR_F15H_EX_CFG:
609e36d3 2929 msr_info->data = 0;
15c4a640 2930 break;
c51eb52b 2931 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
6912ac32
WH		 2932 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2933 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2934 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2935 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2936 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2937 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2938 msr_info->data = 0;
5753785f 2939 break;
742bc670 2940 case MSR_IA32_UCODE_REV:
518e7b94 2941 msr_info->data = vcpu->arch.microcode_version;
742bc670 2942 break;
0cf9135b
SC		 2943 case MSR_IA32_ARCH_CAPABILITIES:
2944 if (!msr_info->host_initiated &&
2945 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
2946 return 1;
2947 msr_info->data = vcpu->arch.arch_capabilities;
2948 break;
73f624f4
PB		 2949 case MSR_IA32_POWER_CTL:
2950 msr_info->data = vcpu->arch.msr_ia32_power_ctl;
2951 break;
dd259935
PB		 2952 case MSR_IA32_TSC:
2953 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
2954 break;
9ba075a6 2955 case MSR_MTRRcap:
9ba075a6 2956 case 0x200 ... 0x2ff:
ff53604b 2957 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2958 case 0xcd: /* fsb frequency */
609e36d3 2959 msr_info->data = 3;
15c4a640 2960 break;
7b914098
JS		 2961 /*
2962 * MSR_EBC_FREQUENCY_ID
2963 * Conservative value valid for even the basic CPU models.
2964 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2965 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2966 * and 266MHz for model 3, or 4. Set Core Clock
2967 * Frequency to System Bus Frequency Ratio to 1 (bits
2968 * 31:24) even though these are only valid for CPU
2969 * models > 2, however guests may end up dividing or
2970 * multiplying by zero otherwise.
2971 */
2972 case MSR_EBC_FREQUENCY_ID:
609e36d3 2973 msr_info->data = 1 << 24;
7b914098 2974 break;
15c4a640 2975 case MSR_IA32_APICBASE:
609e36d3 2976 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2977 break;
0105d1a5 2978 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2979 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2980 break;
a3e06bbe 2981 case MSR_IA32_TSCDEADLINE:
609e36d3 2982 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2983 break;
ba904635 2984 case MSR_IA32_TSC_ADJUST:
609e36d3 2985 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2986 break;
15c4a640 2987 case MSR_IA32_MISC_ENABLE:
609e36d3 2988 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2989 break;
64d60670
PB		 2990 case MSR_IA32_SMBASE:
2991 if (!msr_info->host_initiated)
2992 return 1;
2993 msr_info->data = vcpu->arch.smbase;
15c4a640 2994 break;
52797bf9
LA		 2995 case MSR_SMI_COUNT:
2996 msr_info->data = vcpu->arch.smi_count;
2997 break;
847f0ad8
AG		 2998 case MSR_IA32_PERF_STATUS:
2999 /* TSC increment by tick */
609e36d3 3000 msr_info->data = 1000ULL;
847f0ad8 3001 /* CPU multiplier */
b0996ae4 3002 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 3003 break;
15c4a640 3004 case MSR_EFER:
609e36d3 3005 msr_info->data = vcpu->arch.efer;
15c4a640 3006 break;
18068523 3007 case MSR_KVM_WALL_CLOCK:
11c6bffa 3008 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 3009 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 3010 break;
3011 case MSR_KVM_SYSTEM_TIME:
11c6bffa 3012 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 3013 msr_info->data = vcpu->arch.time;
18068523 3014 break;
344d9588 3015 case MSR_KVM_ASYNC_PF_EN:
609e36d3 3016 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 3017 break;
c9aaa895 3018 case MSR_KVM_STEAL_TIME:
609e36d3 3019 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 3020 break;
1d92128f 3021 case MSR_KVM_PV_EOI_EN:
609e36d3 3022 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 3023 break;
2d5ba19b
MT		 3024 case MSR_KVM_POLL_CONTROL:
3025 msr_info->data = vcpu->arch.msr_kvm_poll_control;
3026 break;
890ca9ae
HY		 3027 case MSR_IA32_P5_MC_ADDR:
3028 case MSR_IA32_P5_MC_TYPE:
3029 case MSR_IA32_MCG_CAP:
3030 case MSR_IA32_MCG_CTL:
3031 case MSR_IA32_MCG_STATUS:
81760dcc 3032 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
44883f01
PB		 3033 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
3034 msr_info->host_initiated);
84e0cefa
JS		 3035 case MSR_K7_CLK_CTL:
3036 /*
3037 * Provide expected ramp-up count for K7. All other
3038 * are set to zero, indicating minimum divisors for
3039 * every field.
3040 *
3041 * This prevents guest kernels on AMD host with CPU
3042 * type 6, model 8 and higher from exploding due to
3043 * the rdmsr failing.
3044 */
609e36d3 3045 msr_info->data = 0x20000000;
84e0cefa 3046 break;
55cd8e5a 3047 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 3048 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3049 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 3050 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 3051 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3052 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3053 case HV_X64_MSR_TSC_EMULATION_STATUS:
e83d5887 3054 return kvm_hv_get_msr_common(vcpu,
44883f01
PB		 3055 msr_info->index, &msr_info->data,
3056 msr_info->host_initiated);
55cd8e5a 3057 break;
91c9c3ed 3058 case MSR_IA32_BBL_CR_CTL3:
3059 /* This legacy MSR exists but isn't fully documented in current
3060 * silicon. It is however accessed by winxp in very narrow
3061 * scenarios where it sets bit #19, itself documented as
3062 * a "reserved" bit. Best effort attempt to source coherent
3063 * read data here should the balance of the register be
3064 * interpreted by the guest:
3065 *
3066 * L2 cache control register 3: 64GB range, 256KB size,
3067 * enabled, latency 0x1, configured
3068 */
609e36d3 3069 msr_info->data = 0xbe702111;
91c9c3ed 3070 break;
2b036c6b 3071 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 3072 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 3073 return 1;
609e36d3 3074 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 3075 break;
3076 case MSR_AMD64_OSVW_STATUS:
d6321d49 3077 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 3078 return 1;
609e36d3 3079 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 3080 break;
db2336a8 3081 case MSR_PLATFORM_INFO:
6fbbde9a
DS		 3082 if (!msr_info->host_initiated &&
3083 !vcpu->kvm->arch.guest_can_read_msr_platform_info)
3084 return 1;
db2336a8
KH		 3085 msr_info->data = vcpu->arch.msr_platform_info;
3086 break;
3087 case MSR_MISC_FEATURES_ENABLES:
3088 msr_info->data = vcpu->arch.msr_misc_features_enables;
3089 break;
191c8137
BP		 3090 case MSR_K7_HWCR:
3091 msr_info->data = vcpu->arch.msr_hwcr;
3092 break;
15c4a640 3093 default:
c6702c9d 3094 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 3095 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 3096 if (!ignore_msrs) {
ae0f5499
BD		 3097 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
3098 msr_info->index);
ed85c068
AP		 3099 return 1;
3100 } else {
fab0aa3b
EM		 3101 if (report_ignored_msrs)
3102 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
3103 msr_info->index);
609e36d3 3104 msr_info->data = 0;
ed85c068
AP		 3105 }
3106 break;
15c4a640 3107 }
15c4a640
CO		 3108 return 0;
3109}
3110EXPORT_SYMBOL_GPL(kvm_get_msr_common);
3111
313a3dc7
CO		 3112/*
3113 * Read or write a bunch of msrs. All parameters are kernel addresses.
3114 *
3115 * @return number of msrs set successfully.
3116 */
3117static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
3118 struct kvm_msr_entry *entries,
3119 int (*do_msr)(struct kvm_vcpu *vcpu,
3120 unsigned index, u64 *data))
3121{
801e459a 3122 int i;
313a3dc7 3123
313a3dc7
CO		 3124 for (i = 0; i < msrs->nmsrs; ++i)
3125 if (do_msr(vcpu, entries[i].index, &entries[i].data))
3126 break;
3127
313a3dc7
CO		 3128 return i;
3129}
3130
3131/*
3132 * Read or write a bunch of msrs. Parameters are user addresses.
3133 *
3134 * @return number of msrs set successfully.
3135 */
3136static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
3137 int (*do_msr)(struct kvm_vcpu *vcpu,
3138 unsigned index, u64 *data),
3139 int writeback)
3140{
3141 struct kvm_msrs msrs;
3142 struct kvm_msr_entry *entries;
3143 int r, n;
3144 unsigned size;
3145
3146 r = -EFAULT;
0e96f31e 3147 if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
313a3dc7
CO		 3148 goto out;
3149
3150 r = -E2BIG;
3151 if (msrs.nmsrs >= MAX_IO_MSRS)
3152 goto out;
3153
313a3dc7 3154 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 3155 entries = memdup_user(user_msrs->entries, size);
3156 if (IS_ERR(entries)) {
3157 r = PTR_ERR(entries);
313a3dc7 3158 goto out;
ff5c2c03 3159 }
313a3dc7
CO		 3160
3161 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
3162 if (r < 0)
3163 goto out_free;
3164
3165 r = -EFAULT;
3166 if (writeback && copy_to_user(user_msrs->entries, entries, size))
3167 goto out_free;
3168
3169 r = n;
3170
3171out_free:
7a73c028 3172 kfree(entries);
313a3dc7
CO		 3173out:
3174 return r;
3175}
3176
4d5422ce
WL		 3177static inline bool kvm_can_mwait_in_guest(void)
3178{
3179 return boot_cpu_has(X86_FEATURE_MWAIT) &&
8e9b29b6
KA		 3180 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
3181 boot_cpu_has(X86_FEATURE_ARAT);
4d5422ce
WL		 3182}
3183
784aa3d7 3184int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2 3185{
4d5422ce 3186 int r = 0;
018d00d2
ZX		 3187
3188 switch (ext) {
3189 case KVM_CAP_IRQCHIP:
3190 case KVM_CAP_HLT:
3191 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 3192 case KVM_CAP_SET_TSS_ADDR:
07716717 3193 case KVM_CAP_EXT_CPUID:
9c15bb1d 3194 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 3195 case KVM_CAP_CLOCKSOURCE:
7837699f 3196 case KVM_CAP_PIT:
a28e4f5a 3197 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 3198 case KVM_CAP_MP_STATE:
ed848624 3199 case KVM_CAP_SYNC_MMU:
a355c85c 3200 case KVM_CAP_USER_NMI:
52d939a0 3201 case KVM_CAP_REINJECT_CONTROL:
4925663a 3202 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 3203 case KVM_CAP_IOEVENTFD:
f848a5a8 3204 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 3205 case KVM_CAP_PIT2:
e9f42757 3206 case KVM_CAP_PIT_STATE2:
b927a3ce 3207 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 3208 case KVM_CAP_XEN_HVM:
3cfc3092 3209 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 3210 case KVM_CAP_HYPERV:
10388a07 3211 case KVM_CAP_HYPERV_VAPIC:
c25bc163 3212 case KVM_CAP_HYPERV_SPIN:
5c919412 3213 case KVM_CAP_HYPERV_SYNIC:
efc479e6 3214 case KVM_CAP_HYPERV_SYNIC2:
d3457c87 3215 case KVM_CAP_HYPERV_VP_INDEX:
faeb7833 3216 case KVM_CAP_HYPERV_EVENTFD:
c1aea919 3217 case KVM_CAP_HYPERV_TLBFLUSH:
214ff83d 3218 case KVM_CAP_HYPERV_SEND_IPI:
2bc39970 3219 case KVM_CAP_HYPERV_CPUID:
ab9f4ecb 3220 case KVM_CAP_PCI_SEGMENT:
a1efbe77 3221 case KVM_CAP_DEBUGREGS:
d2be1651 3222 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 3223 case KVM_CAP_XSAVE:
344d9588 3224 case KVM_CAP_ASYNC_PF:
92a1f12d 3225 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 3226 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 3227 case KVM_CAP_READONLY_MEM:
5f66b620 3228 case KVM_CAP_HYPERV_TIME:
100943c5 3229 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 3230 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18 3231 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 3232 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 3233 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 3234 case KVM_CAP_IMMEDIATE_EXIT:
66bb8a06 3235 case KVM_CAP_PMU_EVENT_FILTER:
801e459a 3236 case KVM_CAP_GET_MSR_FEATURES:
6fbbde9a 3237 case KVM_CAP_MSR_PLATFORM_INFO:
c4f55198 3238 case KVM_CAP_EXCEPTION_PAYLOAD:
018d00d2
ZX		 3239 r = 1;
3240 break;
01643c51
KH		 3241 case KVM_CAP_SYNC_REGS:
3242 r = KVM_SYNC_X86_VALID_FIELDS;
3243 break;
e3fd9a93
PB		 3244 case KVM_CAP_ADJUST_CLOCK:
3245 r = KVM_CLOCK_TSC_STABLE;
3246 break;
4d5422ce 3247 case KVM_CAP_X86_DISABLE_EXITS:
b5170063
WL		 3248 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE |
3249 KVM_X86_DISABLE_EXITS_CSTATE;
4d5422ce
WL		 3250 if(kvm_can_mwait_in_guest())
3251 r |= KVM_X86_DISABLE_EXITS_MWAIT;
668fffa3 3252 break;
6d396b55
PB		 3253 case KVM_CAP_X86_SMM:
3254 /* SMBASE is usually relocated above 1M on modern chipsets,
3255 * and SMM handlers might indeed rely on 4G segment limits,
3256 * so do not report SMM to be available if real mode is
3257 * emulated via vm86 mode. Still, do not go to great lengths
3258 * to avoid userspace's usage of the feature, because it is a
3259 * fringe case that is not enabled except via specific settings
3260 * of the module parameters.
3261 */
bc226f07 3262 r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE);
6d396b55 3263 break;
774ead3a
AK		 3264 case KVM_CAP_VAPIC:
3265 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
3266 break;
f725230a 3267 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 3268 r = KVM_SOFT_MAX_VCPUS;
3269 break;
3270 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 3271 r = KVM_MAX_VCPUS;
3272 break;
a86cb413
TH		 3273 case KVM_CAP_MAX_VCPU_ID:
3274 r = KVM_MAX_VCPU_ID;
3275 break;
a68a6a72
MT		 3276 case KVM_CAP_PV_MMU: /* obsolete */
3277 r = 0;
2f333bcb 3278 break;
890ca9ae
HY		 3279 case KVM_CAP_MCE:
3280 r = KVM_MAX_MCE_BANKS;
3281 break;
2d5b5a66 3282 case KVM_CAP_XCRS:
d366bf7e 3283 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 3284 break;
92a1f12d
JR		 3285 case KVM_CAP_TSC_CONTROL:
3286 r = kvm_has_tsc_control;
3287 break;
37131313
RK		 3288 case KVM_CAP_X2APIC_API:
3289 r = KVM_X2APIC_API_VALID_FLAGS;
3290 break;
8fcc4b59
JM		 3291 case KVM_CAP_NESTED_STATE:
3292 r = kvm_x86_ops->get_nested_state ?
be43c440 3293 kvm_x86_ops->get_nested_state(NULL, NULL, 0) : 0;
8fcc4b59 3294 break;
344c6c80 3295 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
5a0165f6
VK		 3296 r = kvm_x86_ops->enable_direct_tlbflush != NULL;
3297 break;
3298 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
3299 r = kvm_x86_ops->nested_enable_evmcs != NULL;
344c6c80 3300 break;
018d00d2 3301 default:
018d00d2
ZX		 3302 break;
3303 }
3304 return r;
3305
3306}
3307
043405e1
CO		 3308long kvm_arch_dev_ioctl(struct file *filp,
3309 unsigned int ioctl, unsigned long arg)
3310{
3311 void __user *argp = (void __user *)arg;
3312 long r;
3313
3314 switch (ioctl) {
3315 case KVM_GET_MSR_INDEX_LIST: {
3316 struct kvm_msr_list __user *user_msr_list = argp;
3317 struct kvm_msr_list msr_list;
3318 unsigned n;
3319
3320 r = -EFAULT;
0e96f31e 3321 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
043405e1
CO		 3322 goto out;
3323 n = msr_list.nmsrs;
62ef68bb 3324 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
0e96f31e 3325 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
043405e1
CO		 3326 goto out;
3327 r = -E2BIG;
e125e7b6 3328 if (n < msr_list.nmsrs)
043405e1
CO		 3329 goto out;
3330 r = -EFAULT;
3331 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
3332 num_msrs_to_save * sizeof(u32)))
3333 goto out;
e125e7b6 3334 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 3335 &emulated_msrs,
62ef68bb 3336 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 3337 goto out;
3338 r = 0;
3339 break;
3340 }
9c15bb1d
BP		 3341 case KVM_GET_SUPPORTED_CPUID:
3342 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 3343 struct kvm_cpuid2 __user *cpuid_arg = argp;
3344 struct kvm_cpuid2 cpuid;
3345
3346 r = -EFAULT;
0e96f31e 3347 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
674eea0f 3348 goto out;
9c15bb1d
BP		 3349
3350 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3351 ioctl);
674eea0f
AK		 3352 if (r)
3353 goto out;
3354
3355 r = -EFAULT;
0e96f31e 3356 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
674eea0f
AK		 3357 goto out;
3358 r = 0;
3359 break;
3360 }
890ca9ae 3361 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 3362 r = -EFAULT;
c45dcc71
AR		 3363 if (copy_to_user(argp, &kvm_mce_cap_supported,
3364 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 3365 goto out;
3366 r = 0;
3367 break;
801e459a
TL		 3368 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3369 struct kvm_msr_list __user *user_msr_list = argp;
3370 struct kvm_msr_list msr_list;
3371 unsigned int n;
3372
3373 r = -EFAULT;
3374 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3375 goto out;
3376 n = msr_list.nmsrs;
3377 msr_list.nmsrs = num_msr_based_features;
3378 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3379 goto out;
3380 r = -E2BIG;
3381 if (n < msr_list.nmsrs)
3382 goto out;
3383 r = -EFAULT;
3384 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3385 num_msr_based_features * sizeof(u32)))
3386 goto out;
3387 r = 0;
3388 break;
3389 }
3390 case KVM_GET_MSRS:
3391 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3392 break;
890ca9ae 3393 }
043405e1
CO		 3394 default:
3395 r = -EINVAL;
3396 }
3397out:
3398 return r;
3399}
3400
f5f48ee1
SY		 3401static void wbinvd_ipi(void *garbage)
3402{
3403 wbinvd();
3404}
3405
3406static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3407{
e0f0bbc5 3408 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 3409}
3410
313a3dc7
CO		 3411void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3412{
f5f48ee1
SY		 3413 /* Address WBINVD may be executed by guest */
3414 if (need_emulate_wbinvd(vcpu)) {
3415 if (kvm_x86_ops->has_wbinvd_exit())
3416 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3417 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3418 smp_call_function_single(vcpu->cpu,
3419 wbinvd_ipi, NULL, 1);
3420 }
3421
313a3dc7 3422 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 3423
e7517324
WL		 3424 fpregs_assert_state_consistent();
3425 if (test_thread_flag(TIF_NEED_FPU_LOAD))
3426 switch_fpu_return();
3427
0dd6a6ed
ZA		 3428 /* Apply any externally detected TSC adjustments (due to suspend) */
3429 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3430 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3431 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 3432 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 3433 }
8f6055cb 3434
b0c39dc6 3435 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
6f526ec5 3436 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 3437 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 3438 if (tsc_delta < 0)
3439 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 3440
b0c39dc6 3441 if (kvm_check_tsc_unstable()) {
07c1419a 3442 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 3443 vcpu->arch.last_guest_tsc);
a545ab6a 3444 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 3445 vcpu->arch.tsc_catchup = 1;
c285545f 3446 }
a749e247
PB		 3447
3448 if (kvm_lapic_hv_timer_in_use(vcpu))
3449 kvm_lapic_restart_hv_timer(vcpu);
3450
d98d07ca
MT		 3451 /*
3452 * On a host with synchronized TSC, there is no need to update
3453 * kvmclock on vcpu->cpu migration
3454 */
3455 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 3456 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f 3457 if (vcpu->cpu != cpu)
1bd2009e 3458 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
e48672fa 3459 vcpu->cpu = cpu;
6b7d7e76 3460 }
c9aaa895 3461
c9aaa895 3462 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 3463}
3464
0b9f6c46
PX		 3465static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3466{
3467 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3468 return;
3469
fa55eedd 3470 vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED;
0b9f6c46 3471
4e335d9e 3472 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
0b9f6c46
PX		 3473 &vcpu->arch.st.steal.preempted,
3474 offsetof(struct kvm_steal_time, preempted),
3475 sizeof(vcpu->arch.st.steal.preempted));
3476}
3477
313a3dc7
CO		 3478void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3479{
cc0d907c 3480 int idx;
de63ad4c
LM		 3481
3482 if (vcpu->preempted)
3483 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3484
931f261b
AA		 3485 /*
3486 * Disable page faults because we're in atomic context here.
3487 * kvm_write_guest_offset_cached() would call might_fault()
3488 * that relies on pagefault_disable() to tell if there's a
3489 * bug. NOTE: the write to guest memory may not go through if
3490 * during postcopy live migration or if there's heavy guest
3491 * paging.
3492 */
3493 pagefault_disable();
cc0d907c
AA		 3494 /*
3495 * kvm_memslots() will be called by
3496 * kvm_write_guest_offset_cached() so take the srcu lock.
3497 */
3498 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 3499 kvm_steal_time_set_preempted(vcpu);
cc0d907c 3500 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 3501 pagefault_enable();
02daab21 3502 kvm_x86_ops->vcpu_put(vcpu);
4ea1636b 3503 vcpu->arch.last_host_tsc = rdtsc();
efdab992 3504 /*
f9dcf08e
RK		 3505 * If userspace has set any breakpoints or watchpoints, dr6 is restored
3506 * on every vmexit, but if not, we might have a stale dr6 from the
3507 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
efdab992 3508 */
f9dcf08e 3509 set_debugreg(0, 6);
313a3dc7
CO		 3510}
3511
313a3dc7
CO		 3512static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3513 struct kvm_lapic_state *s)
3514{
fa59cc00 3515 if (vcpu->arch.apicv_active)
d62caabb
AS		 3516 kvm_x86_ops->sync_pir_to_irr(vcpu);
3517
a92e2543 3518 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 3519}
3520
3521static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3522 struct kvm_lapic_state *s)
3523{
a92e2543
RK		 3524 int r;
3525
3526 r = kvm_apic_set_state(vcpu, s);
3527 if (r)
3528 return r;
cb142eb7 3529 update_cr8_intercept(vcpu);
313a3dc7
CO		 3530
3531 return 0;
3532}
3533
127a457a
MG		 3534static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3535{
3536 return (!lapic_in_kernel(vcpu) ||
3537 kvm_apic_accept_pic_intr(vcpu));
3538}
3539
782d422b
MG		 3540/*
3541 * if userspace requested an interrupt window, check that the
3542 * interrupt window is open.
3543 *
3544 * No need to exit to userspace if we already have an interrupt queued.
3545 */
3546static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3547{
3548 return kvm_arch_interrupt_allowed(vcpu) &&
3549 !kvm_cpu_has_interrupt(vcpu) &&
3550 !kvm_event_needs_reinjection(vcpu) &&
3551 kvm_cpu_accept_dm_intr(vcpu);
3552}
3553
f77bc6a4
ZX		 3554static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3555 struct kvm_interrupt *irq)
3556{
02cdb50f 3557 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 3558 return -EINVAL;
1c1a9ce9
SR		 3559
3560 if (!irqchip_in_kernel(vcpu->kvm)) {
3561 kvm_queue_interrupt(vcpu, irq->irq, false);
3562 kvm_make_request(KVM_REQ_EVENT, vcpu);
3563 return 0;
3564 }
3565
3566 /*
3567 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3568 * fail for in-kernel 8259.
3569 */
3570 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 3571 return -ENXIO;
f77bc6a4 3572
1c1a9ce9
SR		 3573 if (vcpu->arch.pending_external_vector != -1)
3574 return -EEXIST;
f77bc6a4 3575
1c1a9ce9 3576 vcpu->arch.pending_external_vector = irq->irq;
934bf653 3577 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 3578 return 0;
3579}
3580
c4abb7c9
JK		 3581static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3582{
c4abb7c9 3583 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 3584
3585 return 0;
3586}
3587
f077825a
PB		 3588static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3589{
64d60670
PB		 3590 kvm_make_request(KVM_REQ_SMI, vcpu);
3591
f077825a
PB		 3592 return 0;
3593}
3594
b209749f
AK		 3595static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3596 struct kvm_tpr_access_ctl *tac)
3597{
3598 if (tac->flags)
3599 return -EINVAL;
3600 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3601 return 0;
3602}
3603
890ca9ae
HY		 3604static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3605 u64 mcg_cap)
3606{
3607 int r;
3608 unsigned bank_num = mcg_cap & 0xff, bank;
3609
3610 r = -EINVAL;
a9e38c3e 3611 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 3612 goto out;
c45dcc71 3613 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 3614 goto out;
3615 r = 0;
3616 vcpu->arch.mcg_cap = mcg_cap;
3617 /* Init IA32_MCG_CTL to all 1s */
3618 if (mcg_cap & MCG_CTL_P)
3619 vcpu->arch.mcg_ctl = ~(u64)0;
3620 /* Init IA32_MCi_CTL to all 1s */
3621 for (bank = 0; bank < bank_num; bank++)
3622 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71 3623
92735b1b 3624 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3625out:
3626 return r;
3627}
3628
3629static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3630 struct kvm_x86_mce *mce)
3631{
3632 u64 mcg_cap = vcpu->arch.mcg_cap;
3633 unsigned bank_num = mcg_cap & 0xff;
3634 u64 *banks = vcpu->arch.mce_banks;
3635
3636 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3637 return -EINVAL;
3638 /*
3639 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3640 * reporting is disabled
3641 */
3642 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3643 vcpu->arch.mcg_ctl != ~(u64)0)
3644 return 0;
3645 banks += 4 * mce->bank;
3646 /*
3647 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3648 * reporting is disabled for the bank
3649 */
3650 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3651 return 0;
3652 if (mce->status & MCI_STATUS_UC) {
3653 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3654 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3655 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3656 return 0;
3657 }
3658 if (banks[1] & MCI_STATUS_VAL)
3659 mce->status |= MCI_STATUS_OVER;
3660 banks[2] = mce->addr;
3661 banks[3] = mce->misc;
3662 vcpu->arch.mcg_status = mce->mcg_status;
3663 banks[1] = mce->status;
3664 kvm_queue_exception(vcpu, MC_VECTOR);
3665 } else if (!(banks[1] & MCI_STATUS_VAL)
3666 || !(banks[1] & MCI_STATUS_UC)) {
3667 if (banks[1] & MCI_STATUS_VAL)
3668 mce->status |= MCI_STATUS_OVER;
3669 banks[2] = mce->addr;
3670 banks[3] = mce->misc;
3671 banks[1] = mce->status;
3672 } else
3673 banks[1] |= MCI_STATUS_OVER;
3674 return 0;
3675}
3676
3cfc3092
JK		 3677static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3678 struct kvm_vcpu_events *events)
3679{
7460fb4a 3680 process_nmi(vcpu);
59073aaf 3681
664f8e26 3682 /*
59073aaf
JM		 3683 * The API doesn't provide the instruction length for software
3684 * exceptions, so don't report them. As long as the guest RIP
3685 * isn't advanced, we should expect to encounter the exception
3686 * again.
664f8e26 3687 */
59073aaf
JM		 3688 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
3689 events->exception.injected = 0;
3690 events->exception.pending = 0;
3691 } else {
3692 events->exception.injected = vcpu->arch.exception.injected;
3693 events->exception.pending = vcpu->arch.exception.pending;
3694 /*
3695 * For ABI compatibility, deliberately conflate
3696 * pending and injected exceptions when
3697 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
3698 */
3699 if (!vcpu->kvm->arch.exception_payload_enabled)
3700 events->exception.injected |=
3701 vcpu->arch.exception.pending;
3702 }
3cfc3092
JK		 3703 events->exception.nr = vcpu->arch.exception.nr;
3704 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3705 events->exception.error_code = vcpu->arch.exception.error_code;
59073aaf
JM		 3706 events->exception_has_payload = vcpu->arch.exception.has_payload;
3707 events->exception_payload = vcpu->arch.exception.payload;
3cfc3092 3708
03b82a30 3709 events->interrupt.injected =
04140b41 3710 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
3cfc3092 3711 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3712 events->interrupt.soft = 0;
37ccdcbe 3713 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3714
3715 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3716 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3717 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3718 events->nmi.pad = 0;
3cfc3092 3719
66450a21 3720 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3721
f077825a
PB		 3722 events->smi.smm = is_smm(vcpu);
3723 events->smi.pending = vcpu->arch.smi_pending;
3724 events->smi.smm_inside_nmi =
3725 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3726 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3727
dab4b911 3728 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3729 | KVM_VCPUEVENT_VALID_SHADOW
3730 | KVM_VCPUEVENT_VALID_SMM);
59073aaf
JM		 3731 if (vcpu->kvm->arch.exception_payload_enabled)
3732 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
3733
97e69aa6 3734 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3735}
3736
c5833c7a 3737static void kvm_smm_changed(struct kvm_vcpu *vcpu);
6ef4e07e 3738
3cfc3092
JK		 3739static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3740 struct kvm_vcpu_events *events)
3741{
dab4b911 3742 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3743 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a 3744 | KVM_VCPUEVENT_VALID_SHADOW
59073aaf
JM		 3745 | KVM_VCPUEVENT_VALID_SMM
3746 | KVM_VCPUEVENT_VALID_PAYLOAD))
3cfc3092
JK		 3747 return -EINVAL;
3748
59073aaf
JM		 3749 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
3750 if (!vcpu->kvm->arch.exception_payload_enabled)
3751 return -EINVAL;
3752 if (events->exception.pending)
3753 events->exception.injected = 0;
3754 else
3755 events->exception_has_payload = 0;
3756 } else {
3757 events->exception.pending = 0;
3758 events->exception_has_payload = 0;
3759 }
3760
3761 if ((events->exception.injected || events->exception.pending) &&
3762 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
78e546c8
PB		 3763 return -EINVAL;
3764
28bf2888
DH		 3765 /* INITs are latched while in SMM */
3766 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3767 (events->smi.smm || events->smi.pending) &&
3768 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3769 return -EINVAL;
3770
7460fb4a 3771 process_nmi(vcpu);
59073aaf
JM		 3772 vcpu->arch.exception.injected = events->exception.injected;
3773 vcpu->arch.exception.pending = events->exception.pending;
3cfc3092
JK		 3774 vcpu->arch.exception.nr = events->exception.nr;
3775 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3776 vcpu->arch.exception.error_code = events->exception.error_code;
59073aaf
JM		 3777 vcpu->arch.exception.has_payload = events->exception_has_payload;
3778 vcpu->arch.exception.payload = events->exception_payload;
3cfc3092 3779
04140b41 3780 vcpu->arch.interrupt.injected = events->interrupt.injected;
3cfc3092
JK		 3781 vcpu->arch.interrupt.nr = events->interrupt.nr;
3782 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3783 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3784 kvm_x86_ops->set_interrupt_shadow(vcpu,
3785 events->interrupt.shadow);
3cfc3092
JK		 3786
3787 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3788 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3789 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3790 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3791
66450a21 3792 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3793 lapic_in_kernel(vcpu))
66450a21 3794 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3795
f077825a 3796 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
c5833c7a
SC		 3797 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
3798 if (events->smi.smm)
3799 vcpu->arch.hflags |= HF_SMM_MASK;
3800 else
3801 vcpu->arch.hflags &= ~HF_SMM_MASK;
3802 kvm_smm_changed(vcpu);
3803 }
6ef4e07e 3804
f077825a 3805 vcpu->arch.smi_pending = events->smi.pending;
f4ef1910
WL		 3806
3807 if (events->smi.smm) {
3808 if (events->smi.smm_inside_nmi)
3809 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
f077825a 3810 else
f4ef1910
WL		 3811 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3812 if (lapic_in_kernel(vcpu)) {
3813 if (events->smi.latched_init)
3814 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3815 else
3816 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3817 }
f077825a
PB		 3818 }
3819 }
3820
3842d135
AK		 3821 kvm_make_request(KVM_REQ_EVENT, vcpu);
3822
3cfc3092
JK		 3823 return 0;
3824}
3825
a1efbe77
JK		 3826static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3827 struct kvm_debugregs *dbgregs)
3828{
73aaf249
JK		 3829 unsigned long val;
3830
a1efbe77 3831 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3832 kvm_get_dr(vcpu, 6, &val);
73aaf249 3833 dbgregs->dr6 = val;
a1efbe77
JK		 3834 dbgregs->dr7 = vcpu->arch.dr7;
3835 dbgregs->flags = 0;
97e69aa6 3836 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3837}
3838
3839static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3840 struct kvm_debugregs *dbgregs)
3841{
3842 if (dbgregs->flags)
3843 return -EINVAL;
3844
d14bdb55
PB		 3845 if (dbgregs->dr6 & ~0xffffffffull)
3846 return -EINVAL;
3847 if (dbgregs->dr7 & ~0xffffffffull)
3848 return -EINVAL;
3849
a1efbe77 3850 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3851 kvm_update_dr0123(vcpu);
a1efbe77 3852 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3853 kvm_update_dr6(vcpu);
a1efbe77 3854 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3855 kvm_update_dr7(vcpu);
a1efbe77 3856
a1efbe77
JK		 3857 return 0;
3858}
3859
df1daba7
PB		 3860#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3861
3862static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3863{
b666a4b6 3864 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
400e4b20 3865 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3866 u64 valid;
3867
3868 /*
3869 * Copy legacy XSAVE area, to avoid complications with CPUID
3870 * leaves 0 and 1 in the loop below.
3871 */
3872 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3873
3874 /* Set XSTATE_BV */
00c87e9a 3875 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3876 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3877
3878 /*
3879 * Copy each region from the possibly compacted offset to the
3880 * non-compacted offset.
3881 */
d91cab78 3882 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7 3883 while (valid) {
abd16d68
SAS		 3884 u64 xfeature_mask = valid & -valid;
3885 int xfeature_nr = fls64(xfeature_mask) - 1;
3886 void *src = get_xsave_addr(xsave, xfeature_nr);
df1daba7
PB		 3887
3888 if (src) {
3889 u32 size, offset, ecx, edx;
abd16d68 3890 cpuid_count(XSTATE_CPUID, xfeature_nr,
df1daba7 3891 &size, &offset, &ecx, &edx);
abd16d68 3892 if (xfeature_nr == XFEATURE_PKRU)
38cfd5e3
PB		 3893 memcpy(dest + offset, &vcpu->arch.pkru,
3894 sizeof(vcpu->arch.pkru));
3895 else
3896 memcpy(dest + offset, src, size);
3897
df1daba7
PB		 3898 }
3899
abd16d68 3900 valid -= xfeature_mask;
df1daba7
PB		 3901 }
3902}
3903
3904static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3905{
b666a4b6 3906 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
df1daba7
PB		 3907 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3908 u64 valid;
3909
3910 /*
3911 * Copy legacy XSAVE area, to avoid complications with CPUID
3912 * leaves 0 and 1 in the loop below.
3913 */
3914 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3915
3916 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3917 xsave->header.xfeatures = xstate_bv;
782511b0 3918 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3919 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3920
3921 /*
3922 * Copy each region from the non-compacted offset to the
3923 * possibly compacted offset.
3924 */
d91cab78 3925 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7 3926 while (valid) {
abd16d68
SAS		 3927 u64 xfeature_mask = valid & -valid;
3928 int xfeature_nr = fls64(xfeature_mask) - 1;
3929 void *dest = get_xsave_addr(xsave, xfeature_nr);
df1daba7
PB		 3930
3931 if (dest) {
3932 u32 size, offset, ecx, edx;
abd16d68 3933 cpuid_count(XSTATE_CPUID, xfeature_nr,
df1daba7 3934 &size, &offset, &ecx, &edx);
abd16d68 3935 if (xfeature_nr == XFEATURE_PKRU)
38cfd5e3
PB		 3936 memcpy(&vcpu->arch.pkru, src + offset,
3937 sizeof(vcpu->arch.pkru));
3938 else
3939 memcpy(dest, src + offset, size);
ee4100da 3940 }
df1daba7 3941
abd16d68 3942 valid -= xfeature_mask;
df1daba7
PB		 3943 }
3944}
3945
2d5b5a66
SY		 3946static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3947 struct kvm_xsave *guest_xsave)
3948{
d366bf7e 3949 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3950 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3951 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3952 } else {
2d5b5a66 3953 memcpy(guest_xsave->region,
b666a4b6 3954 &vcpu->arch.guest_fpu->state.fxsave,
c47ada30 3955 sizeof(struct fxregs_state));
2d5b5a66 3956 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3957 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3958 }
3959}
3960
a575813b
WL		 3961#define XSAVE_MXCSR_OFFSET 24
3962
2d5b5a66
SY		 3963static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3964 struct kvm_xsave *guest_xsave)
3965{
3966 u64 xstate_bv =
3967 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
a575813b 3968 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
2d5b5a66 3969
d366bf7e 3970 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3971 /*
3972 * Here we allow setting states that are not present in
3973 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3974 * with old userspace.
3975 */
a575813b
WL		 3976 if (xstate_bv & ~kvm_supported_xcr0() ||
3977 mxcsr & ~mxcsr_feature_mask)
d7876f1b 3978 return -EINVAL;
df1daba7 3979 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3980 } else {
a575813b
WL		 3981 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3982 mxcsr & ~mxcsr_feature_mask)
2d5b5a66 3983 return -EINVAL;
b666a4b6 3984 memcpy(&vcpu->arch.guest_fpu->state.fxsave,
c47ada30 3985 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3986 }
3987 return 0;
3988}
3989
3990static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3991 struct kvm_xcrs *guest_xcrs)
3992{
d366bf7e 3993 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3994 guest_xcrs->nr_xcrs = 0;
3995 return;
3996 }
3997
3998 guest_xcrs->nr_xcrs = 1;
3999 guest_xcrs->flags = 0;
4000 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
4001 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
4002}
4003
4004static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
4005 struct kvm_xcrs *guest_xcrs)
4006{
4007 int i, r = 0;
4008
d366bf7e 4009 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 4010 return -EINVAL;
4011
4012 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
4013 return -EINVAL;
4014
4015 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
4016 /* Only support XCR0 currently */
c67a04cb 4017 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 4018 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 4019 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 4020 break;
4021 }
4022 if (r)
4023 r = -EINVAL;
4024 return r;
4025}
4026
1c0b28c2
EM		 4027/*
4028 * kvm_set_guest_paused() indicates to the guest kernel that it has been
4029 * stopped by the hypervisor. This function will be called from the host only.
4030 * EINVAL is returned when the host attempts to set the flag for a guest that
4031 * does not support pv clocks.
4032 */
4033static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
4034{
0b79459b 4035 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 4036 return -EINVAL;
51d59c6b 4037 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 4038 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
4039 return 0;
4040}
4041
5c919412
AS		 4042static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
4043 struct kvm_enable_cap *cap)
4044{
57b119da
VK		 4045 int r;
4046 uint16_t vmcs_version;
4047 void __user *user_ptr;
4048
5c919412
AS		 4049 if (cap->flags)
4050 return -EINVAL;
4051
4052 switch (cap->cap) {
efc479e6
RK		 4053 case KVM_CAP_HYPERV_SYNIC2:
4054 if (cap->args[0])
4055 return -EINVAL;
b2869f28
GS		 4056 /* fall through */
4057
5c919412 4058 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 4059 if (!irqchip_in_kernel(vcpu->kvm))
4060 return -EINVAL;
efc479e6
RK		 4061 return kvm_hv_activate_synic(vcpu, cap->cap ==
4062 KVM_CAP_HYPERV_SYNIC2);
57b119da 4063 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
5158917c
SC		 4064 if (!kvm_x86_ops->nested_enable_evmcs)
4065 return -ENOTTY;
57b119da
VK		 4066 r = kvm_x86_ops->nested_enable_evmcs(vcpu, &vmcs_version);
4067 if (!r) {
4068 user_ptr = (void __user *)(uintptr_t)cap->args[0];
4069 if (copy_to_user(user_ptr, &vmcs_version,
4070 sizeof(vmcs_version)))
4071 r = -EFAULT;
4072 }
4073 return r;
344c6c80
TL		 4074 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
4075 if (!kvm_x86_ops->enable_direct_tlbflush)
4076 return -ENOTTY;
4077
4078 return kvm_x86_ops->enable_direct_tlbflush(vcpu);
57b119da 4079
5c919412
AS		 4080 default:
4081 return -EINVAL;
4082 }
4083}
4084
313a3dc7
CO		 4085long kvm_arch_vcpu_ioctl(struct file *filp,
4086 unsigned int ioctl, unsigned long arg)
4087{
4088 struct kvm_vcpu *vcpu = filp->private_data;
4089 void __user *argp = (void __user *)arg;
4090 int r;
d1ac91d8
AK		 4091 union {
4092 struct kvm_lapic_state *lapic;
4093 struct kvm_xsave *xsave;
4094 struct kvm_xcrs *xcrs;
4095 void *buffer;
4096 } u;
4097
9b062471
CD		 4098 vcpu_load(vcpu);
4099
d1ac91d8 4100 u.buffer = NULL;
313a3dc7
CO		 4101 switch (ioctl) {
4102 case KVM_GET_LAPIC: {
2204ae3c 4103 r = -EINVAL;
bce87cce 4104 if (!lapic_in_kernel(vcpu))
2204ae3c 4105 goto out;
254272ce
BG		 4106 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
4107 GFP_KERNEL_ACCOUNT);
313a3dc7 4108
b772ff36 4109 r = -ENOMEM;
d1ac91d8 4110 if (!u.lapic)
b772ff36 4111 goto out;
d1ac91d8 4112 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 4113 if (r)
4114 goto out;
4115 r = -EFAULT;
d1ac91d8 4116 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 4117 goto out;
4118 r = 0;
4119 break;
4120 }
4121 case KVM_SET_LAPIC: {
2204ae3c 4122 r = -EINVAL;
bce87cce 4123 if (!lapic_in_kernel(vcpu))
2204ae3c 4124 goto out;
ff5c2c03 4125 u.lapic = memdup_user(argp, sizeof(*u.lapic));
9b062471
CD		 4126 if (IS_ERR(u.lapic)) {
4127 r = PTR_ERR(u.lapic);
4128 goto out_nofree;
4129 }
ff5c2c03 4130
d1ac91d8 4131 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 4132 break;
4133 }
f77bc6a4
ZX		 4134 case KVM_INTERRUPT: {
4135 struct kvm_interrupt irq;
4136
4137 r = -EFAULT;
0e96f31e 4138 if (copy_from_user(&irq, argp, sizeof(irq)))
f77bc6a4
ZX		 4139 goto out;
4140 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 4141 break;
4142 }
c4abb7c9
JK		 4143 case KVM_NMI: {
4144 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 4145 break;
4146 }
f077825a
PB		 4147 case KVM_SMI: {
4148 r = kvm_vcpu_ioctl_smi(vcpu);
4149 break;
4150 }
313a3dc7
CO		 4151 case KVM_SET_CPUID: {
4152 struct kvm_cpuid __user *cpuid_arg = argp;
4153 struct kvm_cpuid cpuid;
4154
4155 r = -EFAULT;
0e96f31e 4156 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
313a3dc7
CO		 4157 goto out;
4158 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 4159 break;
4160 }
07716717
DK		 4161 case KVM_SET_CPUID2: {
4162 struct kvm_cpuid2 __user *cpuid_arg = argp;
4163 struct kvm_cpuid2 cpuid;
4164
4165 r = -EFAULT;
0e96f31e 4166 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
07716717
DK		 4167 goto out;
4168 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 4169 cpuid_arg->entries);
07716717
DK		 4170 break;
4171 }
4172 case KVM_GET_CPUID2: {
4173 struct kvm_cpuid2 __user *cpuid_arg = argp;
4174 struct kvm_cpuid2 cpuid;
4175
4176 r = -EFAULT;
0e96f31e 4177 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
07716717
DK		 4178 goto out;
4179 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 4180 cpuid_arg->entries);
07716717
DK		 4181 if (r)
4182 goto out;
4183 r = -EFAULT;
0e96f31e 4184 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
07716717
DK		 4185 goto out;
4186 r = 0;
4187 break;
4188 }
801e459a
TL		 4189 case KVM_GET_MSRS: {
4190 int idx = srcu_read_lock(&vcpu->kvm->srcu);
609e36d3 4191 r = msr_io(vcpu, argp, do_get_msr, 1);
801e459a 4192 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 4193 break;
801e459a
TL		 4194 }
4195 case KVM_SET_MSRS: {
4196 int idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7 4197 r = msr_io(vcpu, argp, do_set_msr, 0);
801e459a 4198 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 4199 break;
801e459a 4200 }
b209749f
AK		 4201 case KVM_TPR_ACCESS_REPORTING: {
4202 struct kvm_tpr_access_ctl tac;
4203
4204 r = -EFAULT;
0e96f31e 4205 if (copy_from_user(&tac, argp, sizeof(tac)))
b209749f
AK		 4206 goto out;
4207 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
4208 if (r)
4209 goto out;
4210 r = -EFAULT;
0e96f31e 4211 if (copy_to_user(argp, &tac, sizeof(tac)))
b209749f
AK		 4212 goto out;
4213 r = 0;
4214 break;
4215 };
b93463aa
AK		 4216 case KVM_SET_VAPIC_ADDR: {
4217 struct kvm_vapic_addr va;
7301d6ab 4218 int idx;
b93463aa
AK		 4219
4220 r = -EINVAL;
35754c98 4221 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 4222 goto out;
4223 r = -EFAULT;
0e96f31e 4224 if (copy_from_user(&va, argp, sizeof(va)))
b93463aa 4225 goto out;
7301d6ab 4226 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 4227 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 4228 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 4229 break;
4230 }
890ca9ae
HY		 4231 case KVM_X86_SETUP_MCE: {
4232 u64 mcg_cap;
4233
4234 r = -EFAULT;
0e96f31e 4235 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
890ca9ae
HY		 4236 goto out;
4237 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
4238 break;
4239 }
4240 case KVM_X86_SET_MCE: {
4241 struct kvm_x86_mce mce;
4242
4243 r = -EFAULT;
0e96f31e 4244 if (copy_from_user(&mce, argp, sizeof(mce)))
890ca9ae
HY		 4245 goto out;
4246 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
4247 break;
4248 }
3cfc3092
JK		 4249 case KVM_GET_VCPU_EVENTS: {
4250 struct kvm_vcpu_events events;
4251
4252 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
4253
4254 r = -EFAULT;
4255 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
4256 break;
4257 r = 0;
4258 break;
4259 }
4260 case KVM_SET_VCPU_EVENTS: {
4261 struct kvm_vcpu_events events;
4262
4263 r = -EFAULT;
4264 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
4265 break;
4266
4267 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
4268 break;
4269 }
a1efbe77
JK		 4270 case KVM_GET_DEBUGREGS: {
4271 struct kvm_debugregs dbgregs;
4272
4273 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
4274
4275 r = -EFAULT;
4276 if (copy_to_user(argp, &dbgregs,
4277 sizeof(struct kvm_debugregs)))
4278 break;
4279 r = 0;
4280 break;
4281 }
4282 case KVM_SET_DEBUGREGS: {
4283 struct kvm_debugregs dbgregs;
4284
4285 r = -EFAULT;
4286 if (copy_from_user(&dbgregs, argp,
4287 sizeof(struct kvm_debugregs)))
4288 break;
4289
4290 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
4291 break;
4292 }
2d5b5a66 4293 case KVM_GET_XSAVE: {
254272ce 4294 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
2d5b5a66 4295 r = -ENOMEM;
d1ac91d8 4296 if (!u.xsave)
2d5b5a66
SY		 4297 break;
4298
d1ac91d8 4299 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 4300
4301 r = -EFAULT;
d1ac91d8 4302 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 4303 break;
4304 r = 0;
4305 break;
4306 }
4307 case KVM_SET_XSAVE: {
ff5c2c03 4308 u.xsave = memdup_user(argp, sizeof(*u.xsave));
9b062471
CD		 4309 if (IS_ERR(u.xsave)) {
4310 r = PTR_ERR(u.xsave);
4311 goto out_nofree;
4312 }
2d5b5a66 4313
d1ac91d8 4314 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 4315 break;
4316 }
4317 case KVM_GET_XCRS: {
254272ce 4318 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
2d5b5a66 4319 r = -ENOMEM;
d1ac91d8 4320 if (!u.xcrs)
2d5b5a66
SY		 4321 break;
4322
d1ac91d8 4323 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 4324
4325 r = -EFAULT;
d1ac91d8 4326 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 4327 sizeof(struct kvm_xcrs)))
4328 break;
4329 r = 0;
4330 break;
4331 }
4332 case KVM_SET_XCRS: {
ff5c2c03 4333 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
9b062471
CD		 4334 if (IS_ERR(u.xcrs)) {
4335 r = PTR_ERR(u.xcrs);
4336 goto out_nofree;
4337 }
2d5b5a66 4338
d1ac91d8 4339 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 4340 break;
4341 }
92a1f12d
JR		 4342 case KVM_SET_TSC_KHZ: {
4343 u32 user_tsc_khz;
4344
4345 r = -EINVAL;
92a1f12d
JR		 4346 user_tsc_khz = (u32)arg;
4347
4348 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
4349 goto out;
4350
cc578287
ZA		 4351 if (user_tsc_khz == 0)
4352 user_tsc_khz = tsc_khz;
4353
381d585c
HZ		 4354 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
4355 r = 0;
92a1f12d 4356
92a1f12d
JR		 4357 goto out;
4358 }
4359 case KVM_GET_TSC_KHZ: {
cc578287 4360 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 4361 goto out;
4362 }
1c0b28c2
EM		 4363 case KVM_KVMCLOCK_CTRL: {
4364 r = kvm_set_guest_paused(vcpu);
4365 goto out;
4366 }
5c919412
AS		 4367 case KVM_ENABLE_CAP: {
4368 struct kvm_enable_cap cap;
4369
4370 r = -EFAULT;
4371 if (copy_from_user(&cap, argp, sizeof(cap)))
4372 goto out;
4373 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
4374 break;
4375 }
8fcc4b59
JM		 4376 case KVM_GET_NESTED_STATE: {
4377 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4378 u32 user_data_size;
4379
4380 r = -EINVAL;
4381 if (!kvm_x86_ops->get_nested_state)
4382 break;
4383
4384 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
26b471c7 4385 r = -EFAULT;
8fcc4b59 4386 if (get_user(user_data_size, &user_kvm_nested_state->size))
26b471c7 4387 break;
8fcc4b59
JM		 4388
4389 r = kvm_x86_ops->get_nested_state(vcpu, user_kvm_nested_state,
4390 user_data_size);
4391 if (r < 0)
26b471c7 4392 break;
8fcc4b59
JM		 4393
4394 if (r > user_data_size) {
4395 if (put_user(r, &user_kvm_nested_state->size))
26b471c7
LA		 4396 r = -EFAULT;
4397 else
4398 r = -E2BIG;
4399 break;
8fcc4b59 4400 }
26b471c7 4401
8fcc4b59
JM		 4402 r = 0;
4403 break;
4404 }
4405 case KVM_SET_NESTED_STATE: {
4406 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4407 struct kvm_nested_state kvm_state;
4408
4409 r = -EINVAL;
4410 if (!kvm_x86_ops->set_nested_state)
4411 break;
4412
26b471c7 4413 r = -EFAULT;
8fcc4b59 4414 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
26b471c7 4415 break;
8fcc4b59 4416
26b471c7 4417 r = -EINVAL;
8fcc4b59 4418 if (kvm_state.size < sizeof(kvm_state))
26b471c7 4419 break;
8fcc4b59
JM		 4420
4421 if (kvm_state.flags &
8cab6507
VK		 4422 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
4423 | KVM_STATE_NESTED_EVMCS))
26b471c7 4424 break;
8fcc4b59
JM		 4425
4426 /* nested_run_pending implies guest_mode. */
8cab6507
VK		 4427 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
4428 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
26b471c7 4429 break;
8fcc4b59
JM		 4430
4431 r = kvm_x86_ops->set_nested_state(vcpu, user_kvm_nested_state, &kvm_state);
4432 break;
4433 }
2bc39970
VK		 4434 case KVM_GET_SUPPORTED_HV_CPUID: {
4435 struct kvm_cpuid2 __user *cpuid_arg = argp;
4436 struct kvm_cpuid2 cpuid;
4437
4438 r = -EFAULT;
4439 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4440 goto out;
4441
4442 r = kvm_vcpu_ioctl_get_hv_cpuid(vcpu, &cpuid,
4443 cpuid_arg->entries);
4444 if (r)
4445 goto out;
4446
4447 r = -EFAULT;
4448 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4449 goto out;
4450 r = 0;
4451 break;
4452 }
313a3dc7
CO		 4453 default:
4454 r = -EINVAL;
4455 }
4456out:
d1ac91d8 4457 kfree(u.buffer);
9b062471
CD		 4458out_nofree:
4459 vcpu_put(vcpu);
313a3dc7
CO		 4460 return r;
4461}
4462
1499fa80 4463vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
5b1c1493
CO		 4464{
4465 return VM_FAULT_SIGBUS;
4466}
4467
1fe779f8
CO		 4468static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
4469{
4470 int ret;
4471
4472 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 4473 return -EINVAL;
1fe779f8
CO		 4474 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
4475 return ret;
4476}
4477
b927a3ce
SY		 4478static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
4479 u64 ident_addr)
4480{
2ac52ab8 4481 return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 4482}
4483
1fe779f8 4484static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
bc8a3d89 4485 unsigned long kvm_nr_mmu_pages)
1fe779f8
CO		 4486{
4487 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
4488 return -EINVAL;
4489
79fac95e 4490 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 4491
4492 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 4493 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 4494
79fac95e 4495 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 4496 return 0;
4497}
4498
bc8a3d89 4499static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
1fe779f8 4500{
39de71ec 4501 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 4502}
4503
1fe779f8
CO		 4504static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4505{
90bca052 4506 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4507 int r;
4508
4509 r = 0;
4510 switch (chip->chip_id) {
4511 case KVM_IRQCHIP_PIC_MASTER:
90bca052 4512 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 4513 sizeof(struct kvm_pic_state));
4514 break;
4515 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 4516 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 4517 sizeof(struct kvm_pic_state));
4518 break;
4519 case KVM_IRQCHIP_IOAPIC:
33392b49 4520 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4521 break;
4522 default:
4523 r = -EINVAL;
4524 break;
4525 }
4526 return r;
4527}
4528
4529static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4530{
90bca052 4531 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4532 int r;
4533
4534 r = 0;
4535 switch (chip->chip_id) {
4536 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 4537 spin_lock(&pic->lock);
4538 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 4539 sizeof(struct kvm_pic_state));
90bca052 4540 spin_unlock(&pic->lock);
1fe779f8
CO		 4541 break;
4542 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 4543 spin_lock(&pic->lock);
4544 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 4545 sizeof(struct kvm_pic_state));
90bca052 4546 spin_unlock(&pic->lock);
1fe779f8
CO		 4547 break;
4548 case KVM_IRQCHIP_IOAPIC:
33392b49 4549 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4550 break;
4551 default:
4552 r = -EINVAL;
4553 break;
4554 }
90bca052 4555 kvm_pic_update_irq(pic);
1fe779f8
CO		 4556 return r;
4557}
4558
e0f63cb9
SY		 4559static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4560{
34f3941c
RK		 4561 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4562
4563 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4564
4565 mutex_lock(&kps->lock);
4566 memcpy(ps, &kps->channels, sizeof(*ps));
4567 mutex_unlock(&kps->lock);
2da29bcc 4568 return 0;
e0f63cb9
SY		 4569}
4570
4571static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4572{
0185604c 4573 int i;
09edea72
RK		 4574 struct kvm_pit *pit = kvm->arch.vpit;
4575
4576 mutex_lock(&pit->pit_state.lock);
34f3941c 4577 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 4578 for (i = 0; i < 3; i++)
09edea72
RK		 4579 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4580 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4581 return 0;
e9f42757
BK		 4582}
4583
4584static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4585{
e9f42757
BK		 4586 mutex_lock(&kvm->arch.vpit->pit_state.lock);
4587 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4588 sizeof(ps->channels));
4589 ps->flags = kvm->arch.vpit->pit_state.flags;
4590 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 4591 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 4592 return 0;
e9f42757
BK		 4593}
4594
4595static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4596{
2da29bcc 4597 int start = 0;
0185604c 4598 int i;
e9f42757 4599 u32 prev_legacy, cur_legacy;
09edea72
RK		 4600 struct kvm_pit *pit = kvm->arch.vpit;
4601
4602 mutex_lock(&pit->pit_state.lock);
4603 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 4604 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4605 if (!prev_legacy && cur_legacy)
4606 start = 1;
09edea72
RK		 4607 memcpy(&pit->pit_state.channels, &ps->channels,
4608 sizeof(pit->pit_state.channels));
4609 pit->pit_state.flags = ps->flags;
0185604c 4610 for (i = 0; i < 3; i++)
09edea72 4611 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 4612 start && i == 0);
09edea72 4613 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4614 return 0;
e0f63cb9
SY		 4615}
4616
52d939a0
MT		 4617static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4618 struct kvm_reinject_control *control)
4619{
71474e2f
RK		 4620 struct kvm_pit *pit = kvm->arch.vpit;
4621
4622 if (!pit)
52d939a0 4623 return -ENXIO;
b39c90b6 4624
71474e2f
RK		 4625 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4626 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4627 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4628 */
4629 mutex_lock(&pit->pit_state.lock);
4630 kvm_pit_set_reinject(pit, control->pit_reinject);
4631 mutex_unlock(&pit->pit_state.lock);
b39c90b6 4632
52d939a0
MT		 4633 return 0;
4634}
4635
95d4c16c 4636/**
60c34612
TY		 4637 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4638 * @kvm: kvm instance
4639 * @log: slot id and address to which we copy the log
95d4c16c 4640 *
e108ff2f
PB		 4641 * Steps 1-4 below provide general overview of dirty page logging. See
4642 * kvm_get_dirty_log_protect() function description for additional details.
4643 *
4644 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4645 * always flush the TLB (step 4) even if previous step failed and the dirty
4646 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4647 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4648 * writes will be marked dirty for next log read.
95d4c16c 4649 *
60c34612
TY		 4650 * 1. Take a snapshot of the bit and clear it if needed.
4651 * 2. Write protect the corresponding page.
e108ff2f
PB		 4652 * 3. Copy the snapshot to the userspace.
4653 * 4. Flush TLB's if needed.
5bb064dc 4654 */
60c34612 4655int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 4656{
8fe65a82 4657 bool flush = false;
e108ff2f 4658 int r;
5bb064dc 4659
79fac95e 4660 mutex_lock(&kvm->slots_lock);
5bb064dc 4661
88178fd4
KH		 4662 /*
4663 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4664 */
4665 if (kvm_x86_ops->flush_log_dirty)
4666 kvm_x86_ops->flush_log_dirty(kvm);
4667
8fe65a82 4668 r = kvm_get_dirty_log_protect(kvm, log, &flush);
198c74f4
XG		 4669
4670 /*
4671 * All the TLBs can be flushed out of mmu lock, see the comments in
4672 * kvm_mmu_slot_remove_write_access().
4673 */
e108ff2f 4674 lockdep_assert_held(&kvm->slots_lock);
8fe65a82 4675 if (flush)
2a31b9db
PB		 4676 kvm_flush_remote_tlbs(kvm);
4677
4678 mutex_unlock(&kvm->slots_lock);
4679 return r;
4680}
4681
4682int kvm_vm_ioctl_clear_dirty_log(struct kvm *kvm, struct kvm_clear_dirty_log *log)
4683{
4684 bool flush = false;
4685 int r;
4686
4687 mutex_lock(&kvm->slots_lock);
4688
4689 /*
4690 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4691 */
4692 if (kvm_x86_ops->flush_log_dirty)
4693 kvm_x86_ops->flush_log_dirty(kvm);
4694
4695 r = kvm_clear_dirty_log_protect(kvm, log, &flush);
4696
4697 /*
4698 * All the TLBs can be flushed out of mmu lock, see the comments in
4699 * kvm_mmu_slot_remove_write_access().
4700 */
4701 lockdep_assert_held(&kvm->slots_lock);
4702 if (flush)
198c74f4
XG		 4703 kvm_flush_remote_tlbs(kvm);
4704
79fac95e 4705 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 4706 return r;
4707}
4708
aa2fbe6d
YZ		 4709int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4710 bool line_status)
23d43cf9
CD		 4711{
4712 if (!irqchip_in_kernel(kvm))
4713 return -ENXIO;
4714
4715 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 4716 irq_event->irq, irq_event->level,
4717 line_status);
23d43cf9
CD		 4718 return 0;
4719}
4720
e5d83c74
PB		 4721int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4722 struct kvm_enable_cap *cap)
90de4a18
NA		 4723{
4724 int r;
4725
4726 if (cap->flags)
4727 return -EINVAL;
4728
4729 switch (cap->cap) {
4730 case KVM_CAP_DISABLE_QUIRKS:
4731 kvm->arch.disabled_quirks = cap->args[0];
4732 r = 0;
4733 break;
49df6397
SR		 4734 case KVM_CAP_SPLIT_IRQCHIP: {
4735 mutex_lock(&kvm->lock);
b053b2ae
SR		 4736 r = -EINVAL;
4737 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4738 goto split_irqchip_unlock;
49df6397
SR		 4739 r = -EEXIST;
4740 if (irqchip_in_kernel(kvm))
4741 goto split_irqchip_unlock;
557abc40 4742 if (kvm->created_vcpus)
49df6397
SR		 4743 goto split_irqchip_unlock;
4744 r = kvm_setup_empty_irq_routing(kvm);
5c0aea0e 4745 if (r)
49df6397
SR		 4746 goto split_irqchip_unlock;
4747 /* Pairs with irqchip_in_kernel. */
4748 smp_wmb();
49776faf 4749 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 4750 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 4751 r = 0;
4752split_irqchip_unlock:
4753 mutex_unlock(&kvm->lock);
4754 break;
4755 }
37131313
RK		 4756 case KVM_CAP_X2APIC_API:
4757 r = -EINVAL;
4758 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4759 break;
4760
4761 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4762 kvm->arch.x2apic_format = true;
c519265f
RK		 4763 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4764 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 4765
4766 r = 0;
4767 break;
4d5422ce
WL		 4768 case KVM_CAP_X86_DISABLE_EXITS:
4769 r = -EINVAL;
4770 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
4771 break;
4772
4773 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
4774 kvm_can_mwait_in_guest())
4775 kvm->arch.mwait_in_guest = true;
766d3571 4776 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
caa057a2 4777 kvm->arch.hlt_in_guest = true;
b31c114b
WL		 4778 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
4779 kvm->arch.pause_in_guest = true;
b5170063
WL		 4780 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE)
4781 kvm->arch.cstate_in_guest = true;
4d5422ce
WL		 4782 r = 0;
4783 break;
6fbbde9a
DS		 4784 case KVM_CAP_MSR_PLATFORM_INFO:
4785 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
4786 r = 0;
c4f55198
JM		 4787 break;
4788 case KVM_CAP_EXCEPTION_PAYLOAD:
4789 kvm->arch.exception_payload_enabled = cap->args[0];
4790 r = 0;
6fbbde9a 4791 break;
90de4a18
NA		 4792 default:
4793 r = -EINVAL;
4794 break;
4795 }
4796 return r;
4797}
4798
1fe779f8
CO		 4799long kvm_arch_vm_ioctl(struct file *filp,
4800 unsigned int ioctl, unsigned long arg)
4801{
4802 struct kvm *kvm = filp->private_data;
4803 void __user *argp = (void __user *)arg;
367e1319 4804 int r = -ENOTTY;
f0d66275
DH		 4805 /*
4806 * This union makes it completely explicit to gcc-3.x
4807 * that these two variables' stack usage should be
4808 * combined, not added together.
4809 */
4810 union {
4811 struct kvm_pit_state ps;
e9f42757 4812 struct kvm_pit_state2 ps2;
c5ff41ce 4813 struct kvm_pit_config pit_config;
f0d66275 4814 } u;
1fe779f8
CO		 4815
4816 switch (ioctl) {
4817 case KVM_SET_TSS_ADDR:
4818 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 4819 break;
b927a3ce
SY		 4820 case KVM_SET_IDENTITY_MAP_ADDR: {
4821 u64 ident_addr;
4822
1af1ac91
DH		 4823 mutex_lock(&kvm->lock);
4824 r = -EINVAL;
4825 if (kvm->created_vcpus)
4826 goto set_identity_unlock;
b927a3ce 4827 r = -EFAULT;
0e96f31e 4828 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
1af1ac91 4829 goto set_identity_unlock;
b927a3ce 4830 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
1af1ac91
DH		 4831set_identity_unlock:
4832 mutex_unlock(&kvm->lock);
b927a3ce
SY		 4833 break;
4834 }
1fe779f8
CO		 4835 case KVM_SET_NR_MMU_PAGES:
4836 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 4837 break;
4838 case KVM_GET_NR_MMU_PAGES:
4839 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4840 break;
3ddea128 4841 case KVM_CREATE_IRQCHIP: {
3ddea128 4842 mutex_lock(&kvm->lock);
09941366 4843
3ddea128 4844 r = -EEXIST;
35e6eaa3 4845 if (irqchip_in_kernel(kvm))
3ddea128 4846 goto create_irqchip_unlock;
09941366 4847
3e515705 4848 r = -EINVAL;
557abc40 4849 if (kvm->created_vcpus)
3e515705 4850 goto create_irqchip_unlock;
09941366
RK		 4851
4852 r = kvm_pic_init(kvm);
4853 if (r)
3ddea128 4854 goto create_irqchip_unlock;
09941366
RK		 4855
4856 r = kvm_ioapic_init(kvm);
4857 if (r) {
09941366 4858 kvm_pic_destroy(kvm);
3ddea128 4859 goto create_irqchip_unlock;
09941366
RK		 4860 }
4861
399ec807
AK		 4862 r = kvm_setup_default_irq_routing(kvm);
4863 if (r) {
72bb2fcd 4864 kvm_ioapic_destroy(kvm);
09941366 4865 kvm_pic_destroy(kvm);
71ba994c 4866 goto create_irqchip_unlock;
399ec807 4867 }
49776faf 4868 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4869 smp_wmb();
49776faf 4870 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4871 create_irqchip_unlock:
4872 mutex_unlock(&kvm->lock);
1fe779f8 4873 break;
3ddea128 4874 }
7837699f 4875 case KVM_CREATE_PIT:
c5ff41ce
JK		 4876 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4877 goto create_pit;
4878 case KVM_CREATE_PIT2:
4879 r = -EFAULT;
4880 if (copy_from_user(&u.pit_config, argp,
4881 sizeof(struct kvm_pit_config)))
4882 goto out;
4883 create_pit:
250715a6 4884 mutex_lock(&kvm->lock);
269e05e4
AK		 4885 r = -EEXIST;
4886 if (kvm->arch.vpit)
4887 goto create_pit_unlock;
7837699f 4888 r = -ENOMEM;
c5ff41ce 4889 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4890 if (kvm->arch.vpit)
4891 r = 0;
269e05e4 4892 create_pit_unlock:
250715a6 4893 mutex_unlock(&kvm->lock);
7837699f 4894 break;
1fe779f8
CO		 4895 case KVM_GET_IRQCHIP: {
4896 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4897 struct kvm_irqchip *chip;
1fe779f8 4898
ff5c2c03
SL		 4899 chip = memdup_user(argp, sizeof(*chip));
4900 if (IS_ERR(chip)) {
4901 r = PTR_ERR(chip);
1fe779f8 4902 goto out;
ff5c2c03
SL		 4903 }
4904
1fe779f8 4905 r = -ENXIO;
826da321 4906 if (!irqchip_kernel(kvm))
f0d66275
DH		 4907 goto get_irqchip_out;
4908 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4909 if (r)
f0d66275 4910 goto get_irqchip_out;
1fe779f8 4911 r = -EFAULT;
0e96f31e 4912 if (copy_to_user(argp, chip, sizeof(*chip)))
f0d66275 4913 goto get_irqchip_out;
1fe779f8 4914 r = 0;
f0d66275
DH		 4915 get_irqchip_out:
4916 kfree(chip);
1fe779f8
CO		 4917 break;
4918 }
4919 case KVM_SET_IRQCHIP: {
4920 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4921 struct kvm_irqchip *chip;
1fe779f8 4922
ff5c2c03
SL		 4923 chip = memdup_user(argp, sizeof(*chip));
4924 if (IS_ERR(chip)) {
4925 r = PTR_ERR(chip);
1fe779f8 4926 goto out;
ff5c2c03
SL		 4927 }
4928
1fe779f8 4929 r = -ENXIO;
826da321 4930 if (!irqchip_kernel(kvm))
f0d66275
DH		 4931 goto set_irqchip_out;
4932 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4933 if (r)
f0d66275 4934 goto set_irqchip_out;
1fe779f8 4935 r = 0;
f0d66275
DH		 4936 set_irqchip_out:
4937 kfree(chip);
1fe779f8
CO		 4938 break;
4939 }
e0f63cb9 4940 case KVM_GET_PIT: {
e0f63cb9 4941 r = -EFAULT;
f0d66275 4942 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4943 goto out;
4944 r = -ENXIO;
4945 if (!kvm->arch.vpit)
4946 goto out;
f0d66275 4947 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4948 if (r)
4949 goto out;
4950 r = -EFAULT;
f0d66275 4951 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4952 goto out;
4953 r = 0;
4954 break;
4955 }
4956 case KVM_SET_PIT: {
e0f63cb9 4957 r = -EFAULT;
0e96f31e 4958 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
e0f63cb9
SY		 4959 goto out;
4960 r = -ENXIO;
4961 if (!kvm->arch.vpit)
4962 goto out;
f0d66275 4963 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4964 break;
4965 }
e9f42757
BK		 4966 case KVM_GET_PIT2: {
4967 r = -ENXIO;
4968 if (!kvm->arch.vpit)
4969 goto out;
4970 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4971 if (r)
4972 goto out;
4973 r = -EFAULT;
4974 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4975 goto out;
4976 r = 0;
4977 break;
4978 }
4979 case KVM_SET_PIT2: {
4980 r = -EFAULT;
4981 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4982 goto out;
4983 r = -ENXIO;
4984 if (!kvm->arch.vpit)
4985 goto out;
4986 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4987 break;
4988 }
52d939a0
MT		 4989 case KVM_REINJECT_CONTROL: {
4990 struct kvm_reinject_control control;
4991 r = -EFAULT;
4992 if (copy_from_user(&control, argp, sizeof(control)))
4993 goto out;
4994 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4995 break;
4996 }
d71ba788
PB		 4997 case KVM_SET_BOOT_CPU_ID:
4998 r = 0;
4999 mutex_lock(&kvm->lock);
557abc40 5000 if (kvm->created_vcpus)
d71ba788
PB		 5001 r = -EBUSY;
5002 else
5003 kvm->arch.bsp_vcpu_id = arg;
5004 mutex_unlock(&kvm->lock);
5005 break;
ffde22ac 5006 case KVM_XEN_HVM_CONFIG: {
51776043 5007 struct kvm_xen_hvm_config xhc;
ffde22ac 5008 r = -EFAULT;
51776043 5009 if (copy_from_user(&xhc, argp, sizeof(xhc)))
ffde22ac
ES		 5010 goto out;
5011 r = -EINVAL;
51776043 5012 if (xhc.flags)
ffde22ac 5013 goto out;
51776043 5014 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
ffde22ac
ES		 5015 r = 0;
5016 break;
5017 }
afbcf7ab 5018 case KVM_SET_CLOCK: {
afbcf7ab
GC		 5019 struct kvm_clock_data user_ns;
5020 u64 now_ns;
afbcf7ab
GC		 5021
5022 r = -EFAULT;
5023 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
5024 goto out;
5025
5026 r = -EINVAL;
5027 if (user_ns.flags)
5028 goto out;
5029
5030 r = 0;
0bc48bea
RK		 5031 /*
5032 * TODO: userspace has to take care of races with VCPU_RUN, so
5033 * kvm_gen_update_masterclock() can be cut down to locked
5034 * pvclock_update_vm_gtod_copy().
5035 */
5036 kvm_gen_update_masterclock(kvm);
e891a32e 5037 now_ns = get_kvmclock_ns(kvm);
108b249c 5038 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
0bc48bea 5039 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
afbcf7ab
GC		 5040 break;
5041 }
5042 case KVM_GET_CLOCK: {
afbcf7ab
GC		 5043 struct kvm_clock_data user_ns;
5044 u64 now_ns;
5045
e891a32e 5046 now_ns = get_kvmclock_ns(kvm);
108b249c 5047 user_ns.clock = now_ns;
e3fd9a93 5048 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 5049 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 5050
5051 r = -EFAULT;
5052 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
5053 goto out;
5054 r = 0;
5055 break;
5056 }
5acc5c06
BS		 5057 case KVM_MEMORY_ENCRYPT_OP: {
5058 r = -ENOTTY;
5059 if (kvm_x86_ops->mem_enc_op)
5060 r = kvm_x86_ops->mem_enc_op(kvm, argp);
5061 break;
5062 }
69eaedee
BS		 5063 case KVM_MEMORY_ENCRYPT_REG_REGION: {
5064 struct kvm_enc_region region;
5065
5066 r = -EFAULT;
5067 if (copy_from_user(&region, argp, sizeof(region)))
5068 goto out;
5069
5070 r = -ENOTTY;
5071 if (kvm_x86_ops->mem_enc_reg_region)
5072 r = kvm_x86_ops->mem_enc_reg_region(kvm, &region);
5073 break;
5074 }
5075 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
5076 struct kvm_enc_region region;
5077
5078 r = -EFAULT;
5079 if (copy_from_user(&region, argp, sizeof(region)))
5080 goto out;
5081
5082 r = -ENOTTY;
5083 if (kvm_x86_ops->mem_enc_unreg_region)
5084 r = kvm_x86_ops->mem_enc_unreg_region(kvm, &region);
5085 break;
5086 }
faeb7833
RK		 5087 case KVM_HYPERV_EVENTFD: {
5088 struct kvm_hyperv_eventfd hvevfd;
5089
5090 r = -EFAULT;
5091 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
5092 goto out;
5093 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
5094 break;
5095 }
66bb8a06
EH		 5096 case KVM_SET_PMU_EVENT_FILTER:
5097 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp);
5098 break;
1fe779f8 5099 default:
ad6260da 5100 r = -ENOTTY;
1fe779f8
CO		 5101 }
5102out:
5103 return r;
5104}
5105
a16b043c 5106static void kvm_init_msr_list(void)
043405e1
CO		 5107{
5108 u32 dummy[2];
5109 unsigned i, j;
5110
e2ada66e
JM		 5111 BUILD_BUG_ON_MSG(INTEL_PMC_MAX_FIXED != 4,
5112 "Please update the fixed PMCs in msrs_to_save[]");
5113 BUILD_BUG_ON_MSG(INTEL_PMC_MAX_GENERIC != 32,
5114 "Please update the generic perfctr/eventsel MSRs in msrs_to_save[]");
5115
62ef68bb 5116 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 5117 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
5118 continue;
93c4adc7
PB		 5119
5120 /*
5121 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 5122 * to the guests in some cases.
93c4adc7
PB		 5123 */
5124 switch (msrs_to_save[i]) {
5125 case MSR_IA32_BNDCFGS:
503234b3 5126 if (!kvm_mpx_supported())
93c4adc7
PB		 5127 continue;
5128 break;
9dbe6cf9
PB		 5129 case MSR_TSC_AUX:
5130 if (!kvm_x86_ops->rdtscp_supported())
5131 continue;
5132 break;
bf8c55d8
CP		 5133 case MSR_IA32_RTIT_CTL:
5134 case MSR_IA32_RTIT_STATUS:
5135 if (!kvm_x86_ops->pt_supported())
5136 continue;
5137 break;
5138 case MSR_IA32_RTIT_CR3_MATCH:
5139 if (!kvm_x86_ops->pt_supported() ||
5140 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
5141 continue;
5142 break;
5143 case MSR_IA32_RTIT_OUTPUT_BASE:
5144 case MSR_IA32_RTIT_OUTPUT_MASK:
5145 if (!kvm_x86_ops->pt_supported() ||
5146 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
5147 !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
5148 continue;
5149 break;
5150 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: {
5151 if (!kvm_x86_ops->pt_supported() ||
5152 msrs_to_save[i] - MSR_IA32_RTIT_ADDR0_A >=
5153 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
5154 continue;
5155 break;
5156 }
93c4adc7
PB		 5157 default:
5158 break;
5159 }
5160
043405e1
CO		 5161 if (j < i)
5162 msrs_to_save[j] = msrs_to_save[i];
5163 j++;
5164 }
5165 num_msrs_to_save = j;
62ef68bb
PB		 5166
5167 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
bc226f07
TL		 5168 if (!kvm_x86_ops->has_emulated_msr(emulated_msrs[i]))
5169 continue;
62ef68bb
PB		 5170
5171 if (j < i)
5172 emulated_msrs[j] = emulated_msrs[i];
5173 j++;
5174 }
5175 num_emulated_msrs = j;
801e459a
TL		 5176
5177 for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) {
5178 struct kvm_msr_entry msr;
5179
5180 msr.index = msr_based_features[i];
66421c1e 5181 if (kvm_get_msr_feature(&msr))
801e459a
TL		 5182 continue;
5183
5184 if (j < i)
5185 msr_based_features[j] = msr_based_features[i];
5186 j++;
5187 }
5188 num_msr_based_features = j;
043405e1
CO		 5189}
5190
bda9020e
MT		 5191static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
5192 const void *v)
bbd9b64e 5193{
70252a10
AK		 5194 int handled = 0;
5195 int n;
5196
5197 do {
5198 n = min(len, 8);
bce87cce 5199 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 5200 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
5201 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 5202 break;
5203 handled += n;
5204 addr += n;
5205 len -= n;
5206 v += n;
5207 } while (len);
bbd9b64e 5208
70252a10 5209 return handled;
bbd9b64e
CO		 5210}
5211
bda9020e 5212static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 5213{
70252a10
AK		 5214 int handled = 0;
5215 int n;
5216
5217 do {
5218 n = min(len, 8);
bce87cce 5219 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 5220 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
5221 addr, n, v))
5222 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10 5223 break;
e39d200f 5224 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
70252a10
AK		 5225 handled += n;
5226 addr += n;
5227 len -= n;
5228 v += n;
5229 } while (len);
bbd9b64e 5230
70252a10 5231 return handled;
bbd9b64e
CO		 5232}
5233
2dafc6c2
GN		 5234static void kvm_set_segment(struct kvm_vcpu *vcpu,
5235 struct kvm_segment *var, int seg)
5236{
5237 kvm_x86_ops->set_segment(vcpu, var, seg);
5238}
5239
5240void kvm_get_segment(struct kvm_vcpu *vcpu,
5241 struct kvm_segment *var, int seg)
5242{
5243 kvm_x86_ops->get_segment(vcpu, var, seg);
5244}
5245
54987b7a
PB		 5246gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
5247 struct x86_exception *exception)
02f59dc9
JR		 5248{
5249 gpa_t t_gpa;
02f59dc9
JR		 5250
5251 BUG_ON(!mmu_is_nested(vcpu));
5252
5253 /* NPT walks are always user-walks */
5254 access |= PFERR_USER_MASK;
44dd3ffa 5255 t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 5256
5257 return t_gpa;
5258}
5259
ab9ae313
AK		 5260gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
5261 struct x86_exception *exception)
1871c602
GN		 5262{
5263 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 5264 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 5265}
5266
ab9ae313
AK		 5267 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
5268 struct x86_exception *exception)
1871c602
GN		 5269{
5270 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5271 access |= PFERR_FETCH_MASK;
ab9ae313 5272 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 5273}
5274
ab9ae313
AK		 5275gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
5276 struct x86_exception *exception)
1871c602
GN		 5277{
5278 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5279 access |= PFERR_WRITE_MASK;
ab9ae313 5280 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 5281}
5282
5283/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 5284gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
5285 struct x86_exception *exception)
1871c602 5286{
ab9ae313 5287 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 5288}
5289
5290static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5291 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 5292 struct x86_exception *exception)
bbd9b64e
CO		 5293{
5294 void *data = val;
10589a46 5295 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 5296
5297 while (bytes) {
14dfe855 5298 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 5299 exception);
bbd9b64e 5300 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 5301 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 5302 int ret;
5303
bcc55cba 5304 if (gpa == UNMAPPED_GVA)
ab9ae313 5305 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 5306 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
5307 offset, toread);
10589a46 5308 if (ret < 0) {
c3cd7ffa 5309 r = X86EMUL_IO_NEEDED;
10589a46
MT		 5310 goto out;
5311 }
bbd9b64e 5312
77c2002e
IE		 5313 bytes -= toread;
5314 data += toread;
5315 addr += toread;
bbd9b64e 5316 }
10589a46 5317out:
10589a46 5318 return r;
bbd9b64e 5319}
77c2002e 5320
1871c602 5321/* used for instruction fetching */
0f65dd70
AK		 5322static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
5323 gva_t addr, void *val, unsigned int bytes,
bcc55cba 5324 struct x86_exception *exception)
1871c602 5325{
0f65dd70 5326 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 5327 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 5328 unsigned offset;
5329 int ret;
0f65dd70 5330
44583cba
PB		 5331 /* Inline kvm_read_guest_virt_helper for speed. */
5332 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
5333 exception);
5334 if (unlikely(gpa == UNMAPPED_GVA))
5335 return X86EMUL_PROPAGATE_FAULT;
5336
5337 offset = addr & (PAGE_SIZE-1);
5338 if (WARN_ON(offset + bytes > PAGE_SIZE))
5339 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 5340 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
5341 offset, bytes);
44583cba
PB		 5342 if (unlikely(ret < 0))
5343 return X86EMUL_IO_NEEDED;
5344
5345 return X86EMUL_CONTINUE;
1871c602
GN		 5346}
5347
ce14e868 5348int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
0f65dd70 5349 gva_t addr, void *val, unsigned int bytes,
bcc55cba 5350 struct x86_exception *exception)
1871c602
GN		 5351{
5352 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 5353
353c0956
PB		 5354 /*
5355 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5356 * is returned, but our callers are not ready for that and they blindly
5357 * call kvm_inject_page_fault. Ensure that they at least do not leak
5358 * uninitialized kernel stack memory into cr2 and error code.
5359 */
5360 memset(exception, 0, sizeof(*exception));
1871c602 5361 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 5362 exception);
1871c602 5363}
064aea77 5364EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 5365
ce14e868
PB		 5366static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
5367 gva_t addr, void *val, unsigned int bytes,
3c9fa24c 5368 struct x86_exception *exception, bool system)
1871c602 5369{
0f65dd70 5370 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3c9fa24c
PB		 5371 u32 access = 0;
5372
5373 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5374 access |= PFERR_USER_MASK;
5375
5376 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
1871c602
GN		 5377}
5378
7a036a6f
RK		 5379static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
5380 unsigned long addr, void *val, unsigned int bytes)
5381{
5382 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5383 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
5384
5385 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
5386}
5387
ce14e868
PB		 5388static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5389 struct kvm_vcpu *vcpu, u32 access,
5390 struct x86_exception *exception)
77c2002e
IE		 5391{
5392 void *data = val;
5393 int r = X86EMUL_CONTINUE;
5394
5395 while (bytes) {
14dfe855 5396 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
ce14e868 5397 access,
ab9ae313 5398 exception);
77c2002e
IE		 5399 unsigned offset = addr & (PAGE_SIZE-1);
5400 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
5401 int ret;
5402
bcc55cba 5403 if (gpa == UNMAPPED_GVA)
ab9ae313 5404 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 5405 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 5406 if (ret < 0) {
c3cd7ffa 5407 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 5408 goto out;
5409 }
5410
5411 bytes -= towrite;
5412 data += towrite;
5413 addr += towrite;
5414 }
5415out:
5416 return r;
5417}
ce14e868
PB		 5418
5419static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
3c9fa24c
PB		 5420 unsigned int bytes, struct x86_exception *exception,
5421 bool system)
ce14e868
PB		 5422{
5423 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3c9fa24c
PB		 5424 u32 access = PFERR_WRITE_MASK;
5425
5426 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5427 access |= PFERR_USER_MASK;
ce14e868
PB		 5428
5429 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
3c9fa24c 5430 access, exception);
ce14e868
PB		 5431}
5432
5433int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
5434 unsigned int bytes, struct x86_exception *exception)
5435{
c595ceee
PB		 5436 /* kvm_write_guest_virt_system can pull in tons of pages. */
5437 vcpu->arch.l1tf_flush_l1d = true;
5438
541ab2ae
FH		 5439 /*
5440 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5441 * is returned, but our callers are not ready for that and they blindly
5442 * call kvm_inject_page_fault. Ensure that they at least do not leak
5443 * uninitialized kernel stack memory into cr2 and error code.
5444 */
5445 memset(exception, 0, sizeof(*exception));
ce14e868
PB		 5446 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5447 PFERR_WRITE_MASK, exception);
5448}
6a4d7550 5449EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 5450
082d06ed
WL		 5451int handle_ud(struct kvm_vcpu *vcpu)
5452{
6c86eedc 5453 int emul_type = EMULTYPE_TRAP_UD;
6c86eedc
WL		 5454 char sig[5]; /* ud2; .ascii "kvm" */
5455 struct x86_exception e;
5456
5457 if (force_emulation_prefix &&
3c9fa24c
PB		 5458 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
5459 sig, sizeof(sig), &e) == 0 &&
6c86eedc
WL		 5460 memcmp(sig, "\xf\xbkvm", sizeof(sig)) == 0) {
5461 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
b4000606 5462 emul_type = EMULTYPE_TRAP_UD_FORCED;
6c86eedc 5463 }
082d06ed 5464
60fc3d02 5465 return kvm_emulate_instruction(vcpu, emul_type);
082d06ed
WL		 5466}
5467EXPORT_SYMBOL_GPL(handle_ud);
5468
0f89b207
TL		 5469static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5470 gpa_t gpa, bool write)
5471{
5472 /* For APIC access vmexit */
5473 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5474 return 1;
5475
5476 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
5477 trace_vcpu_match_mmio(gva, gpa, write, true);
5478 return 1;
5479 }
5480
5481 return 0;
5482}
5483
af7cc7d1
XG		 5484static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5485 gpa_t *gpa, struct x86_exception *exception,
5486 bool write)
5487{
97d64b78
AK		 5488 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
5489 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 5490
be94f6b7
HH		 5491 /*
5492 * currently PKRU is only applied to ept enabled guest so
5493 * there is no pkey in EPT page table for L1 guest or EPT
5494 * shadow page table for L2 guest.
5495 */
97d64b78 5496 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 5497 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
871bd034 5498 vcpu->arch.mmio_access, 0, access)) {
bebb106a
XG		 5499 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
5500 (gva & (PAGE_SIZE - 1));
4f022648 5501 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 5502 return 1;
5503 }
5504
af7cc7d1
XG		 5505 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5506
5507 if (*gpa == UNMAPPED_GVA)
5508 return -1;
5509
0f89b207 5510 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 5511}
5512
3200f405 5513int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 5514 const void *val, int bytes)
bbd9b64e
CO		 5515{
5516 int ret;
5517
54bf36aa 5518 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 5519 if (ret < 0)
bbd9b64e 5520 return 0;
0eb05bf2 5521 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 5522 return 1;
5523}
5524
77d197b2
XG		 5525struct read_write_emulator_ops {
5526 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
5527 int bytes);
5528 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
5529 void *val, int bytes);
5530 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5531 int bytes, void *val);
5532 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5533 void *val, int bytes);
5534 bool write;
5535};
5536
5537static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
5538{
5539 if (vcpu->mmio_read_completed) {
77d197b2 5540 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
e39d200f 5541 vcpu->mmio_fragments[0].gpa, val);
77d197b2
XG		 5542 vcpu->mmio_read_completed = 0;
5543 return 1;
5544 }
5545
5546 return 0;
5547}
5548
5549static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5550 void *val, int bytes)
5551{
54bf36aa 5552 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 5553}
5554
5555static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5556 void *val, int bytes)
5557{
5558 return emulator_write_phys(vcpu, gpa, val, bytes);
5559}
5560
5561static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
5562{
e39d200f 5563 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
77d197b2
XG		 5564 return vcpu_mmio_write(vcpu, gpa, bytes, val);
5565}
5566
5567static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5568 void *val, int bytes)
5569{
e39d200f 5570 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
77d197b2
XG		 5571 return X86EMUL_IO_NEEDED;
5572}
5573
5574static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5575 void *val, int bytes)
5576{
f78146b0
AK		 5577 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
5578
87da7e66 5579 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 5580 return X86EMUL_CONTINUE;
5581}
5582
0fbe9b0b 5583static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 5584 .read_write_prepare = read_prepare,
5585 .read_write_emulate = read_emulate,
5586 .read_write_mmio = vcpu_mmio_read,
5587 .read_write_exit_mmio = read_exit_mmio,
5588};
5589
0fbe9b0b 5590static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 5591 .read_write_emulate = write_emulate,
5592 .read_write_mmio = write_mmio,
5593 .read_write_exit_mmio = write_exit_mmio,
5594 .write = true,
5595};
5596
22388a3c
XG		 5597static int emulator_read_write_onepage(unsigned long addr, void *val,
5598 unsigned int bytes,
5599 struct x86_exception *exception,
5600 struct kvm_vcpu *vcpu,
0fbe9b0b 5601 const struct read_write_emulator_ops *ops)
bbd9b64e 5602{
af7cc7d1
XG		 5603 gpa_t gpa;
5604 int handled, ret;
22388a3c 5605 bool write = ops->write;
f78146b0 5606 struct kvm_mmio_fragment *frag;
0f89b207
TL		 5607 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5608
5609 /*
5610 * If the exit was due to a NPF we may already have a GPA.
5611 * If the GPA is present, use it to avoid the GVA to GPA table walk.
5612 * Note, this cannot be used on string operations since string
5613 * operation using rep will only have the initial GPA from the NPF
5614 * occurred.
5615 */
5616 if (vcpu->arch.gpa_available &&
5617 emulator_can_use_gpa(ctxt) &&
618232e2
BS		 5618 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
5619 gpa = vcpu->arch.gpa_val;
5620 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
5621 } else {
5622 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
5623 if (ret < 0)
5624 return X86EMUL_PROPAGATE_FAULT;
0f89b207 5625 }
10589a46 5626
618232e2 5627 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 5628 return X86EMUL_CONTINUE;
5629
bbd9b64e
CO		 5630 /*
5631 * Is this MMIO handled locally?
5632 */
22388a3c 5633 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 5634 if (handled == bytes)
bbd9b64e 5635 return X86EMUL_CONTINUE;
bbd9b64e 5636
70252a10
AK		 5637 gpa += handled;
5638 bytes -= handled;
5639 val += handled;
5640
87da7e66
XG		 5641 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5642 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5643 frag->gpa = gpa;
5644 frag->data = val;
5645 frag->len = bytes;
f78146b0 5646 return X86EMUL_CONTINUE;
bbd9b64e
CO		 5647}
5648
52eb5a6d
XL		 5649static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5650 unsigned long addr,
22388a3c
XG		 5651 void *val, unsigned int bytes,
5652 struct x86_exception *exception,
0fbe9b0b 5653 const struct read_write_emulator_ops *ops)
bbd9b64e 5654{
0f65dd70 5655 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 5656 gpa_t gpa;
5657 int rc;
5658
5659 if (ops->read_write_prepare &&
5660 ops->read_write_prepare(vcpu, val, bytes))
5661 return X86EMUL_CONTINUE;
5662
5663 vcpu->mmio_nr_fragments = 0;
0f65dd70 5664
bbd9b64e
CO		 5665 /* Crossing a page boundary? */
5666 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 5667 int now;
bbd9b64e
CO		 5668
5669 now = -addr & ~PAGE_MASK;
22388a3c
XG		 5670 rc = emulator_read_write_onepage(addr, val, now, exception,
5671 vcpu, ops);
5672
bbd9b64e
CO		 5673 if (rc != X86EMUL_CONTINUE)
5674 return rc;
5675 addr += now;
bac15531
NA		 5676 if (ctxt->mode != X86EMUL_MODE_PROT64)
5677 addr = (u32)addr;
bbd9b64e
CO		 5678 val += now;
5679 bytes -= now;
5680 }
22388a3c 5681
f78146b0
AK		 5682 rc = emulator_read_write_onepage(addr, val, bytes, exception,
5683 vcpu, ops);
5684 if (rc != X86EMUL_CONTINUE)
5685 return rc;
5686
5687 if (!vcpu->mmio_nr_fragments)
5688 return rc;
5689
5690 gpa = vcpu->mmio_fragments[0].gpa;
5691
5692 vcpu->mmio_needed = 1;
5693 vcpu->mmio_cur_fragment = 0;
5694
87da7e66 5695 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 5696 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5697 vcpu->run->exit_reason = KVM_EXIT_MMIO;
5698 vcpu->run->mmio.phys_addr = gpa;
5699
5700 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 5701}
5702
5703static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5704 unsigned long addr,
5705 void *val,
5706 unsigned int bytes,
5707 struct x86_exception *exception)
5708{
5709 return emulator_read_write(ctxt, addr, val, bytes,
5710 exception, &read_emultor);
5711}
5712
52eb5a6d 5713static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 5714 unsigned long addr,
5715 const void *val,
5716 unsigned int bytes,
5717 struct x86_exception *exception)
5718{
5719 return emulator_read_write(ctxt, addr, (void *)val, bytes,
5720 exception, &write_emultor);
bbd9b64e 5721}
bbd9b64e 5722
daea3e73
AK		 5723#define CMPXCHG_TYPE(t, ptr, old, new) \
5724 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5725
5726#ifdef CONFIG_X86_64
5727# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5728#else
5729# define CMPXCHG64(ptr, old, new) \
9749a6c0 5730 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 5731#endif
5732
0f65dd70
AK		 5733static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5734 unsigned long addr,
bbd9b64e
CO		 5735 const void *old,
5736 const void *new,
5737 unsigned int bytes,
0f65dd70 5738 struct x86_exception *exception)
bbd9b64e 5739{
42e35f80 5740 struct kvm_host_map map;
0f65dd70 5741 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73 5742 gpa_t gpa;
daea3e73
AK		 5743 char *kaddr;
5744 bool exchanged;
2bacc55c 5745
daea3e73
AK		 5746 /* guests cmpxchg8b have to be emulated atomically */
5747 if (bytes > 8 || (bytes & (bytes - 1)))
5748 goto emul_write;
10589a46 5749
daea3e73 5750 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 5751
daea3e73
AK		 5752 if (gpa == UNMAPPED_GVA ||
5753 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5754 goto emul_write;
2bacc55c 5755
daea3e73
AK		 5756 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5757 goto emul_write;
72dc67a6 5758
42e35f80 5759 if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map))
c19b8bd6 5760 goto emul_write;
72dc67a6 5761
42e35f80
KA		 5762 kaddr = map.hva + offset_in_page(gpa);
5763
daea3e73
AK		 5764 switch (bytes) {
5765 case 1:
5766 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5767 break;
5768 case 2:
5769 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5770 break;
5771 case 4:
5772 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5773 break;
5774 case 8:
5775 exchanged = CMPXCHG64(kaddr, old, new);
5776 break;
5777 default:
5778 BUG();
2bacc55c 5779 }
42e35f80
KA		 5780
5781 kvm_vcpu_unmap(vcpu, &map, true);
daea3e73
AK		 5782
5783 if (!exchanged)
5784 return X86EMUL_CMPXCHG_FAILED;
5785
0eb05bf2 5786 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 5787
5788 return X86EMUL_CONTINUE;
4a5f48f6 5789
3200f405 5790emul_write:
daea3e73 5791 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 5792
0f65dd70 5793 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 5794}
5795
cf8f70bf
GN		 5796static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5797{
cbfc6c91 5798 int r = 0, i;
cf8f70bf 5799
cbfc6c91
WL		 5800 for (i = 0; i < vcpu->arch.pio.count; i++) {
5801 if (vcpu->arch.pio.in)
5802 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5803 vcpu->arch.pio.size, pd);
5804 else
5805 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5806 vcpu->arch.pio.port, vcpu->arch.pio.size,
5807 pd);
5808 if (r)
5809 break;
5810 pd += vcpu->arch.pio.size;
5811 }
cf8f70bf
GN		 5812 return r;
5813}
5814
6f6fbe98
XG		 5815static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5816 unsigned short port, void *val,
5817 unsigned int count, bool in)
cf8f70bf 5818{
cf8f70bf 5819 vcpu->arch.pio.port = port;
6f6fbe98 5820 vcpu->arch.pio.in = in;
7972995b 5821 vcpu->arch.pio.count = count;
cf8f70bf
GN		 5822 vcpu->arch.pio.size = size;
5823
5824 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 5825 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5826 return 1;
5827 }
5828
5829 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 5830 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 5831 vcpu->run->io.size = size;
5832 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5833 vcpu->run->io.count = count;
5834 vcpu->run->io.port = port;
5835
5836 return 0;
5837}
5838
6f6fbe98
XG		 5839static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5840 int size, unsigned short port, void *val,
5841 unsigned int count)
cf8f70bf 5842{
ca1d4a9e 5843 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 5844 int ret;
ca1d4a9e 5845
6f6fbe98
XG		 5846 if (vcpu->arch.pio.count)
5847 goto data_avail;
cf8f70bf 5848
cbfc6c91
WL		 5849 memset(vcpu->arch.pio_data, 0, size * count);
5850
6f6fbe98
XG		 5851 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5852 if (ret) {
5853data_avail:
5854 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 5855 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 5856 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5857 return 1;
5858 }
5859
cf8f70bf
GN		 5860 return 0;
5861}
5862
6f6fbe98
XG		 5863static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5864 int size, unsigned short port,
5865 const void *val, unsigned int count)
5866{
5867 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5868
5869 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 5870 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 5871 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5872}
5873
bbd9b64e
CO		 5874static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5875{
5876 return kvm_x86_ops->get_segment_base(vcpu, seg);
5877}
5878
3cb16fe7 5879static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 5880{
3cb16fe7 5881 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 5882}
5883
ae6a2375 5884static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 5885{
5886 if (!need_emulate_wbinvd(vcpu))
5887 return X86EMUL_CONTINUE;
5888
5889 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 5890 int cpu = get_cpu();
5891
5892 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 5893 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5894 wbinvd_ipi, NULL, 1);
2eec7343 5895 put_cpu();
f5f48ee1 5896 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 5897 } else
5898 wbinvd();
f5f48ee1
SY		 5899 return X86EMUL_CONTINUE;
5900}
5cb56059
JS		 5901
5902int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5903{
6affcbed
KH		 5904 kvm_emulate_wbinvd_noskip(vcpu);
5905 return kvm_skip_emulated_instruction(vcpu);
5cb56059 5906}
f5f48ee1
SY		 5907EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5908
5cb56059
JS		 5909
5910
bcaf5cc5
AK		 5911static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5912{
5cb56059 5913 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 5914}
5915
52eb5a6d
XL		 5916static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5917 unsigned long *dest)
bbd9b64e 5918{
16f8a6f9 5919 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 5920}
5921
52eb5a6d
XL		 5922static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5923 unsigned long value)
bbd9b64e 5924{
338dbc97 5925
717746e3 5926 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 5927}
5928
52a46617 5929static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 5930{
52a46617 5931 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 5932}
5933
717746e3 5934static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 5935{
717746e3 5936 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 5937 unsigned long value;
5938
5939 switch (cr) {
5940 case 0:
5941 value = kvm_read_cr0(vcpu);
5942 break;
5943 case 2:
5944 value = vcpu->arch.cr2;
5945 break;
5946 case 3:
9f8fe504 5947 value = kvm_read_cr3(vcpu);
52a46617
GN		 5948 break;
5949 case 4:
5950 value = kvm_read_cr4(vcpu);
5951 break;
5952 case 8:
5953 value = kvm_get_cr8(vcpu);
5954 break;
5955 default:
a737f256 5956 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 5957 return 0;
5958 }
5959
5960 return value;
5961}
5962
717746e3 5963static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 5964{
717746e3 5965 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 5966 int res = 0;
5967
52a46617
GN		 5968 switch (cr) {
5969 case 0:
49a9b07e 5970 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 5971 break;
5972 case 2:
5973 vcpu->arch.cr2 = val;
5974 break;
5975 case 3:
2390218b 5976 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 5977 break;
5978 case 4:
a83b29c6 5979 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5980 break;
5981 case 8:
eea1cff9 5982 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5983 break;
5984 default:
a737f256 5985 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5986 res = -1;
52a46617 5987 }
0f12244f
GN		 5988
5989 return res;
52a46617
GN		 5990}
5991
717746e3 5992static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5993{
717746e3 5994 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5995}
5996
4bff1e86 5997static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5998{
4bff1e86 5999 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 6000}
6001
4bff1e86 6002static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 6003{
4bff1e86 6004 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 6005}
6006
1ac9d0cf
AK		 6007static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6008{
6009 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
6010}
6011
6012static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6013{
6014 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
6015}
6016
4bff1e86
AK		 6017static unsigned long emulator_get_cached_segment_base(
6018 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 6019{
4bff1e86 6020 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 6021}
6022
1aa36616
AK		 6023static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
6024 struct desc_struct *desc, u32 *base3,
6025 int seg)
2dafc6c2
GN		 6026{
6027 struct kvm_segment var;
6028
4bff1e86 6029 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 6030 *selector = var.selector;
2dafc6c2 6031
378a8b09
GN		 6032 if (var.unusable) {
6033 memset(desc, 0, sizeof(*desc));
f0367ee1
RK		 6034 if (base3)
6035 *base3 = 0;
2dafc6c2 6036 return false;
378a8b09 6037 }
2dafc6c2
GN		 6038
6039 if (var.g)
6040 var.limit >>= 12;
6041 set_desc_limit(desc, var.limit);
6042 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 6043#ifdef CONFIG_X86_64
6044 if (base3)
6045 *base3 = var.base >> 32;
6046#endif
2dafc6c2
GN		 6047 desc->type = var.type;
6048 desc->s = var.s;
6049 desc->dpl = var.dpl;
6050 desc->p = var.present;
6051 desc->avl = var.avl;
6052 desc->l = var.l;
6053 desc->d = var.db;
6054 desc->g = var.g;
6055
6056 return true;
6057}
6058
1aa36616
AK		 6059static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
6060 struct desc_struct *desc, u32 base3,
6061 int seg)
2dafc6c2 6062{
4bff1e86 6063 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 6064 struct kvm_segment var;
6065
1aa36616 6066 var.selector = selector;
2dafc6c2 6067 var.base = get_desc_base(desc);
5601d05b
GN		 6068#ifdef CONFIG_X86_64
6069 var.base |= ((u64)base3) << 32;
6070#endif
2dafc6c2
GN		 6071 var.limit = get_desc_limit(desc);
6072 if (desc->g)
6073 var.limit = (var.limit << 12) | 0xfff;
6074 var.type = desc->type;
2dafc6c2
GN		 6075 var.dpl = desc->dpl;
6076 var.db = desc->d;
6077 var.s = desc->s;
6078 var.l = desc->l;
6079 var.g = desc->g;
6080 var.avl = desc->avl;
6081 var.present = desc->p;
6082 var.unusable = !var.present;
6083 var.padding = 0;
6084
6085 kvm_set_segment(vcpu, &var, seg);
6086 return;
6087}
6088
717746e3
AK		 6089static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
6090 u32 msr_index, u64 *pdata)
6091{
f20935d8 6092 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
717746e3
AK		 6093}
6094
6095static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
6096 u32 msr_index, u64 data)
6097{
f20935d8 6098 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
717746e3
AK		 6099}
6100
64d60670
PB		 6101static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
6102{
6103 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6104
6105 return vcpu->arch.smbase;
6106}
6107
6108static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
6109{
6110 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6111
6112 vcpu->arch.smbase = smbase;
6113}
6114
67f4d428
NA		 6115static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
6116 u32 pmc)
6117{
c6702c9d 6118 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 6119}
6120
222d21aa
AK		 6121static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
6122 u32 pmc, u64 *pdata)
6123{
c6702c9d 6124 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 6125}
6126
6c3287f7
AK		 6127static void emulator_halt(struct x86_emulate_ctxt *ctxt)
6128{
6129 emul_to_vcpu(ctxt)->arch.halt_request = 1;
6130}
6131
2953538e 6132static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 6133 struct x86_instruction_info *info,
c4f035c6
AK		 6134 enum x86_intercept_stage stage)
6135{
2953538e 6136 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 6137}
6138
e911eb3b
YZ		 6139static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
6140 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
bdb42f5a 6141{
e911eb3b 6142 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
bdb42f5a
SB		 6143}
6144
dd856efa
AK		 6145static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
6146{
6147 return kvm_register_read(emul_to_vcpu(ctxt), reg);
6148}
6149
6150static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
6151{
6152 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
6153}
6154
801806d9
NA		 6155static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
6156{
6157 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
6158}
6159
6ed071f0
LP		 6160static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
6161{
6162 return emul_to_vcpu(ctxt)->arch.hflags;
6163}
6164
6165static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
6166{
c5833c7a 6167 emul_to_vcpu(ctxt)->arch.hflags = emul_flags;
6ed071f0
LP		 6168}
6169
ed19321f
SC		 6170static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt,
6171 const char *smstate)
0234bf88 6172{
ed19321f 6173 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smstate);
0234bf88
LP		 6174}
6175
c5833c7a
SC		 6176static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt)
6177{
6178 kvm_smm_changed(emul_to_vcpu(ctxt));
6179}
6180
02d4160f
VK		 6181static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr)
6182{
6183 return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr);
6184}
6185
0225fb50 6186static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 6187 .read_gpr = emulator_read_gpr,
6188 .write_gpr = emulator_write_gpr,
ce14e868
PB		 6189 .read_std = emulator_read_std,
6190 .write_std = emulator_write_std,
7a036a6f 6191 .read_phys = kvm_read_guest_phys_system,
1871c602 6192 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 6193 .read_emulated = emulator_read_emulated,
6194 .write_emulated = emulator_write_emulated,
6195 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 6196 .invlpg = emulator_invlpg,
cf8f70bf
GN		 6197 .pio_in_emulated = emulator_pio_in_emulated,
6198 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 6199 .get_segment = emulator_get_segment,
6200 .set_segment = emulator_set_segment,
5951c442 6201 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 6202 .get_gdt = emulator_get_gdt,
160ce1f1 6203 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 6204 .set_gdt = emulator_set_gdt,
6205 .set_idt = emulator_set_idt,
52a46617
GN		 6206 .get_cr = emulator_get_cr,
6207 .set_cr = emulator_set_cr,
9c537244 6208 .cpl = emulator_get_cpl,
35aa5375
GN		 6209 .get_dr = emulator_get_dr,
6210 .set_dr = emulator_set_dr,
64d60670
PB		 6211 .get_smbase = emulator_get_smbase,
6212 .set_smbase = emulator_set_smbase,
717746e3
AK		 6213 .set_msr = emulator_set_msr,
6214 .get_msr = emulator_get_msr,
67f4d428 6215 .check_pmc = emulator_check_pmc,
222d21aa 6216 .read_pmc = emulator_read_pmc,
6c3287f7 6217 .halt = emulator_halt,
bcaf5cc5 6218 .wbinvd = emulator_wbinvd,
d6aa1000 6219 .fix_hypercall = emulator_fix_hypercall,
c4f035c6 6220 .intercept = emulator_intercept,
bdb42f5a 6221 .get_cpuid = emulator_get_cpuid,
801806d9 6222 .set_nmi_mask = emulator_set_nmi_mask,
6ed071f0
LP		 6223 .get_hflags = emulator_get_hflags,
6224 .set_hflags = emulator_set_hflags,
0234bf88 6225 .pre_leave_smm = emulator_pre_leave_smm,
c5833c7a 6226 .post_leave_smm = emulator_post_leave_smm,
02d4160f 6227 .set_xcr = emulator_set_xcr,
bbd9b64e
CO		 6228};
6229
95cb2295
GN		 6230static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
6231{
37ccdcbe 6232 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 6233 /*
6234 * an sti; sti; sequence only disable interrupts for the first
6235 * instruction. So, if the last instruction, be it emulated or
6236 * not, left the system with the INT_STI flag enabled, it
6237 * means that the last instruction is an sti. We should not
6238 * leave the flag on in this case. The same goes for mov ss
6239 */
37ccdcbe
PB		 6240 if (int_shadow & mask)
6241 mask = 0;
6addfc42 6242 if (unlikely(int_shadow || mask)) {
95cb2295 6243 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 6244 if (!mask)
6245 kvm_make_request(KVM_REQ_EVENT, vcpu);
6246 }
95cb2295
GN		 6247}
6248
ef54bcfe 6249static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 6250{
6251 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 6252 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 6253 return kvm_propagate_fault(vcpu, &ctxt->exception);
6254
6255 if (ctxt->exception.error_code_valid)
da9cb575
AK		 6256 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
6257 ctxt->exception.error_code);
54b8486f 6258 else
da9cb575 6259 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 6260 return false;
54b8486f
GN		 6261}
6262
8ec4722d
MG		 6263static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
6264{
adf52235 6265 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 6266 int cs_db, cs_l;
6267
8ec4722d
MG		 6268 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
6269
adf52235 6270 ctxt->eflags = kvm_get_rflags(vcpu);
c8401dda
PB		 6271 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
6272
adf52235
TY		 6273 ctxt->eip = kvm_rip_read(vcpu);
6274 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
6275 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 6276 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 6277 cs_db ? X86EMUL_MODE_PROT32 :
6278 X86EMUL_MODE_PROT16;
a584539b 6279 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 6280 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
6281 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
adf52235 6282
dd856efa 6283 init_decode_cache(ctxt);
7ae441ea 6284 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 6285}
6286
9497e1f2 6287void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 6288{
9d74191a 6289 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 6290 int ret;
6291
6292 init_emulate_ctxt(vcpu);
6293
9dac77fa
AK		 6294 ctxt->op_bytes = 2;
6295 ctxt->ad_bytes = 2;
6296 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 6297 ret = emulate_int_real(ctxt, irq);
63995653 6298
9497e1f2
SC		 6299 if (ret != X86EMUL_CONTINUE) {
6300 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6301 } else {
6302 ctxt->eip = ctxt->_eip;
6303 kvm_rip_write(vcpu, ctxt->eip);
6304 kvm_set_rflags(vcpu, ctxt->eflags);
6305 }
63995653
MG		 6306}
6307EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
6308
e2366171 6309static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6d77dbfc 6310{
6d77dbfc
GN		 6311 ++vcpu->stat.insn_emulation_fail;
6312 trace_kvm_emulate_insn_failed(vcpu);
e2366171 6313
42cbf068
SC		 6314 if (emulation_type & EMULTYPE_VMWARE_GP) {
6315 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
60fc3d02 6316 return 1;
42cbf068 6317 }
e2366171 6318
738fece4
SC		 6319 if (emulation_type & EMULTYPE_SKIP) {
6320 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6321 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6322 vcpu->run->internal.ndata = 0;
60fc3d02 6323 return 0;
738fece4
SC		 6324 }
6325
22da61c9
SC		 6326 kvm_queue_exception(vcpu, UD_VECTOR);
6327
a2b9e6c1 6328 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 6329 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6330 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6331 vcpu->run->internal.ndata = 0;
60fc3d02 6332 return 0;
fc3a9157 6333 }
e2366171 6334
60fc3d02 6335 return 1;
6d77dbfc
GN		 6336}
6337
93c05d3e 6338static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 6339 bool write_fault_to_shadow_pgtable,
6340 int emulation_type)
a6f177ef 6341{
95b3cf69 6342 gpa_t gpa = cr2;
ba049e93 6343 kvm_pfn_t pfn;
a6f177ef 6344
384bf221 6345 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
991eebf9
GN		 6346 return false;
6347
6c3dfeb6
SC		 6348 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6349 return false;
6350
44dd3ffa 6351 if (!vcpu->arch.mmu->direct_map) {
95b3cf69
XG		 6352 /*
6353 * Write permission should be allowed since only
6354 * write access need to be emulated.
6355 */
6356 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 6357
95b3cf69
XG		 6358 /*
6359 * If the mapping is invalid in guest, let cpu retry
6360 * it to generate fault.
6361 */
6362 if (gpa == UNMAPPED_GVA)
6363 return true;
6364 }
a6f177ef 6365
8e3d9d06
XG		 6366 /*
6367 * Do not retry the unhandleable instruction if it faults on the
6368 * readonly host memory, otherwise it will goto a infinite loop:
6369 * retry instruction -> write #PF -> emulation fail -> retry
6370 * instruction -> ...
6371 */
6372 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 6373
6374 /*
6375 * If the instruction failed on the error pfn, it can not be fixed,
6376 * report the error to userspace.
6377 */
6378 if (is_error_noslot_pfn(pfn))
6379 return false;
6380
6381 kvm_release_pfn_clean(pfn);
6382
6383 /* The instructions are well-emulated on direct mmu. */
44dd3ffa 6384 if (vcpu->arch.mmu->direct_map) {
95b3cf69
XG		 6385 unsigned int indirect_shadow_pages;
6386
6387 spin_lock(&vcpu->kvm->mmu_lock);
6388 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
6389 spin_unlock(&vcpu->kvm->mmu_lock);
6390
6391 if (indirect_shadow_pages)
6392 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6393
a6f177ef 6394 return true;
8e3d9d06 6395 }
a6f177ef 6396
95b3cf69
XG		 6397 /*
6398 * if emulation was due to access to shadowed page table
6399 * and it failed try to unshadow page and re-enter the
6400 * guest to let CPU execute the instruction.
6401 */
6402 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 6403
6404 /*
6405 * If the access faults on its page table, it can not
6406 * be fixed by unprotecting shadow page and it should
6407 * be reported to userspace.
6408 */
6409 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 6410}
6411
1cb3f3ae
XG		 6412static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
6413 unsigned long cr2, int emulation_type)
6414{
6415 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6416 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
6417
6418 last_retry_eip = vcpu->arch.last_retry_eip;
6419 last_retry_addr = vcpu->arch.last_retry_addr;
6420
6421 /*
6422 * If the emulation is caused by #PF and it is non-page_table
6423 * writing instruction, it means the VM-EXIT is caused by shadow
6424 * page protected, we can zap the shadow page and retry this
6425 * instruction directly.
6426 *
6427 * Note: if the guest uses a non-page-table modifying instruction
6428 * on the PDE that points to the instruction, then we will unmap
6429 * the instruction and go to an infinite loop. So, we cache the
6430 * last retried eip and the last fault address, if we meet the eip
6431 * and the address again, we can break out of the potential infinite
6432 * loop.
6433 */
6434 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
6435
384bf221 6436 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
1cb3f3ae
XG		 6437 return false;
6438
6c3dfeb6
SC		 6439 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6440 return false;
6441
1cb3f3ae
XG		 6442 if (x86_page_table_writing_insn(ctxt))
6443 return false;
6444
6445 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
6446 return false;
6447
6448 vcpu->arch.last_retry_eip = ctxt->eip;
6449 vcpu->arch.last_retry_addr = cr2;
6450
44dd3ffa 6451 if (!vcpu->arch.mmu->direct_map)
1cb3f3ae
XG		 6452 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
6453
22368028 6454 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 6455
6456 return true;
6457}
6458
716d51ab
GN		 6459static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
6460static int complete_emulated_pio(struct kvm_vcpu *vcpu);
6461
64d60670 6462static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 6463{
64d60670 6464 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 6465 /* This is a good place to trace that we are exiting SMM. */
6466 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
6467
c43203ca
PB		 6468 /* Process a latched INIT or SMI, if any. */
6469 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 6470 }
699023e2
PB		 6471
6472 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6473}
6474
4a1e10d5
PB		 6475static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
6476 unsigned long *db)
6477{
6478 u32 dr6 = 0;
6479 int i;
6480 u32 enable, rwlen;
6481
6482 enable = dr7;
6483 rwlen = dr7 >> 16;
6484 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
6485 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
6486 dr6 |= (1 << i);
6487 return dr6;
6488}
6489
120c2c4f 6490static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu)
663f4c61
PB		 6491{
6492 struct kvm_run *kvm_run = vcpu->run;
6493
c8401dda
PB		 6494 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6495 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
6496 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
6497 kvm_run->debug.arch.exception = DB_VECTOR;
6498 kvm_run->exit_reason = KVM_EXIT_DEBUG;
60fc3d02 6499 return 0;
663f4c61 6500 }
120c2c4f 6501 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
60fc3d02 6502 return 1;
663f4c61
PB		 6503}
6504
6affcbed
KH		 6505int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
6506{
6507 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
f8ea7c60 6508 int r;
6affcbed 6509
f8ea7c60 6510 r = kvm_x86_ops->skip_emulated_instruction(vcpu);
60fc3d02 6511 if (unlikely(!r))
f8ea7c60 6512 return 0;
c8401dda
PB		 6513
6514 /*
6515 * rflags is the old, "raw" value of the flags. The new value has
6516 * not been saved yet.
6517 *
6518 * This is correct even for TF set by the guest, because "the
6519 * processor will not generate this exception after the instruction
6520 * that sets the TF flag".
6521 */
6522 if (unlikely(rflags & X86_EFLAGS_TF))
120c2c4f 6523 r = kvm_vcpu_do_singlestep(vcpu);
60fc3d02 6524 return r;
6affcbed
KH		 6525}
6526EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
6527
4a1e10d5
PB		 6528static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
6529{
4a1e10d5
PB		 6530 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
6531 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 6532 struct kvm_run *kvm_run = vcpu->run;
6533 unsigned long eip = kvm_get_linear_rip(vcpu);
6534 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 6535 vcpu->arch.guest_debug_dr7,
6536 vcpu->arch.eff_db);
6537
6538 if (dr6 != 0) {
6f43ed01 6539 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 6540 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 6541 kvm_run->debug.arch.exception = DB_VECTOR;
6542 kvm_run->exit_reason = KVM_EXIT_DEBUG;
60fc3d02 6543 *r = 0;
4a1e10d5
PB		 6544 return true;
6545 }
6546 }
6547
4161a569
NA		 6548 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
6549 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 6550 unsigned long eip = kvm_get_linear_rip(vcpu);
6551 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 6552 vcpu->arch.dr7,
6553 vcpu->arch.db);
6554
6555 if (dr6 != 0) {
1fc5d194 6556 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
6f43ed01 6557 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5 6558 kvm_queue_exception(vcpu, DB_VECTOR);
60fc3d02 6559 *r = 1;
4a1e10d5
PB		 6560 return true;
6561 }
6562 }
6563
6564 return false;
6565}
6566
04789b66
LA		 6567static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
6568{
2d7921c4
AM		 6569 switch (ctxt->opcode_len) {
6570 case 1:
6571 switch (ctxt->b) {
6572 case 0xe4: /* IN */
6573 case 0xe5:
6574 case 0xec:
6575 case 0xed:
6576 case 0xe6: /* OUT */
6577 case 0xe7:
6578 case 0xee:
6579 case 0xef:
6580 case 0x6c: /* INS */
6581 case 0x6d:
6582 case 0x6e: /* OUTS */
6583 case 0x6f:
6584 return true;
6585 }
6586 break;
6587 case 2:
6588 switch (ctxt->b) {
6589 case 0x33: /* RDPMC */
6590 return true;
6591 }
6592 break;
04789b66
LA		 6593 }
6594
6595 return false;
6596}
6597
51d8b661
AP		 6598int x86_emulate_instruction(struct kvm_vcpu *vcpu,
6599 unsigned long cr2,
dc25e89e
AP		 6600 int emulation_type,
6601 void *insn,
6602 int insn_len)
bbd9b64e 6603{
95cb2295 6604 int r;
9d74191a 6605 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 6606 bool writeback = true;
93c05d3e 6607 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 6608
c595ceee
PB		 6609 vcpu->arch.l1tf_flush_l1d = true;
6610
93c05d3e
XG		 6611 /*
6612 * Clear write_fault_to_shadow_pgtable here to ensure it is
6613 * never reused.
6614 */
6615 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 6616 kvm_clear_exception_queue(vcpu);
8d7d8102 6617
571008da 6618 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 6619 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 6620
6621 /*
6622 * We will reenter on the same instruction since
6623 * we do not set complete_userspace_io. This does not
6624 * handle watchpoints yet, those would be handled in
6625 * the emulate_ops.
6626 */
d391f120
VK		 6627 if (!(emulation_type & EMULTYPE_SKIP) &&
6628 kvm_vcpu_check_breakpoint(vcpu, &r))
4a1e10d5
PB		 6629 return r;
6630
9d74191a
TY		 6631 ctxt->interruptibility = 0;
6632 ctxt->have_exception = false;
e0ad0b47 6633 ctxt->exception.vector = -1;
9d74191a 6634 ctxt->perm_ok = false;
bbd9b64e 6635
b51e974f 6636 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 6637
9d74191a 6638 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 6639
e46479f8 6640 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 6641 ++vcpu->stat.insn_emulation;
1d2887e2 6642 if (r != EMULATION_OK) {
b4000606 6643 if ((emulation_type & EMULTYPE_TRAP_UD) ||
c83fad65
SC		 6644 (emulation_type & EMULTYPE_TRAP_UD_FORCED)) {
6645 kvm_queue_exception(vcpu, UD_VECTOR);
60fc3d02 6646 return 1;
c83fad65 6647 }
991eebf9
GN		 6648 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6649 emulation_type))
60fc3d02 6650 return 1;
8530a79c 6651 if (ctxt->have_exception) {
c8848cee
JD		 6652 /*
6653 * #UD should result in just EMULATION_FAILED, and trap-like
6654 * exception should not be encountered during decode.
6655 */
6656 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR ||
6657 exception_type(ctxt->exception.vector) == EXCPT_TRAP);
8530a79c 6658 inject_emulated_exception(vcpu);
60fc3d02 6659 return 1;
8530a79c 6660 }
e2366171 6661 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6662 }
6663 }
6664
42cbf068
SC		 6665 if ((emulation_type & EMULTYPE_VMWARE_GP) &&
6666 !is_vmware_backdoor_opcode(ctxt)) {
6667 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
60fc3d02 6668 return 1;
42cbf068 6669 }
04789b66 6670
1957aa63
SC		 6671 /*
6672 * Note, EMULTYPE_SKIP is intended for use *only* by vendor callbacks
6673 * for kvm_skip_emulated_instruction(). The caller is responsible for
6674 * updating interruptibility state and injecting single-step #DBs.
6675 */
ba8afb6b 6676 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 6677 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 6678 if (ctxt->eflags & X86_EFLAGS_RF)
6679 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
60fc3d02 6680 return 1;
ba8afb6b
GN		 6681 }
6682
1cb3f3ae 6683 if (retry_instruction(ctxt, cr2, emulation_type))
60fc3d02 6684 return 1;
1cb3f3ae 6685
7ae441ea 6686 /* this is needed for vmware backdoor interface to work since it
4d2179e1 6687 changes registers values during IO operation */
7ae441ea
GN		 6688 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6689 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 6690 emulator_invalidate_register_cache(ctxt);
7ae441ea 6691 }
4d2179e1 6692
5cd21917 6693restart:
0f89b207
TL		 6694 /* Save the faulting GPA (cr2) in the address field */
6695 ctxt->exception.address = cr2;
6696
9d74191a 6697 r = x86_emulate_insn(ctxt);
bbd9b64e 6698
775fde86 6699 if (r == EMULATION_INTERCEPTED)
60fc3d02 6700 return 1;
775fde86 6701
d2ddd1c4 6702 if (r == EMULATION_FAILED) {
991eebf9
GN		 6703 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6704 emulation_type))
60fc3d02 6705 return 1;
c3cd7ffa 6706
e2366171 6707 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6708 }
6709
9d74191a 6710 if (ctxt->have_exception) {
60fc3d02 6711 r = 1;
ef54bcfe
PB		 6712 if (inject_emulated_exception(vcpu))
6713 return r;
d2ddd1c4 6714 } else if (vcpu->arch.pio.count) {
0912c977
PB		 6715 if (!vcpu->arch.pio.in) {
6716 /* FIXME: return into emulator if single-stepping. */
3457e419 6717 vcpu->arch.pio.count = 0;
0912c977 6718 } else {
7ae441ea 6719 writeback = false;
716d51ab
GN		 6720 vcpu->arch.complete_userspace_io = complete_emulated_pio;
6721 }
60fc3d02 6722 r = 0;
7ae441ea 6723 } else if (vcpu->mmio_needed) {
bc8a0aaf
SC		 6724 ++vcpu->stat.mmio_exits;
6725
7ae441ea
GN		 6726 if (!vcpu->mmio_is_write)
6727 writeback = false;
60fc3d02 6728 r = 0;
716d51ab 6729 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 6730 } else if (r == EMULATION_RESTART)
5cd21917 6731 goto restart;
d2ddd1c4 6732 else
60fc3d02 6733 r = 1;
f850e2e6 6734
7ae441ea 6735 if (writeback) {
6addfc42 6736 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 6737 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 6738 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
38827dbd 6739 if (!ctxt->have_exception ||
75ee23b3
SC		 6740 exception_type(ctxt->exception.vector) == EXCPT_TRAP) {
6741 kvm_rip_write(vcpu, ctxt->eip);
60fc3d02 6742 if (r && ctxt->tf)
120c2c4f 6743 r = kvm_vcpu_do_singlestep(vcpu);
38827dbd 6744 __kvm_set_rflags(vcpu, ctxt->eflags);
75ee23b3 6745 }
6addfc42
PB		 6746
6747 /*
6748 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6749 * do nothing, and it will be requested again as soon as
6750 * the shadow expires. But we still need to check here,
6751 * because POPF has no interrupt shadow.
6752 */
6753 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6754 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 6755 } else
6756 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 6757
6758 return r;
de7d789a 6759}
c60658d1
SC		 6760
6761int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
6762{
6763 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
6764}
6765EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
6766
6767int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
6768 void *insn, int insn_len)
6769{
6770 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
6771}
6772EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
de7d789a 6773
8764ed55
SC		 6774static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu)
6775{
6776 vcpu->arch.pio.count = 0;
6777 return 1;
6778}
6779
45def77e
SC		 6780static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
6781{
6782 vcpu->arch.pio.count = 0;
6783
6784 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
6785 return 1;
6786
6787 return kvm_skip_emulated_instruction(vcpu);
6788}
6789
dca7f128
SC		 6790static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
6791 unsigned short port)
de7d789a 6792{
de3cd117 6793 unsigned long val = kvm_rax_read(vcpu);
ca1d4a9e
AK		 6794 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
6795 size, port, &val, 1);
8764ed55
SC		 6796 if (ret)
6797 return ret;
45def77e 6798
8764ed55
SC		 6799 /*
6800 * Workaround userspace that relies on old KVM behavior of %rip being
6801 * incremented prior to exiting to userspace to handle "OUT 0x7e".
6802 */
6803 if (port == 0x7e &&
6804 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) {
6805 vcpu->arch.complete_userspace_io =
6806 complete_fast_pio_out_port_0x7e;
6807 kvm_skip_emulated_instruction(vcpu);
6808 } else {
45def77e
SC		 6809 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
6810 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
6811 }
8764ed55 6812 return 0;
de7d789a 6813}
de7d789a 6814
8370c3d0
TL		 6815static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6816{
6817 unsigned long val;
6818
6819 /* We should only ever be called with arch.pio.count equal to 1 */
6820 BUG_ON(vcpu->arch.pio.count != 1);
6821
45def77e
SC		 6822 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
6823 vcpu->arch.pio.count = 0;
6824 return 1;
6825 }
6826
8370c3d0 6827 /* For size less than 4 we merge, else we zero extend */
de3cd117 6828 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0;
8370c3d0
TL		 6829
6830 /*
6831 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
6832 * the copy and tracing
6833 */
6834 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
6835 vcpu->arch.pio.port, &val, 1);
de3cd117 6836 kvm_rax_write(vcpu, val);
8370c3d0 6837
45def77e 6838 return kvm_skip_emulated_instruction(vcpu);
8370c3d0
TL		 6839}
6840
dca7f128
SC		 6841static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
6842 unsigned short port)
8370c3d0
TL		 6843{
6844 unsigned long val;
6845 int ret;
6846
6847 /* For size less than 4 we merge, else we zero extend */
de3cd117 6848 val = (size < 4) ? kvm_rax_read(vcpu) : 0;
8370c3d0
TL		 6849
6850 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
6851 &val, 1);
6852 if (ret) {
de3cd117 6853 kvm_rax_write(vcpu, val);
8370c3d0
TL		 6854 return ret;
6855 }
6856
45def77e 6857 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
8370c3d0
TL		 6858 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
6859
6860 return 0;
6861}
dca7f128
SC		 6862
6863int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
6864{
45def77e 6865 int ret;
dca7f128 6866
dca7f128 6867 if (in)
45def77e 6868 ret = kvm_fast_pio_in(vcpu, size, port);
dca7f128 6869 else
45def77e
SC		 6870 ret = kvm_fast_pio_out(vcpu, size, port);
6871 return ret && kvm_skip_emulated_instruction(vcpu);
dca7f128
SC		 6872}
6873EXPORT_SYMBOL_GPL(kvm_fast_pio);
8370c3d0 6874
251a5fd6 6875static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 6876{
0a3aee0d 6877 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 6878 return 0;
8cfdc000
ZA		 6879}
6880
6881static void tsc_khz_changed(void *data)
c8076604 6882{
8cfdc000
ZA		 6883 struct cpufreq_freqs *freq = data;
6884 unsigned long khz = 0;
6885
6886 if (data)
6887 khz = freq->new;
6888 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6889 khz = cpufreq_quick_get(raw_smp_processor_id());
6890 if (!khz)
6891 khz = tsc_khz;
0a3aee0d 6892 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 6893}
6894
5fa4ec9c 6895#ifdef CONFIG_X86_64
0092e434
VK		 6896static void kvm_hyperv_tsc_notifier(void)
6897{
0092e434
VK		 6898 struct kvm *kvm;
6899 struct kvm_vcpu *vcpu;
6900 int cpu;
6901
0d9ce162 6902 mutex_lock(&kvm_lock);
0092e434
VK		 6903 list_for_each_entry(kvm, &vm_list, vm_list)
6904 kvm_make_mclock_inprogress_request(kvm);
6905
6906 hyperv_stop_tsc_emulation();
6907
6908 /* TSC frequency always matches when on Hyper-V */
6909 for_each_present_cpu(cpu)
6910 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
6911 kvm_max_guest_tsc_khz = tsc_khz;
6912
6913 list_for_each_entry(kvm, &vm_list, vm_list) {
6914 struct kvm_arch *ka = &kvm->arch;
6915
6916 spin_lock(&ka->pvclock_gtod_sync_lock);
6917
6918 pvclock_update_vm_gtod_copy(kvm);
6919
6920 kvm_for_each_vcpu(cpu, vcpu, kvm)
6921 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6922
6923 kvm_for_each_vcpu(cpu, vcpu, kvm)
6924 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
6925
6926 spin_unlock(&ka->pvclock_gtod_sync_lock);
6927 }
0d9ce162 6928 mutex_unlock(&kvm_lock);
0092e434 6929}
5fa4ec9c 6930#endif
0092e434 6931
df24014a 6932static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu)
c8076604 6933{
c8076604
GH		 6934 struct kvm *kvm;
6935 struct kvm_vcpu *vcpu;
6936 int i, send_ipi = 0;
6937
8cfdc000
ZA		 6938 /*
6939 * We allow guests to temporarily run on slowing clocks,
6940 * provided we notify them after, or to run on accelerating
6941 * clocks, provided we notify them before. Thus time never
6942 * goes backwards.
6943 *
6944 * However, we have a problem. We can't atomically update
6945 * the frequency of a given CPU from this function; it is
6946 * merely a notifier, which can be called from any CPU.
6947 * Changing the TSC frequency at arbitrary points in time
6948 * requires a recomputation of local variables related to
6949 * the TSC for each VCPU. We must flag these local variables
6950 * to be updated and be sure the update takes place with the
6951 * new frequency before any guests proceed.
6952 *
6953 * Unfortunately, the combination of hotplug CPU and frequency
6954 * change creates an intractable locking scenario; the order
6955 * of when these callouts happen is undefined with respect to
6956 * CPU hotplug, and they can race with each other. As such,
6957 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
6958 * undefined; you can actually have a CPU frequency change take
6959 * place in between the computation of X and the setting of the
6960 * variable. To protect against this problem, all updates of
6961 * the per_cpu tsc_khz variable are done in an interrupt
6962 * protected IPI, and all callers wishing to update the value
6963 * must wait for a synchronous IPI to complete (which is trivial
6964 * if the caller is on the CPU already). This establishes the
6965 * necessary total order on variable updates.
6966 *
6967 * Note that because a guest time update may take place
6968 * anytime after the setting of the VCPU's request bit, the
6969 * correct TSC value must be set before the request. However,
6970 * to ensure the update actually makes it to any guest which
6971 * starts running in hardware virtualization between the set
6972 * and the acquisition of the spinlock, we must also ping the
6973 * CPU after setting the request bit.
6974 *
6975 */
6976
df24014a 6977 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
c8076604 6978
0d9ce162 6979 mutex_lock(&kvm_lock);
c8076604 6980 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 6981 kvm_for_each_vcpu(i, vcpu, kvm) {
df24014a 6982 if (vcpu->cpu != cpu)
c8076604 6983 continue;
c285545f 6984 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0d9ce162 6985 if (vcpu->cpu != raw_smp_processor_id())
8cfdc000 6986 send_ipi = 1;
c8076604
GH		 6987 }
6988 }
0d9ce162 6989 mutex_unlock(&kvm_lock);
c8076604
GH		 6990
6991 if (freq->old < freq->new && send_ipi) {
6992 /*
6993 * We upscale the frequency. Must make the guest
6994 * doesn't see old kvmclock values while running with
6995 * the new frequency, otherwise we risk the guest sees
6996 * time go backwards.
6997 *
6998 * In case we update the frequency for another cpu
6999 * (which might be in guest context) send an interrupt
7000 * to kick the cpu out of guest context. Next time
7001 * guest context is entered kvmclock will be updated,
7002 * so the guest will not see stale values.
7003 */
df24014a 7004 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
c8076604 7005 }
df24014a
VK		 7006}
7007
7008static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
7009 void *data)
7010{
7011 struct cpufreq_freqs *freq = data;
7012 int cpu;
7013
7014 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
7015 return 0;
7016 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
7017 return 0;
7018
7019 for_each_cpu(cpu, freq->policy->cpus)
7020 __kvmclock_cpufreq_notifier(freq, cpu);
7021
c8076604
GH		 7022 return 0;
7023}
7024
7025static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 7026 .notifier_call = kvmclock_cpufreq_notifier
7027};
7028
251a5fd6 7029static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 7030{
251a5fd6
SAS		 7031 tsc_khz_changed(NULL);
7032 return 0;
8cfdc000
ZA		 7033}
7034
b820cc0c
ZA		 7035static void kvm_timer_init(void)
7036{
c285545f 7037 max_tsc_khz = tsc_khz;
460dd42e 7038
b820cc0c 7039 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 7040#ifdef CONFIG_CPU_FREQ
7041 struct cpufreq_policy policy;
758f588d
BP		 7042 int cpu;
7043
c285545f 7044 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 7045 cpu = get_cpu();
7046 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 7047 if (policy.cpuinfo.max_freq)
7048 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 7049 put_cpu();
c285545f 7050#endif
b820cc0c
ZA		 7051 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
7052 CPUFREQ_TRANSITION_NOTIFIER);
7053 }
460dd42e 7054
73c1b41e 7055 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 7056 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 7057}
7058
dd60d217
AK		 7059DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
7060EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
ff9d07a0 7061
f5132b01 7062int kvm_is_in_guest(void)
ff9d07a0 7063{
086c9855 7064 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 7065}
7066
7067static int kvm_is_user_mode(void)
7068{
7069 int user_mode = 3;
dcf46b94 7070
086c9855
AS		 7071 if (__this_cpu_read(current_vcpu))
7072 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 7073
ff9d07a0
ZY		 7074 return user_mode != 0;
7075}
7076
7077static unsigned long kvm_get_guest_ip(void)
7078{
7079 unsigned long ip = 0;
dcf46b94 7080
086c9855
AS		 7081 if (__this_cpu_read(current_vcpu))
7082 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 7083
ff9d07a0
ZY		 7084 return ip;
7085}
7086
8479e04e
LK		 7087static void kvm_handle_intel_pt_intr(void)
7088{
7089 struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu);
7090
7091 kvm_make_request(KVM_REQ_PMI, vcpu);
7092 __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT,
7093 (unsigned long *)&vcpu->arch.pmu.global_status);
7094}
7095
ff9d07a0
ZY		 7096static struct perf_guest_info_callbacks kvm_guest_cbs = {
7097 .is_in_guest = kvm_is_in_guest,
7098 .is_user_mode = kvm_is_user_mode,
7099 .get_guest_ip = kvm_get_guest_ip,
8479e04e 7100 .handle_intel_pt_intr = kvm_handle_intel_pt_intr,
ff9d07a0
ZY		 7101};
7102
16e8d74d
MT		 7103#ifdef CONFIG_X86_64
7104static void pvclock_gtod_update_fn(struct work_struct *work)
7105{
d828199e
MT		 7106 struct kvm *kvm;
7107
7108 struct kvm_vcpu *vcpu;
7109 int i;
7110
0d9ce162 7111 mutex_lock(&kvm_lock);
d828199e
MT		 7112 list_for_each_entry(kvm, &vm_list, vm_list)
7113 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 7114 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 7115 atomic_set(&kvm_guest_has_master_clock, 0);
0d9ce162 7116 mutex_unlock(&kvm_lock);
16e8d74d
MT		 7117}
7118
7119static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
7120
7121/*
7122 * Notification about pvclock gtod data update.
7123 */
7124static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
7125 void *priv)
7126{
7127 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
7128 struct timekeeper *tk = priv;
7129
7130 update_pvclock_gtod(tk);
7131
7132 /* disable master clock if host does not trust, or does not
b0c39dc6 7133 * use, TSC based clocksource.
16e8d74d 7134 */
b0c39dc6 7135 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
16e8d74d
MT		 7136 atomic_read(&kvm_guest_has_master_clock) != 0)
7137 queue_work(system_long_wq, &pvclock_gtod_work);
7138
7139 return 0;
7140}
7141
7142static struct notifier_block pvclock_gtod_notifier = {
7143 .notifier_call = pvclock_gtod_notify,
7144};
7145#endif
7146
f8c16bba 7147int kvm_arch_init(void *opaque)
043405e1 7148{
b820cc0c 7149 int r;
6b61edf7 7150 struct kvm_x86_ops *ops = opaque;
f8c16bba 7151
f8c16bba
ZX		 7152 if (kvm_x86_ops) {
7153 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 7154 r = -EEXIST;
7155 goto out;
f8c16bba
ZX		 7156 }
7157
7158 if (!ops->cpu_has_kvm_support()) {
7159 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 7160 r = -EOPNOTSUPP;
7161 goto out;
f8c16bba
ZX		 7162 }
7163 if (ops->disabled_by_bios()) {
7164 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 7165 r = -EOPNOTSUPP;
7166 goto out;
f8c16bba
ZX		 7167 }
7168
b666a4b6
MO		 7169 /*
7170 * KVM explicitly assumes that the guest has an FPU and
7171 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
7172 * vCPU's FPU state as a fxregs_state struct.
7173 */
7174 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
7175 printk(KERN_ERR "kvm: inadequate fpu\n");
7176 r = -EOPNOTSUPP;
7177 goto out;
7178 }
7179
013f6a5d 7180 r = -ENOMEM;
ed8e4812 7181 x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu),
b666a4b6
MO		 7182 __alignof__(struct fpu), SLAB_ACCOUNT,
7183 NULL);
7184 if (!x86_fpu_cache) {
7185 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n");
7186 goto out;
7187 }
7188
013f6a5d
MT		 7189 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
7190 if (!shared_msrs) {
7191 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
b666a4b6 7192 goto out_free_x86_fpu_cache;
013f6a5d
MT		 7193 }
7194
97db56ce
AK		 7195 r = kvm_mmu_module_init();
7196 if (r)
013f6a5d 7197 goto out_free_percpu;
97db56ce 7198
f8c16bba 7199 kvm_x86_ops = ops;
920c8377 7200
7b52345e 7201 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 7202 PT_DIRTY_MASK, PT64_NX_MASK, 0,
d0ec49d4 7203 PT_PRESENT_MASK, 0, sme_me_mask);
b820cc0c 7204 kvm_timer_init();
c8076604 7205
ff9d07a0
ZY		 7206 perf_register_guest_info_callbacks(&kvm_guest_cbs);
7207
d366bf7e 7208 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 7209 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
7210
c5cc421b 7211 kvm_lapic_init();
0c5f81da
WL		 7212 if (pi_inject_timer == -1)
7213 pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER);
16e8d74d
MT		 7214#ifdef CONFIG_X86_64
7215 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
0092e434 7216
5fa4ec9c 7217 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434 7218 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
16e8d74d
MT		 7219#endif
7220
f8c16bba 7221 return 0;
56c6d28a 7222
013f6a5d
MT		 7223out_free_percpu:
7224 free_percpu(shared_msrs);
b666a4b6
MO		 7225out_free_x86_fpu_cache:
7226 kmem_cache_destroy(x86_fpu_cache);
56c6d28a 7227out:
56c6d28a 7228 return r;
043405e1 7229}
8776e519 7230
f8c16bba
ZX		 7231void kvm_arch_exit(void)
7232{
0092e434 7233#ifdef CONFIG_X86_64
5fa4ec9c 7234 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434
VK		 7235 clear_hv_tscchange_cb();
7236#endif
cef84c30 7237 kvm_lapic_exit();
ff9d07a0
ZY		 7238 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
7239
888d256e
JK		 7240 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7241 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
7242 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 7243 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 7244#ifdef CONFIG_X86_64
7245 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
7246#endif
f8c16bba 7247 kvm_x86_ops = NULL;
56c6d28a 7248 kvm_mmu_module_exit();
013f6a5d 7249 free_percpu(shared_msrs);
b666a4b6 7250 kmem_cache_destroy(x86_fpu_cache);
56c6d28a 7251}
f8c16bba 7252
5cb56059 7253int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 7254{
7255 ++vcpu->stat.halt_exits;
35754c98 7256 if (lapic_in_kernel(vcpu)) {
a4535290 7257 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 7258 return 1;
7259 } else {
7260 vcpu->run->exit_reason = KVM_EXIT_HLT;
7261 return 0;
7262 }
7263}
5cb56059
JS		 7264EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
7265
7266int kvm_emulate_halt(struct kvm_vcpu *vcpu)
7267{
6affcbed
KH		 7268 int ret = kvm_skip_emulated_instruction(vcpu);
7269 /*
7270 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
7271 * KVM_EXIT_DEBUG here.
7272 */
7273 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 7274}
8776e519
HB		 7275EXPORT_SYMBOL_GPL(kvm_emulate_halt);
7276
8ef81a9a 7277#ifdef CONFIG_X86_64
55dd00a7
MT		 7278static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
7279 unsigned long clock_type)
7280{
7281 struct kvm_clock_pairing clock_pairing;
899a31f5 7282 struct timespec64 ts;
80fbd89c 7283 u64 cycle;
55dd00a7
MT		 7284 int ret;
7285
7286 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
7287 return -KVM_EOPNOTSUPP;
7288
7289 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
7290 return -KVM_EOPNOTSUPP;
7291
7292 clock_pairing.sec = ts.tv_sec;
7293 clock_pairing.nsec = ts.tv_nsec;
7294 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
7295 clock_pairing.flags = 0;
bcbfbd8e 7296 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
55dd00a7
MT		 7297
7298 ret = 0;
7299 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
7300 sizeof(struct kvm_clock_pairing)))
7301 ret = -KVM_EFAULT;
7302
7303 return ret;
7304}
8ef81a9a 7305#endif
55dd00a7 7306
6aef266c
SV		 7307/*
7308 * kvm_pv_kick_cpu_op: Kick a vcpu.
7309 *
7310 * @apicid - apicid of vcpu to be kicked.
7311 */
7312static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
7313{
24d2166b 7314 struct kvm_lapic_irq lapic_irq;
6aef266c 7315
24d2166b
R		 7316 lapic_irq.shorthand = 0;
7317 lapic_irq.dest_mode = 0;
ebd28fcb 7318 lapic_irq.level = 0;
24d2166b 7319 lapic_irq.dest_id = apicid;
93bbf0b8 7320 lapic_irq.msi_redir_hint = false;
6aef266c 7321
24d2166b 7322 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 7323 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 7324}
7325
d62caabb
AS		 7326void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
7327{
f7589cca
PB		 7328 if (!lapic_in_kernel(vcpu)) {
7329 WARN_ON_ONCE(vcpu->arch.apicv_active);
7330 return;
7331 }
7332 if (!vcpu->arch.apicv_active)
7333 return;
7334
d62caabb
AS		 7335 vcpu->arch.apicv_active = false;
7336 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
7337}
7338
71506297
WL		 7339static void kvm_sched_yield(struct kvm *kvm, unsigned long dest_id)
7340{
7341 struct kvm_vcpu *target = NULL;
7342 struct kvm_apic_map *map;
7343
7344 rcu_read_lock();
7345 map = rcu_dereference(kvm->arch.apic_map);
7346
7347 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id])
7348 target = map->phys_map[dest_id]->vcpu;
7349
7350 rcu_read_unlock();
7351
266e85a5 7352 if (target && READ_ONCE(target->ready))
71506297
WL		 7353 kvm_vcpu_yield_to(target);
7354}
7355
8776e519
HB		 7356int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
7357{
7358 unsigned long nr, a0, a1, a2, a3, ret;
6356ee0c 7359 int op_64_bit;
8776e519 7360
696ca779
RK		 7361 if (kvm_hv_hypercall_enabled(vcpu->kvm))
7362 return kvm_hv_hypercall(vcpu);
55cd8e5a 7363
de3cd117
SC		 7364 nr = kvm_rax_read(vcpu);
7365 a0 = kvm_rbx_read(vcpu);
7366 a1 = kvm_rcx_read(vcpu);
7367 a2 = kvm_rdx_read(vcpu);
7368 a3 = kvm_rsi_read(vcpu);
8776e519 7369
229456fc 7370 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 7371
a449c7aa
NA		 7372 op_64_bit = is_64_bit_mode(vcpu);
7373 if (!op_64_bit) {
8776e519
HB		 7374 nr &= 0xFFFFFFFF;
7375 a0 &= 0xFFFFFFFF;
7376 a1 &= 0xFFFFFFFF;
7377 a2 &= 0xFFFFFFFF;
7378 a3 &= 0xFFFFFFFF;
7379 }
7380
07708c4a
JK		 7381 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
7382 ret = -KVM_EPERM;
696ca779 7383 goto out;
07708c4a
JK		 7384 }
7385
8776e519 7386 switch (nr) {
b93463aa
AK		 7387 case KVM_HC_VAPIC_POLL_IRQ:
7388 ret = 0;
7389 break;
6aef266c
SV		 7390 case KVM_HC_KICK_CPU:
7391 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
266e85a5 7392 kvm_sched_yield(vcpu->kvm, a1);
6aef266c
SV		 7393 ret = 0;
7394 break;
8ef81a9a 7395#ifdef CONFIG_X86_64
55dd00a7
MT		 7396 case KVM_HC_CLOCK_PAIRING:
7397 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
7398 break;
1ed199a4 7399#endif
4180bf1b
WL		 7400 case KVM_HC_SEND_IPI:
7401 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
7402 break;
71506297
WL		 7403 case KVM_HC_SCHED_YIELD:
7404 kvm_sched_yield(vcpu->kvm, a0);
7405 ret = 0;
7406 break;
8776e519
HB		 7407 default:
7408 ret = -KVM_ENOSYS;
7409 break;
7410 }
696ca779 7411out:
a449c7aa
NA		 7412 if (!op_64_bit)
7413 ret = (u32)ret;
de3cd117 7414 kvm_rax_write(vcpu, ret);
6356ee0c 7415
f11c3a8d 7416 ++vcpu->stat.hypercalls;
6356ee0c 7417 return kvm_skip_emulated_instruction(vcpu);
8776e519
HB		 7418}
7419EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
7420
b6785def 7421static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 7422{
d6aa1000 7423 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 7424 char instruction[3];
5fdbf976 7425 unsigned long rip = kvm_rip_read(vcpu);
8776e519 7426
8776e519 7427 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 7428
ce2e852e
DV		 7429 return emulator_write_emulated(ctxt, rip, instruction, 3,
7430 &ctxt->exception);
8776e519
HB		 7431}
7432
851ba692 7433static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 7434{
782d422b
MG		 7435 return vcpu->run->request_interrupt_window &&
7436 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 7437}
7438
851ba692 7439static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 7440{
851ba692
AK		 7441 struct kvm_run *kvm_run = vcpu->run;
7442
91586a3b 7443 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 7444 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 7445 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 7446 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 7447 kvm_run->ready_for_interrupt_injection =
7448 pic_in_kernel(vcpu->kvm) ||
782d422b 7449 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 7450}
7451
95ba8273
GN		 7452static void update_cr8_intercept(struct kvm_vcpu *vcpu)
7453{
7454 int max_irr, tpr;
7455
7456 if (!kvm_x86_ops->update_cr8_intercept)
7457 return;
7458
bce87cce 7459 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 7460 return;
7461
d62caabb
AS		 7462 if (vcpu->arch.apicv_active)
7463 return;
7464
8db3baa2
GN		 7465 if (!vcpu->arch.apic->vapic_addr)
7466 max_irr = kvm_lapic_find_highest_irr(vcpu);
7467 else
7468 max_irr = -1;
95ba8273
GN		 7469
7470 if (max_irr != -1)
7471 max_irr >>= 4;
7472
7473 tpr = kvm_lapic_get_cr8(vcpu);
7474
7475 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
7476}
7477
b6b8a145 7478static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 7479{
b6b8a145
JK		 7480 int r;
7481
95ba8273 7482 /* try to reinject previous events if any */
664f8e26 7483
1a680e35
LA		 7484 if (vcpu->arch.exception.injected)
7485 kvm_x86_ops->queue_exception(vcpu);
664f8e26 7486 /*
a042c26f
LA		 7487 * Do not inject an NMI or interrupt if there is a pending
7488 * exception. Exceptions and interrupts are recognized at
7489 * instruction boundaries, i.e. the start of an instruction.
7490 * Trap-like exceptions, e.g. #DB, have higher priority than
7491 * NMIs and interrupts, i.e. traps are recognized before an
7492 * NMI/interrupt that's pending on the same instruction.
7493 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
7494 * priority, but are only generated (pended) during instruction
7495 * execution, i.e. a pending fault-like exception means the
7496 * fault occurred on the *previous* instruction and must be
7497 * serviced prior to recognizing any new events in order to
7498 * fully complete the previous instruction.
664f8e26 7499 */
1a680e35
LA		 7500 else if (!vcpu->arch.exception.pending) {
7501 if (vcpu->arch.nmi_injected)
664f8e26 7502 kvm_x86_ops->set_nmi(vcpu);
1a680e35 7503 else if (vcpu->arch.interrupt.injected)
664f8e26 7504 kvm_x86_ops->set_irq(vcpu);
664f8e26
WL		 7505 }
7506
1a680e35
LA		 7507 /*
7508 * Call check_nested_events() even if we reinjected a previous event
7509 * in order for caller to determine if it should require immediate-exit
7510 * from L2 to L1 due to pending L1 events which require exit
7511 * from L2 to L1.
7512 */
664f8e26
WL		 7513 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7514 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7515 if (r != 0)
7516 return r;
7517 }
7518
7519 /* try to inject new event if pending */
b59bb7bd 7520 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 7521 trace_kvm_inj_exception(vcpu->arch.exception.nr,
7522 vcpu->arch.exception.has_error_code,
7523 vcpu->arch.exception.error_code);
d6e8c854 7524
1a680e35 7525 WARN_ON_ONCE(vcpu->arch.exception.injected);
664f8e26
WL		 7526 vcpu->arch.exception.pending = false;
7527 vcpu->arch.exception.injected = true;
7528
d6e8c854
NA		 7529 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
7530 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
7531 X86_EFLAGS_RF);
7532
f10c729f
JM		 7533 if (vcpu->arch.exception.nr == DB_VECTOR) {
7534 /*
7535 * This code assumes that nSVM doesn't use
7536 * check_nested_events(). If it does, the
7537 * DR6/DR7 changes should happen before L1
7538 * gets a #VMEXIT for an intercepted #DB in
7539 * L2. (Under VMX, on the other hand, the
7540 * DR6/DR7 changes should not happen in the
7541 * event of a VM-exit to L1 for an intercepted
7542 * #DB in L2.)
7543 */
7544 kvm_deliver_exception_payload(vcpu);
7545 if (vcpu->arch.dr7 & DR7_GD) {
7546 vcpu->arch.dr7 &= ~DR7_GD;
7547 kvm_update_dr7(vcpu);
7548 }
6bdf0662
NA		 7549 }
7550
cfcd20e5 7551 kvm_x86_ops->queue_exception(vcpu);
1a680e35
LA		 7552 }
7553
7554 /* Don't consider new event if we re-injected an event */
7555 if (kvm_event_needs_reinjection(vcpu))
7556 return 0;
7557
7558 if (vcpu->arch.smi_pending && !is_smm(vcpu) &&
7559 kvm_x86_ops->smi_allowed(vcpu)) {
c43203ca 7560 vcpu->arch.smi_pending = false;
52797bf9 7561 ++vcpu->arch.smi_count;
ee2cd4b7 7562 enter_smm(vcpu);
c43203ca 7563 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 7564 --vcpu->arch.nmi_pending;
7565 vcpu->arch.nmi_injected = true;
7566 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 7567 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 7568 /*
7569 * Because interrupts can be injected asynchronously, we are
7570 * calling check_nested_events again here to avoid a race condition.
7571 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
7572 * proposal and current concerns. Perhaps we should be setting
7573 * KVM_REQ_EVENT only on certain events and not unconditionally?
7574 */
7575 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7576 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7577 if (r != 0)
7578 return r;
7579 }
95ba8273 7580 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 7581 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
7582 false);
7583 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 7584 }
7585 }
ee2cd4b7 7586
b6b8a145 7587 return 0;
95ba8273
GN		 7588}
7589
7460fb4a
AK		 7590static void process_nmi(struct kvm_vcpu *vcpu)
7591{
7592 unsigned limit = 2;
7593
7594 /*
7595 * x86 is limited to one NMI running, and one NMI pending after it.
7596 * If an NMI is already in progress, limit further NMIs to just one.
7597 * Otherwise, allow two (and we'll inject the first one immediately).
7598 */
7599 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
7600 limit = 1;
7601
7602 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
7603 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
7604 kvm_make_request(KVM_REQ_EVENT, vcpu);
7605}
7606
ee2cd4b7 7607static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 7608{
7609 u32 flags = 0;
7610 flags |= seg->g << 23;
7611 flags |= seg->db << 22;
7612 flags |= seg->l << 21;
7613 flags |= seg->avl << 20;
7614 flags |= seg->present << 15;
7615 flags |= seg->dpl << 13;
7616 flags |= seg->s << 12;
7617 flags |= seg->type << 8;
7618 return flags;
7619}
7620
ee2cd4b7 7621static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 7622{
7623 struct kvm_segment seg;
7624 int offset;
7625
7626 kvm_get_segment(vcpu, &seg, n);
7627 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
7628
7629 if (n < 3)
7630 offset = 0x7f84 + n * 12;
7631 else
7632 offset = 0x7f2c + (n - 3) * 12;
7633
7634 put_smstate(u32, buf, offset + 8, seg.base);
7635 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 7636 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7637}
7638
efbb288a 7639#ifdef CONFIG_X86_64
ee2cd4b7 7640static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 7641{
7642 struct kvm_segment seg;
7643 int offset;
7644 u16 flags;
7645
7646 kvm_get_segment(vcpu, &seg, n);
7647 offset = 0x7e00 + n * 16;
7648
ee2cd4b7 7649 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 7650 put_smstate(u16, buf, offset, seg.selector);
7651 put_smstate(u16, buf, offset + 2, flags);
7652 put_smstate(u32, buf, offset + 4, seg.limit);
7653 put_smstate(u64, buf, offset + 8, seg.base);
7654}
efbb288a 7655#endif
660a5d51 7656
ee2cd4b7 7657static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 7658{
7659 struct desc_ptr dt;
7660 struct kvm_segment seg;
7661 unsigned long val;
7662 int i;
7663
7664 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
7665 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
7666 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
7667 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
7668
7669 for (i = 0; i < 8; i++)
7670 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
7671
7672 kvm_get_dr(vcpu, 6, &val);
7673 put_smstate(u32, buf, 0x7fcc, (u32)val);
7674 kvm_get_dr(vcpu, 7, &val);
7675 put_smstate(u32, buf, 0x7fc8, (u32)val);
7676
7677 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7678 put_smstate(u32, buf, 0x7fc4, seg.selector);
7679 put_smstate(u32, buf, 0x7f64, seg.base);
7680 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 7681 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7682
7683 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7684 put_smstate(u32, buf, 0x7fc0, seg.selector);
7685 put_smstate(u32, buf, 0x7f80, seg.base);
7686 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 7687 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7688
7689 kvm_x86_ops->get_gdt(vcpu, &dt);
7690 put_smstate(u32, buf, 0x7f74, dt.address);
7691 put_smstate(u32, buf, 0x7f70, dt.size);
7692
7693 kvm_x86_ops->get_idt(vcpu, &dt);
7694 put_smstate(u32, buf, 0x7f58, dt.address);
7695 put_smstate(u32, buf, 0x7f54, dt.size);
7696
7697 for (i = 0; i < 6; i++)
ee2cd4b7 7698 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 7699
7700 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
7701
7702 /* revision id */
7703 put_smstate(u32, buf, 0x7efc, 0x00020000);
7704 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
7705}
7706
b68f3cc7 7707#ifdef CONFIG_X86_64
ee2cd4b7 7708static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51 7709{
660a5d51
PB		 7710 struct desc_ptr dt;
7711 struct kvm_segment seg;
7712 unsigned long val;
7713 int i;
7714
7715 for (i = 0; i < 16; i++)
7716 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
7717
7718 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
7719 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
7720
7721 kvm_get_dr(vcpu, 6, &val);
7722 put_smstate(u64, buf, 0x7f68, val);
7723 kvm_get_dr(vcpu, 7, &val);
7724 put_smstate(u64, buf, 0x7f60, val);
7725
7726 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
7727 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
7728 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
7729
7730 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
7731
7732 /* revision id */
7733 put_smstate(u32, buf, 0x7efc, 0x00020064);
7734
7735 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
7736
7737 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7738 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 7739 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7740 put_smstate(u32, buf, 0x7e94, seg.limit);
7741 put_smstate(u64, buf, 0x7e98, seg.base);
7742
7743 kvm_x86_ops->get_idt(vcpu, &dt);
7744 put_smstate(u32, buf, 0x7e84, dt.size);
7745 put_smstate(u64, buf, 0x7e88, dt.address);
7746
7747 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7748 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 7749 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7750 put_smstate(u32, buf, 0x7e74, seg.limit);
7751 put_smstate(u64, buf, 0x7e78, seg.base);
7752
7753 kvm_x86_ops->get_gdt(vcpu, &dt);
7754 put_smstate(u32, buf, 0x7e64, dt.size);
7755 put_smstate(u64, buf, 0x7e68, dt.address);
7756
7757 for (i = 0; i < 6; i++)
ee2cd4b7 7758 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51 7759}
b68f3cc7 7760#endif
660a5d51 7761
ee2cd4b7 7762static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 7763{
660a5d51 7764 struct kvm_segment cs, ds;
18c3626e 7765 struct desc_ptr dt;
660a5d51
PB		 7766 char buf[512];
7767 u32 cr0;
7768
660a5d51 7769 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
660a5d51 7770 memset(buf, 0, 512);
b68f3cc7 7771#ifdef CONFIG_X86_64
d6321d49 7772 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
ee2cd4b7 7773 enter_smm_save_state_64(vcpu, buf);
660a5d51 7774 else
b68f3cc7 7775#endif
ee2cd4b7 7776 enter_smm_save_state_32(vcpu, buf);
660a5d51 7777
0234bf88
LP		 7778 /*
7779 * Give pre_enter_smm() a chance to make ISA-specific changes to the
7780 * vCPU state (e.g. leave guest mode) after we've saved the state into
7781 * the SMM state-save area.
7782 */
7783 kvm_x86_ops->pre_enter_smm(vcpu, buf);
7784
7785 vcpu->arch.hflags |= HF_SMM_MASK;
54bf36aa 7786 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 7787
7788 if (kvm_x86_ops->get_nmi_mask(vcpu))
7789 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
7790 else
7791 kvm_x86_ops->set_nmi_mask(vcpu, true);
7792
7793 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
7794 kvm_rip_write(vcpu, 0x8000);
7795
7796 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
7797 kvm_x86_ops->set_cr0(vcpu, cr0);
7798 vcpu->arch.cr0 = cr0;
7799
7800 kvm_x86_ops->set_cr4(vcpu, 0);
7801
18c3626e
PB		 7802 /* Undocumented: IDT limit is set to zero on entry to SMM. */
7803 dt.address = dt.size = 0;
7804 kvm_x86_ops->set_idt(vcpu, &dt);
7805
660a5d51
PB		 7806 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
7807
7808 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
7809 cs.base = vcpu->arch.smbase;
7810
7811 ds.selector = 0;
7812 ds.base = 0;
7813
7814 cs.limit = ds.limit = 0xffffffff;
7815 cs.type = ds.type = 0x3;
7816 cs.dpl = ds.dpl = 0;
7817 cs.db = ds.db = 0;
7818 cs.s = ds.s = 1;
7819 cs.l = ds.l = 0;
7820 cs.g = ds.g = 1;
7821 cs.avl = ds.avl = 0;
7822 cs.present = ds.present = 1;
7823 cs.unusable = ds.unusable = 0;
7824 cs.padding = ds.padding = 0;
7825
7826 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7827 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
7828 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
7829 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
7830 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
7831 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
7832
b68f3cc7 7833#ifdef CONFIG_X86_64
d6321d49 7834 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
660a5d51 7835 kvm_x86_ops->set_efer(vcpu, 0);
b68f3cc7 7836#endif
660a5d51
PB		 7837
7838 kvm_update_cpuid(vcpu);
7839 kvm_mmu_reset_context(vcpu);
64d60670
PB		 7840}
7841
ee2cd4b7 7842static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 7843{
7844 vcpu->arch.smi_pending = true;
7845 kvm_make_request(KVM_REQ_EVENT, vcpu);
7846}
7847
2860c4b1
PB		 7848void kvm_make_scan_ioapic_request(struct kvm *kvm)
7849{
7850 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
7851}
7852
3d81bc7e 7853static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 7854{
dcbd3e49 7855 if (!kvm_apic_present(vcpu))
3d81bc7e 7856 return;
c7c9c56c 7857
6308630b 7858 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 7859
b053b2ae 7860 if (irqchip_split(vcpu->kvm))
6308630b 7861 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7862 else {
fa59cc00 7863 if (vcpu->arch.apicv_active)
d62caabb 7864 kvm_x86_ops->sync_pir_to_irr(vcpu);
e97f852f
WL		 7865 if (ioapic_in_kernel(vcpu->kvm))
7866 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7867 }
e40ff1d6
LA		 7868
7869 if (is_guest_mode(vcpu))
7870 vcpu->arch.load_eoi_exitmap_pending = true;
7871 else
7872 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
7873}
7874
7875static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
7876{
7877 u64 eoi_exit_bitmap[4];
7878
7879 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7880 return;
7881
5c919412
AS		 7882 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
7883 vcpu_to_synic(vcpu)->vec_bitmap, 256);
7884 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 7885}
7886
93065ac7
MH		 7887int kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
7888 unsigned long start, unsigned long end,
7889 bool blockable)
b1394e74
RK		 7890{
7891 unsigned long apic_address;
7892
7893 /*
7894 * The physical address of apic access page is stored in the VMCS.
7895 * Update it when it becomes invalid.
7896 */
7897 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7898 if (start <= apic_address && apic_address < end)
7899 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
93065ac7
MH		 7900
7901 return 0;
b1394e74
RK		 7902}
7903
4256f43f
TC		 7904void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
7905{
c24ae0dc
TC		 7906 struct page *page = NULL;
7907
35754c98 7908 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 7909 return;
7910
4256f43f
TC		 7911 if (!kvm_x86_ops->set_apic_access_page_addr)
7912 return;
7913
c24ae0dc 7914 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 7915 if (is_error_page(page))
7916 return;
c24ae0dc
TC		 7917 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
7918
7919 /*
7920 * Do not pin apic access page in memory, the MMU notifier
7921 * will call us again if it is migrated or swapped out.
7922 */
7923 put_page(page);
4256f43f
TC		 7924}
7925EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
7926
d264ee0c
SC		 7927void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
7928{
7929 smp_send_reschedule(vcpu->cpu);
7930}
7931EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
7932
9357d939 7933/*
362c698f 7934 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 7935 * exiting to the userspace. Otherwise, the value will be returned to the
7936 * userspace.
7937 */
851ba692 7938static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 7939{
7940 int r;
62a193ed
MG		 7941 bool req_int_win =
7942 dm_request_for_irq_injection(vcpu) &&
7943 kvm_cpu_accept_dm_intr(vcpu);
7944
730dca42 7945 bool req_immediate_exit = false;
b6c7a5dc 7946
2fa6e1e1 7947 if (kvm_request_pending(vcpu)) {
7f7f1ba3
PB		 7948 if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu))
7949 kvm_x86_ops->get_vmcs12_pages(vcpu);
a8eeb04a 7950 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 7951 kvm_mmu_unload(vcpu);
a8eeb04a 7952 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 7953 __kvm_migrate_timers(vcpu);
d828199e
MT		 7954 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
7955 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 7956 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
7957 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 7958 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
7959 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 7960 if (unlikely(r))
7961 goto out;
7962 }
a8eeb04a 7963 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 7964 kvm_mmu_sync_roots(vcpu);
6e42782f
JS		 7965 if (kvm_check_request(KVM_REQ_LOAD_CR3, vcpu))
7966 kvm_mmu_load_cr3(vcpu);
a8eeb04a 7967 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
c2ba05cc 7968 kvm_vcpu_flush_tlb(vcpu, true);
a8eeb04a 7969 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 7970 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 7971 r = 0;
7972 goto out;
7973 }
a8eeb04a 7974 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 7975 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 7976 vcpu->mmio_needed = 0;
71c4dfaf
JR		 7977 r = 0;
7978 goto out;
7979 }
af585b92
GN		 7980 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
7981 /* Page is swapped out. Do synthetic halt */
7982 vcpu->arch.apf.halted = true;
7983 r = 1;
7984 goto out;
7985 }
c9aaa895
GC		 7986 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
7987 record_steal_time(vcpu);
64d60670
PB		 7988 if (kvm_check_request(KVM_REQ_SMI, vcpu))
7989 process_smi(vcpu);
7460fb4a
AK		 7990 if (kvm_check_request(KVM_REQ_NMI, vcpu))
7991 process_nmi(vcpu);
f5132b01 7992 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 7993 kvm_pmu_handle_event(vcpu);
f5132b01 7994 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 7995 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 7996 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
7997 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
7998 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 7999 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 8000 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
8001 vcpu->run->eoi.vector =
8002 vcpu->arch.pending_ioapic_eoi;
8003 r = 0;
8004 goto out;
8005 }
8006 }
3d81bc7e
YZ		 8007 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
8008 vcpu_scan_ioapic(vcpu);
e40ff1d6
LA		 8009 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
8010 vcpu_load_eoi_exitmap(vcpu);
4256f43f
TC		 8011 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
8012 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 8013 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
8014 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8015 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
8016 r = 0;
8017 goto out;
8018 }
e516cebb
AS		 8019 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
8020 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8021 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
8022 r = 0;
8023 goto out;
8024 }
db397571
AS		 8025 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
8026 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
8027 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
8028 r = 0;
8029 goto out;
8030 }
f3b138c5
AS		 8031
8032 /*
8033 * KVM_REQ_HV_STIMER has to be processed after
8034 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
8035 * depend on the guest clock being up-to-date
8036 */
1f4b34f8
AS		 8037 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
8038 kvm_hv_process_stimers(vcpu);
2f52d58c 8039 }
b93463aa 8040
b463a6f7 8041 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 8042 ++vcpu->stat.req_event;
66450a21
JK		 8043 kvm_apic_accept_events(vcpu);
8044 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
8045 r = 1;
8046 goto out;
8047 }
8048
b6b8a145
JK		 8049 if (inject_pending_event(vcpu, req_int_win) != 0)
8050 req_immediate_exit = true;
321c5658 8051 else {
cc3d967f 8052 /* Enable SMI/NMI/IRQ window open exits if needed.
c43203ca 8053 *
cc3d967f
LP		 8054 * SMIs have three cases:
8055 * 1) They can be nested, and then there is nothing to
8056 * do here because RSM will cause a vmexit anyway.
8057 * 2) There is an ISA-specific reason why SMI cannot be
8058 * injected, and the moment when this changes can be
8059 * intercepted.
8060 * 3) Or the SMI can be pending because
8061 * inject_pending_event has completed the injection
8062 * of an IRQ or NMI from the previous vmexit, and
8063 * then we request an immediate exit to inject the
8064 * SMI.
c43203ca
PB		 8065 */
8066 if (vcpu->arch.smi_pending && !is_smm(vcpu))
cc3d967f
LP		 8067 if (!kvm_x86_ops->enable_smi_window(vcpu))
8068 req_immediate_exit = true;
321c5658
YS		 8069 if (vcpu->arch.nmi_pending)
8070 kvm_x86_ops->enable_nmi_window(vcpu);
8071 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
8072 kvm_x86_ops->enable_irq_window(vcpu);
664f8e26 8073 WARN_ON(vcpu->arch.exception.pending);
321c5658 8074 }
b463a6f7
AK		 8075
8076 if (kvm_lapic_enabled(vcpu)) {
8077 update_cr8_intercept(vcpu);
8078 kvm_lapic_sync_to_vapic(vcpu);
8079 }
8080 }
8081
d8368af8
AK		 8082 r = kvm_mmu_reload(vcpu);
8083 if (unlikely(r)) {
d905c069 8084 goto cancel_injection;
d8368af8
AK		 8085 }
8086
b6c7a5dc
HB		 8087 preempt_disable();
8088
8089 kvm_x86_ops->prepare_guest_switch(vcpu);
b95234c8
PB		 8090
8091 /*
8092 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
8093 * IPI are then delayed after guest entry, which ensures that they
8094 * result in virtual interrupt delivery.
8095 */
8096 local_irq_disable();
6b7e2d09
XG		 8097 vcpu->mode = IN_GUEST_MODE;
8098
01b71917
MT		 8099 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8100
0f127d12 8101 /*
b95234c8 8102 * 1) We should set ->mode before checking ->requests. Please see
cde9af6e 8103 * the comment in kvm_vcpu_exiting_guest_mode().
b95234c8 8104 *
81b01667 8105 * 2) For APICv, we should set ->mode before checking PID.ON. This
b95234c8
PB		 8106 * pairs with the memory barrier implicit in pi_test_and_set_on
8107 * (see vmx_deliver_posted_interrupt).
8108 *
8109 * 3) This also orders the write to mode from any reads to the page
8110 * tables done while the VCPU is running. Please see the comment
8111 * in kvm_flush_remote_tlbs.
6b7e2d09 8112 */
01b71917 8113 smp_mb__after_srcu_read_unlock();
b6c7a5dc 8114
b95234c8
PB		 8115 /*
8116 * This handles the case where a posted interrupt was
8117 * notified with kvm_vcpu_kick.
8118 */
fa59cc00
LA		 8119 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
8120 kvm_x86_ops->sync_pir_to_irr(vcpu);
32f88400 8121
2fa6e1e1 8122 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
d94e1dc9 8123 || need_resched() || signal_pending(current)) {
6b7e2d09 8124 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 8125 smp_wmb();
6c142801
AK		 8126 local_irq_enable();
8127 preempt_enable();
01b71917 8128 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 8129 r = 1;
d905c069 8130 goto cancel_injection;
6c142801
AK		 8131 }
8132
c43203ca
PB		 8133 if (req_immediate_exit) {
8134 kvm_make_request(KVM_REQ_EVENT, vcpu);
d264ee0c 8135 kvm_x86_ops->request_immediate_exit(vcpu);
c43203ca 8136 }
d6185f20 8137
8b89fe1f 8138 trace_kvm_entry(vcpu->vcpu_id);
6edaa530 8139 guest_enter_irqoff();
b6c7a5dc 8140
e7517324
WL		 8141 /* The preempt notifier should have taken care of the FPU already. */
8142 WARN_ON_ONCE(test_thread_flag(TIF_NEED_FPU_LOAD));
5f409e20 8143
42dbaa5a 8144 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 8145 set_debugreg(0, 7);
8146 set_debugreg(vcpu->arch.eff_db[0], 0);
8147 set_debugreg(vcpu->arch.eff_db[1], 1);
8148 set_debugreg(vcpu->arch.eff_db[2], 2);
8149 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 8150 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 8151 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 8152 }
b6c7a5dc 8153
851ba692 8154 kvm_x86_ops->run(vcpu);
b6c7a5dc 8155
c77fb5fe
PB		 8156 /*
8157 * Do this here before restoring debug registers on the host. And
8158 * since we do this before handling the vmexit, a DR access vmexit
8159 * can (a) read the correct value of the debug registers, (b) set
8160 * KVM_DEBUGREG_WONT_EXIT again.
8161 */
8162 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 8163 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
8164 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 8165 kvm_update_dr0123(vcpu);
8166 kvm_update_dr6(vcpu);
8167 kvm_update_dr7(vcpu);
8168 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 8169 }
8170
24f1e32c
FW		 8171 /*
8172 * If the guest has used debug registers, at least dr7
8173 * will be disabled while returning to the host.
8174 * If we don't have active breakpoints in the host, we don't
8175 * care about the messed up debug address registers. But if
8176 * we have some of them active, restore the old state.
8177 */
59d8eb53 8178 if (hw_breakpoint_active())
24f1e32c 8179 hw_breakpoint_restore();
42dbaa5a 8180
4ba76538 8181 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 8182
6b7e2d09 8183 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 8184 smp_wmb();
a547c6db 8185
95b5a48c 8186 kvm_x86_ops->handle_exit_irqoff(vcpu);
b6c7a5dc 8187
d7a08882
SC		 8188 /*
8189 * Consume any pending interrupts, including the possible source of
8190 * VM-Exit on SVM and any ticks that occur between VM-Exit and now.
8191 * An instruction is required after local_irq_enable() to fully unblock
8192 * interrupts on processors that implement an interrupt shadow, the
8193 * stat.exits increment will do nicely.
8194 */
8195 kvm_before_interrupt(vcpu);
8196 local_irq_enable();
b6c7a5dc 8197 ++vcpu->stat.exits;
d7a08882
SC		 8198 local_irq_disable();
8199 kvm_after_interrupt(vcpu);
b6c7a5dc 8200
f2485b3e 8201 guest_exit_irqoff();
ec0671d5
WL		 8202 if (lapic_in_kernel(vcpu)) {
8203 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta;
8204 if (delta != S64_MIN) {
8205 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta);
8206 vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN;
8207 }
8208 }
b6c7a5dc 8209
f2485b3e 8210 local_irq_enable();
b6c7a5dc
HB		 8211 preempt_enable();
8212
f656ce01 8213 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 8214
b6c7a5dc
HB		 8215 /*
8216 * Profile KVM exit RIPs:
8217 */
8218 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 8219 unsigned long rip = kvm_rip_read(vcpu);
8220 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 8221 }
8222
cc578287
ZA		 8223 if (unlikely(vcpu->arch.tsc_always_catchup))
8224 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 8225
5cfb1d5a
MT		 8226 if (vcpu->arch.apic_attention)
8227 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 8228
618232e2 8229 vcpu->arch.gpa_available = false;
851ba692 8230 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 8231 return r;
8232
8233cancel_injection:
8234 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 8235 if (unlikely(vcpu->arch.apic_attention))
8236 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 8237out:
8238 return r;
8239}
b6c7a5dc 8240
362c698f
PB		 8241static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
8242{
bf9f6ac8
FW		 8243 if (!kvm_arch_vcpu_runnable(vcpu) &&
8244 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 8245 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8246 kvm_vcpu_block(vcpu);
8247 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 8248
8249 if (kvm_x86_ops->post_block)
8250 kvm_x86_ops->post_block(vcpu);
8251
9c8fd1ba
PB		 8252 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
8253 return 1;
8254 }
362c698f
PB		 8255
8256 kvm_apic_accept_events(vcpu);
8257 switch(vcpu->arch.mp_state) {
8258 case KVM_MP_STATE_HALTED:
8259 vcpu->arch.pv.pv_unhalted = false;
8260 vcpu->arch.mp_state =
8261 KVM_MP_STATE_RUNNABLE;
b2869f28 8262 /* fall through */
362c698f
PB		 8263 case KVM_MP_STATE_RUNNABLE:
8264 vcpu->arch.apf.halted = false;
8265 break;
8266 case KVM_MP_STATE_INIT_RECEIVED:
8267 break;
8268 default:
8269 return -EINTR;
8270 break;
8271 }
8272 return 1;
8273}
09cec754 8274
5d9bc648
PB		 8275static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
8276{
0ad3bed6
PB		 8277 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8278 kvm_x86_ops->check_nested_events(vcpu, false);
8279
5d9bc648
PB		 8280 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
8281 !vcpu->arch.apf.halted);
8282}
8283
362c698f 8284static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 8285{
8286 int r;
f656ce01 8287 struct kvm *kvm = vcpu->kvm;
d7690175 8288
f656ce01 8289 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
c595ceee 8290 vcpu->arch.l1tf_flush_l1d = true;
d7690175 8291
362c698f 8292 for (;;) {
58f800d5 8293 if (kvm_vcpu_running(vcpu)) {
851ba692 8294 r = vcpu_enter_guest(vcpu);
bf9f6ac8 8295 } else {
362c698f 8296 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 8297 }
8298
09cec754
GN		 8299 if (r <= 0)
8300 break;
8301
72875d8a 8302 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
09cec754
GN		 8303 if (kvm_cpu_has_pending_timer(vcpu))
8304 kvm_inject_pending_timer_irqs(vcpu);
8305
782d422b
MG		 8306 if (dm_request_for_irq_injection(vcpu) &&
8307 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 8308 r = 0;
8309 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 8310 ++vcpu->stat.request_irq_exits;
362c698f 8311 break;
09cec754 8312 }
af585b92
GN		 8313
8314 kvm_check_async_pf_completion(vcpu);
8315
09cec754
GN		 8316 if (signal_pending(current)) {
8317 r = -EINTR;
851ba692 8318 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 8319 ++vcpu->stat.signal_exits;
362c698f 8320 break;
09cec754
GN		 8321 }
8322 if (need_resched()) {
f656ce01 8323 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 8324 cond_resched();
f656ce01 8325 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 8326 }
b6c7a5dc
HB		 8327 }
8328
f656ce01 8329 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 8330
8331 return r;
8332}
8333
716d51ab
GN		 8334static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
8335{
8336 int r;
60fc3d02 8337
716d51ab 8338 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
0ce97a2b 8339 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
716d51ab 8340 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
60fc3d02 8341 return r;
716d51ab
GN		 8342}
8343
8344static int complete_emulated_pio(struct kvm_vcpu *vcpu)
8345{
8346 BUG_ON(!vcpu->arch.pio.count);
8347
8348 return complete_emulated_io(vcpu);
8349}
8350
f78146b0
AK		 8351/*
8352 * Implements the following, as a state machine:
8353 *
8354 * read:
8355 * for each fragment
87da7e66
XG		 8356 * for each mmio piece in the fragment
8357 * write gpa, len
8358 * exit
8359 * copy data
f78146b0
AK		 8360 * execute insn
8361 *
8362 * write:
8363 * for each fragment
87da7e66
XG		 8364 * for each mmio piece in the fragment
8365 * write gpa, len
8366 * copy data
8367 * exit
f78146b0 8368 */
716d51ab 8369static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 8370{
8371 struct kvm_run *run = vcpu->run;
f78146b0 8372 struct kvm_mmio_fragment *frag;
87da7e66 8373 unsigned len;
5287f194 8374
716d51ab 8375 BUG_ON(!vcpu->mmio_needed);
5287f194 8376
716d51ab 8377 /* Complete previous fragment */
87da7e66
XG		 8378 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
8379 len = min(8u, frag->len);
716d51ab 8380 if (!vcpu->mmio_is_write)
87da7e66
XG		 8381 memcpy(frag->data, run->mmio.data, len);
8382
8383 if (frag->len <= 8) {
8384 /* Switch to the next fragment. */
8385 frag++;
8386 vcpu->mmio_cur_fragment++;
8387 } else {
8388 /* Go forward to the next mmio piece. */
8389 frag->data += len;
8390 frag->gpa += len;
8391 frag->len -= len;
8392 }
8393
a08d3b3b 8394 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 8395 vcpu->mmio_needed = 0;
0912c977
PB		 8396
8397 /* FIXME: return into emulator if single-stepping. */
cef4dea0 8398 if (vcpu->mmio_is_write)
716d51ab
GN		 8399 return 1;
8400 vcpu->mmio_read_completed = 1;
8401 return complete_emulated_io(vcpu);
8402 }
87da7e66 8403
716d51ab
GN		 8404 run->exit_reason = KVM_EXIT_MMIO;
8405 run->mmio.phys_addr = frag->gpa;
8406 if (vcpu->mmio_is_write)
87da7e66
XG		 8407 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
8408 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 8409 run->mmio.is_write = vcpu->mmio_is_write;
8410 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
8411 return 0;
5287f194
AK		 8412}
8413
822f312d
SAS		 8414/* Swap (qemu) user FPU context for the guest FPU context. */
8415static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
8416{
5f409e20
RR		 8417 fpregs_lock();
8418
d9a710e5 8419 copy_fpregs_to_fpstate(vcpu->arch.user_fpu);
822f312d 8420 /* PKRU is separately restored in kvm_x86_ops->run. */
b666a4b6 8421 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state,
822f312d 8422 ~XFEATURE_MASK_PKRU);
5f409e20
RR		 8423
8424 fpregs_mark_activate();
8425 fpregs_unlock();
8426
822f312d
SAS		 8427 trace_kvm_fpu(1);
8428}
8429
8430/* When vcpu_run ends, restore user space FPU context. */
8431static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8432{
5f409e20
RR		 8433 fpregs_lock();
8434
b666a4b6 8435 copy_fpregs_to_fpstate(vcpu->arch.guest_fpu);
d9a710e5 8436 copy_kernel_to_fpregs(&vcpu->arch.user_fpu->state);
5f409e20
RR		 8437
8438 fpregs_mark_activate();
8439 fpregs_unlock();
8440
822f312d
SAS		 8441 ++vcpu->stat.fpu_reload;
8442 trace_kvm_fpu(0);
8443}
8444
b6c7a5dc
HB		 8445int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
8446{
8447 int r;
b6c7a5dc 8448
accb757d 8449 vcpu_load(vcpu);
20b7035c 8450 kvm_sigset_activate(vcpu);
5663d8f9
PX		 8451 kvm_load_guest_fpu(vcpu);
8452
a4535290 8453 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
2f173d26
JS		 8454 if (kvm_run->immediate_exit) {
8455 r = -EINTR;
8456 goto out;
8457 }
b6c7a5dc 8458 kvm_vcpu_block(vcpu);
66450a21 8459 kvm_apic_accept_events(vcpu);
72875d8a 8460 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
ac9f6dc0 8461 r = -EAGAIN;
a0595000
JS		 8462 if (signal_pending(current)) {
8463 r = -EINTR;
8464 vcpu->run->exit_reason = KVM_EXIT_INTR;
8465 ++vcpu->stat.signal_exits;
8466 }
ac9f6dc0 8467 goto out;
b6c7a5dc
HB		 8468 }
8469
01643c51
KH		 8470 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
8471 r = -EINVAL;
8472 goto out;
8473 }
8474
8475 if (vcpu->run->kvm_dirty_regs) {
8476 r = sync_regs(vcpu);
8477 if (r != 0)
8478 goto out;
8479 }
8480
b6c7a5dc 8481 /* re-sync apic's tpr */
35754c98 8482 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 8483 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
8484 r = -EINVAL;
8485 goto out;
8486 }
8487 }
b6c7a5dc 8488
716d51ab
GN		 8489 if (unlikely(vcpu->arch.complete_userspace_io)) {
8490 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
8491 vcpu->arch.complete_userspace_io = NULL;
8492 r = cui(vcpu);
8493 if (r <= 0)
5663d8f9 8494 goto out;
716d51ab
GN		 8495 } else
8496 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 8497
460df4c1
PB		 8498 if (kvm_run->immediate_exit)
8499 r = -EINTR;
8500 else
8501 r = vcpu_run(vcpu);
b6c7a5dc
HB		 8502
8503out:
5663d8f9 8504 kvm_put_guest_fpu(vcpu);
01643c51
KH		 8505 if (vcpu->run->kvm_valid_regs)
8506 store_regs(vcpu);
f1d86e46 8507 post_kvm_run_save(vcpu);
20b7035c 8508 kvm_sigset_deactivate(vcpu);
b6c7a5dc 8509
accb757d 8510 vcpu_put(vcpu);
b6c7a5dc
HB		 8511 return r;
8512}
8513
01643c51 8514static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 8515{
7ae441ea
GN		 8516 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
8517 /*
8518 * We are here if userspace calls get_regs() in the middle of
8519 * instruction emulation. Registers state needs to be copied
4a969980 8520 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 8521 * that usually, but some bad designed PV devices (vmware
8522 * backdoor interface) need this to work
8523 */
dd856efa 8524 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 8525 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8526 }
de3cd117
SC		 8527 regs->rax = kvm_rax_read(vcpu);
8528 regs->rbx = kvm_rbx_read(vcpu);
8529 regs->rcx = kvm_rcx_read(vcpu);
8530 regs->rdx = kvm_rdx_read(vcpu);
8531 regs->rsi = kvm_rsi_read(vcpu);
8532 regs->rdi = kvm_rdi_read(vcpu);
e9c16c78 8533 regs->rsp = kvm_rsp_read(vcpu);
de3cd117 8534 regs->rbp = kvm_rbp_read(vcpu);
b6c7a5dc 8535#ifdef CONFIG_X86_64
de3cd117
SC		 8536 regs->r8 = kvm_r8_read(vcpu);
8537 regs->r9 = kvm_r9_read(vcpu);
8538 regs->r10 = kvm_r10_read(vcpu);
8539 regs->r11 = kvm_r11_read(vcpu);
8540 regs->r12 = kvm_r12_read(vcpu);
8541 regs->r13 = kvm_r13_read(vcpu);
8542 regs->r14 = kvm_r14_read(vcpu);
8543 regs->r15 = kvm_r15_read(vcpu);
b6c7a5dc
HB		 8544#endif
8545
5fdbf976 8546 regs->rip = kvm_rip_read(vcpu);
91586a3b 8547 regs->rflags = kvm_get_rflags(vcpu);
01643c51 8548}
b6c7a5dc 8549
01643c51
KH		 8550int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8551{
8552 vcpu_load(vcpu);
8553 __get_regs(vcpu, regs);
1fc9b76b 8554 vcpu_put(vcpu);
b6c7a5dc
HB		 8555 return 0;
8556}
8557
01643c51 8558static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 8559{
7ae441ea
GN		 8560 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
8561 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8562
de3cd117
SC		 8563 kvm_rax_write(vcpu, regs->rax);
8564 kvm_rbx_write(vcpu, regs->rbx);
8565 kvm_rcx_write(vcpu, regs->rcx);
8566 kvm_rdx_write(vcpu, regs->rdx);
8567 kvm_rsi_write(vcpu, regs->rsi);
8568 kvm_rdi_write(vcpu, regs->rdi);
e9c16c78 8569 kvm_rsp_write(vcpu, regs->rsp);
de3cd117 8570 kvm_rbp_write(vcpu, regs->rbp);
b6c7a5dc 8571#ifdef CONFIG_X86_64
de3cd117
SC		 8572 kvm_r8_write(vcpu, regs->r8);
8573 kvm_r9_write(vcpu, regs->r9);
8574 kvm_r10_write(vcpu, regs->r10);
8575 kvm_r11_write(vcpu, regs->r11);
8576 kvm_r12_write(vcpu, regs->r12);
8577 kvm_r13_write(vcpu, regs->r13);
8578 kvm_r14_write(vcpu, regs->r14);
8579 kvm_r15_write(vcpu, regs->r15);
b6c7a5dc
HB		 8580#endif
8581
5fdbf976 8582 kvm_rip_write(vcpu, regs->rip);
d73235d1 8583 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
b6c7a5dc 8584
b4f14abd
JK		 8585 vcpu->arch.exception.pending = false;
8586
3842d135 8587 kvm_make_request(KVM_REQ_EVENT, vcpu);
01643c51 8588}
3842d135 8589
01643c51
KH		 8590int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8591{
8592 vcpu_load(vcpu);
8593 __set_regs(vcpu, regs);
875656fe 8594 vcpu_put(vcpu);
b6c7a5dc
HB		 8595 return 0;
8596}
8597
b6c7a5dc
HB		 8598void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
8599{
8600 struct kvm_segment cs;
8601
3e6e0aab 8602 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 8603 *db = cs.db;
8604 *l = cs.l;
8605}
8606EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
8607
01643c51 8608static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 8609{
89a27f4d 8610 struct desc_ptr dt;
b6c7a5dc 8611
3e6e0aab
GT		 8612 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8613 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8614 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8615 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8616 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8617 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 8618
3e6e0aab
GT		 8619 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8620 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 8621
8622 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 8623 sregs->idt.limit = dt.size;
8624 sregs->idt.base = dt.address;
b6c7a5dc 8625 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 8626 sregs->gdt.limit = dt.size;
8627 sregs->gdt.base = dt.address;
b6c7a5dc 8628
4d4ec087 8629 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 8630 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 8631 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 8632 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 8633 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 8634 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 8635 sregs->apic_base = kvm_get_apic_base(vcpu);
8636
0e96f31e 8637 memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap));
b6c7a5dc 8638
04140b41 8639 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 8640 set_bit(vcpu->arch.interrupt.nr,
8641 (unsigned long *)sregs->interrupt_bitmap);
01643c51 8642}
16d7a191 8643
01643c51
KH		 8644int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
8645 struct kvm_sregs *sregs)
8646{
8647 vcpu_load(vcpu);
8648 __get_sregs(vcpu, sregs);
bcdec41c 8649 vcpu_put(vcpu);
b6c7a5dc
HB		 8650 return 0;
8651}
8652
62d9f0db
MT		 8653int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
8654 struct kvm_mp_state *mp_state)
8655{
fd232561
CD		 8656 vcpu_load(vcpu);
8657
66450a21 8658 kvm_apic_accept_events(vcpu);
6aef266c
SV		 8659 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
8660 vcpu->arch.pv.pv_unhalted)
8661 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
8662 else
8663 mp_state->mp_state = vcpu->arch.mp_state;
8664
fd232561 8665 vcpu_put(vcpu);
62d9f0db
MT		 8666 return 0;
8667}
8668
8669int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
8670 struct kvm_mp_state *mp_state)
8671{
e83dff5e
CD		 8672 int ret = -EINVAL;
8673
8674 vcpu_load(vcpu);
8675
bce87cce 8676 if (!lapic_in_kernel(vcpu) &&
66450a21 8677 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
e83dff5e 8678 goto out;
66450a21 8679
28bf2888
DH		 8680 /* INITs are latched while in SMM */
8681 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
8682 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
8683 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
e83dff5e 8684 goto out;
28bf2888 8685
66450a21
JK		 8686 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
8687 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
8688 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
8689 } else
8690 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 8691 kvm_make_request(KVM_REQ_EVENT, vcpu);
e83dff5e
CD		 8692
8693 ret = 0;
8694out:
8695 vcpu_put(vcpu);
8696 return ret;
62d9f0db
MT		 8697}
8698
7f3d35fd
KW		 8699int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
8700 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 8701{
9d74191a 8702 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 8703 int ret;
e01c2426 8704
8ec4722d 8705 init_emulate_ctxt(vcpu);
c697518a 8706
7f3d35fd 8707 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 8708 has_error_code, error_code);
1051778f
SC		 8709 if (ret) {
8710 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8711 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
8712 vcpu->run->internal.ndata = 0;
60fc3d02 8713 return 0;
1051778f 8714 }
37817f29 8715
9d74191a
TY		 8716 kvm_rip_write(vcpu, ctxt->eip);
8717 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 8718 kvm_make_request(KVM_REQ_EVENT, vcpu);
60fc3d02 8719 return 1;
37817f29
IE		 8720}
8721EXPORT_SYMBOL_GPL(kvm_task_switch);
8722
3140c156 8723static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
f2981033 8724{
37b95951 8725 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
f2981033
LT		 8726 /*
8727 * When EFER.LME and CR0.PG are set, the processor is in
8728 * 64-bit mode (though maybe in a 32-bit code segment).
8729 * CR4.PAE and EFER.LMA must be set.
8730 */
37b95951 8731 if (!(sregs->cr4 & X86_CR4_PAE)
f2981033
LT		 8732 || !(sregs->efer & EFER_LMA))
8733 return -EINVAL;
8734 } else {
8735 /*
8736 * Not in 64-bit mode: EFER.LMA is clear and the code
8737 * segment cannot be 64-bit.
8738 */
8739 if (sregs->efer & EFER_LMA || sregs->cs.l)
8740 return -EINVAL;
8741 }
8742
3ca94192 8743 return kvm_valid_cr4(vcpu, sregs->cr4);
f2981033
LT		 8744}
8745
01643c51 8746static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 8747{
58cb628d 8748 struct msr_data apic_base_msr;
b6c7a5dc 8749 int mmu_reset_needed = 0;
c4d21882 8750 int cpuid_update_needed = 0;
63f42e02 8751 int pending_vec, max_bits, idx;
89a27f4d 8752 struct desc_ptr dt;
b4ef9d4e
CD		 8753 int ret = -EINVAL;
8754
f2981033 8755 if (kvm_valid_sregs(vcpu, sregs))
8dbfb2bf 8756 goto out;
f2981033 8757
d3802286
JM		 8758 apic_base_msr.data = sregs->apic_base;
8759 apic_base_msr.host_initiated = true;
8760 if (kvm_set_apic_base(vcpu, &apic_base_msr))
b4ef9d4e 8761 goto out;
6d1068b3 8762
89a27f4d
GN		 8763 dt.size = sregs->idt.limit;
8764 dt.address = sregs->idt.base;
b6c7a5dc 8765 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 8766 dt.size = sregs->gdt.limit;
8767 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 8768 kvm_x86_ops->set_gdt(vcpu, &dt);
8769
ad312c7c 8770 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 8771 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 8772 vcpu->arch.cr3 = sregs->cr3;
aff48baa 8773 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 8774
2d3ad1f4 8775 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 8776
f6801dff 8777 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 8778 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc 8779
4d4ec087 8780 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 8781 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 8782 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 8783
fc78f519 8784 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
c4d21882
WH		 8785 cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
8786 (X86_CR4_OSXSAVE | X86_CR4_PKE));
b6c7a5dc 8787 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
c4d21882 8788 if (cpuid_update_needed)
00b27a3e 8789 kvm_update_cpuid(vcpu);
63f42e02
XG		 8790
8791 idx = srcu_read_lock(&vcpu->kvm->srcu);
bf03d4f9 8792 if (is_pae_paging(vcpu)) {
9f8fe504 8793 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 8794 mmu_reset_needed = 1;
8795 }
63f42e02 8796 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 8797
8798 if (mmu_reset_needed)
8799 kvm_mmu_reset_context(vcpu);
8800
a50abc3b 8801 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 8802 pending_vec = find_first_bit(
8803 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
8804 if (pending_vec < max_bits) {
66fd3f7f 8805 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 8806 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 8807 }
8808
3e6e0aab
GT		 8809 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8810 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8811 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8812 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8813 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8814 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 8815
3e6e0aab
GT		 8816 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8817 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 8818
5f0269f5
ME		 8819 update_cr8_intercept(vcpu);
8820
9c3e4aab 8821 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 8822 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 8823 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 8824 !is_protmode(vcpu))
9c3e4aab
MT		 8825 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8826
3842d135
AK		 8827 kvm_make_request(KVM_REQ_EVENT, vcpu);
8828
b4ef9d4e
CD		 8829 ret = 0;
8830out:
01643c51
KH		 8831 return ret;
8832}
8833
8834int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
8835 struct kvm_sregs *sregs)
8836{
8837 int ret;
8838
8839 vcpu_load(vcpu);
8840 ret = __set_sregs(vcpu, sregs);
b4ef9d4e
CD		 8841 vcpu_put(vcpu);
8842 return ret;
b6c7a5dc
HB		 8843}
8844
d0bfb940
JK		 8845int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
8846 struct kvm_guest_debug *dbg)
b6c7a5dc 8847{
355be0b9 8848 unsigned long rflags;
ae675ef0 8849 int i, r;
b6c7a5dc 8850
66b56562
CD		 8851 vcpu_load(vcpu);
8852
4f926bf2
JK		 8853 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
8854 r = -EBUSY;
8855 if (vcpu->arch.exception.pending)
2122ff5e 8856 goto out;
4f926bf2
JK		 8857 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
8858 kvm_queue_exception(vcpu, DB_VECTOR);
8859 else
8860 kvm_queue_exception(vcpu, BP_VECTOR);
8861 }
8862
91586a3b
JK		 8863 /*
8864 * Read rflags as long as potentially injected trace flags are still
8865 * filtered out.
8866 */
8867 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 8868
8869 vcpu->guest_debug = dbg->control;
8870 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
8871 vcpu->guest_debug = 0;
8872
8873 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 8874 for (i = 0; i < KVM_NR_DB_REGS; ++i)
8875 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 8876 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 8877 } else {
8878 for (i = 0; i < KVM_NR_DB_REGS; i++)
8879 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 8880 }
c8639010 8881 kvm_update_dr7(vcpu);
ae675ef0 8882
f92653ee
JK		 8883 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8884 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
8885 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 8886
91586a3b
JK		 8887 /*
8888 * Trigger an rflags update that will inject or remove the trace
8889 * flags.
8890 */
8891 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 8892
a96036b8 8893 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 8894
4f926bf2 8895 r = 0;
d0bfb940 8896
2122ff5e 8897out:
66b56562 8898 vcpu_put(vcpu);
b6c7a5dc
HB		 8899 return r;
8900}
8901
8b006791
ZX		 8902/*
8903 * Translate a guest virtual address to a guest physical address.
8904 */
8905int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
8906 struct kvm_translation *tr)
8907{
8908 unsigned long vaddr = tr->linear_address;
8909 gpa_t gpa;
f656ce01 8910 int idx;
8b006791 8911
1da5b61d
CD		 8912 vcpu_load(vcpu);
8913
f656ce01 8914 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 8915 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 8916 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 8917 tr->physical_address = gpa;
8918 tr->valid = gpa != UNMAPPED_GVA;
8919 tr->writeable = 1;
8920 tr->usermode = 0;
8b006791 8921
1da5b61d 8922 vcpu_put(vcpu);
8b006791
ZX		 8923 return 0;
8924}
8925
d0752060
HB		 8926int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8927{
1393123e 8928 struct fxregs_state *fxsave;
d0752060 8929
1393123e 8930 vcpu_load(vcpu);
d0752060 8931
b666a4b6 8932 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
d0752060
HB		 8933 memcpy(fpu->fpr, fxsave->st_space, 128);
8934 fpu->fcw = fxsave->cwd;
8935 fpu->fsw = fxsave->swd;
8936 fpu->ftwx = fxsave->twd;
8937 fpu->last_opcode = fxsave->fop;
8938 fpu->last_ip = fxsave->rip;
8939 fpu->last_dp = fxsave->rdp;
0e96f31e 8940 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
d0752060 8941
1393123e 8942 vcpu_put(vcpu);
d0752060
HB		 8943 return 0;
8944}
8945
8946int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8947{
6a96bc7f
CD		 8948 struct fxregs_state *fxsave;
8949
8950 vcpu_load(vcpu);
8951
b666a4b6 8952 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
d0752060 8953
d0752060
HB		 8954 memcpy(fxsave->st_space, fpu->fpr, 128);
8955 fxsave->cwd = fpu->fcw;
8956 fxsave->swd = fpu->fsw;
8957 fxsave->twd = fpu->ftwx;
8958 fxsave->fop = fpu->last_opcode;
8959 fxsave->rip = fpu->last_ip;
8960 fxsave->rdp = fpu->last_dp;
0e96f31e 8961 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
d0752060 8962
6a96bc7f 8963 vcpu_put(vcpu);
d0752060
HB		 8964 return 0;
8965}
8966
01643c51
KH		 8967static void store_regs(struct kvm_vcpu *vcpu)
8968{
8969 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
8970
8971 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
8972 __get_regs(vcpu, &vcpu->run->s.regs.regs);
8973
8974 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
8975 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
8976
8977 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
8978 kvm_vcpu_ioctl_x86_get_vcpu_events(
8979 vcpu, &vcpu->run->s.regs.events);
8980}
8981
8982static int sync_regs(struct kvm_vcpu *vcpu)
8983{
8984 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
8985 return -EINVAL;
8986
8987 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
8988 __set_regs(vcpu, &vcpu->run->s.regs.regs);
8989 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
8990 }
8991 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
8992 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
8993 return -EINVAL;
8994 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
8995 }
8996 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
8997 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
8998 vcpu, &vcpu->run->s.regs.events))
8999 return -EINVAL;
9000 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
9001 }
9002
9003 return 0;
9004}
9005
0ee6a517 9006static void fx_init(struct kvm_vcpu *vcpu)
d0752060 9007{
b666a4b6 9008 fpstate_init(&vcpu->arch.guest_fpu->state);
782511b0 9009 if (boot_cpu_has(X86_FEATURE_XSAVES))
b666a4b6 9010 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv =
df1daba7 9011 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 9012
2acf923e
DC		 9013 /*
9014 * Ensure guest xcr0 is valid for loading
9015 */
d91cab78 9016 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 9017
ad312c7c 9018 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 9019}
d0752060 9020
e9b11c17
ZX		 9021void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
9022{
bd768e14
IY		 9023 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
9024
12f9a48f 9025 kvmclock_reset(vcpu);
7f1ea208 9026
e9b11c17 9027 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 9028 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 9029}
9030
9031struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
9032 unsigned int id)
9033{
c447e76b
LL		 9034 struct kvm_vcpu *vcpu;
9035
b0c39dc6 9036 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6755bae8
ZA		 9037 printk_once(KERN_WARNING
9038 "kvm: SMP vm created on host with unstable TSC; "
9039 "guest TSC will not be reliable\n");
c447e76b
LL		 9040
9041 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
9042
c447e76b 9043 return vcpu;
26e5215f 9044}
e9b11c17 9045
26e5215f
AK		 9046int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
9047{
0cf9135b 9048 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
e53d88af 9049 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
19efffa2 9050 kvm_vcpu_mtrr_init(vcpu);
ec7660cc 9051 vcpu_load(vcpu);
d28bc9dd 9052 kvm_vcpu_reset(vcpu, false);
e1732991 9053 kvm_init_mmu(vcpu, false);
e9b11c17 9054 vcpu_put(vcpu);
ec7660cc 9055 return 0;
e9b11c17
ZX		 9056}
9057
31928aa5 9058void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 9059{
8fe8ab46 9060 struct msr_data msr;
332967a3 9061 struct kvm *kvm = vcpu->kvm;
42897d86 9062
d3457c87
RK		 9063 kvm_hv_vcpu_postcreate(vcpu);
9064
ec7660cc 9065 if (mutex_lock_killable(&vcpu->mutex))
31928aa5 9066 return;
ec7660cc 9067 vcpu_load(vcpu);
8fe8ab46
WA		 9068 msr.data = 0x0;
9069 msr.index = MSR_IA32_TSC;
9070 msr.host_initiated = true;
9071 kvm_write_tsc(vcpu, &msr);
42897d86 9072 vcpu_put(vcpu);
2d5ba19b
MT		 9073
9074 /* poll control enabled by default */
9075 vcpu->arch.msr_kvm_poll_control = 1;
9076
ec7660cc 9077 mutex_unlock(&vcpu->mutex);
42897d86 9078
630994b3
MT		 9079 if (!kvmclock_periodic_sync)
9080 return;
9081
332967a3
AJ		 9082 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
9083 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 9084}
9085
d40ccc62 9086void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 9087{
344d9588
GN		 9088 vcpu->arch.apf.msr_val = 0;
9089
ec7660cc 9090 vcpu_load(vcpu);
e9b11c17
ZX		 9091 kvm_mmu_unload(vcpu);
9092 vcpu_put(vcpu);
9093
9094 kvm_x86_ops->vcpu_free(vcpu);
9095}
9096
d28bc9dd 9097void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 9098{
b7e31be3
RK		 9099 kvm_lapic_reset(vcpu, init_event);
9100
e69fab5d
PB		 9101 vcpu->arch.hflags = 0;
9102
c43203ca 9103 vcpu->arch.smi_pending = 0;
52797bf9 9104 vcpu->arch.smi_count = 0;
7460fb4a
AK		 9105 atomic_set(&vcpu->arch.nmi_queued, 0);
9106 vcpu->arch.nmi_pending = 0;
448fa4a9 9107 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 9108 kvm_clear_interrupt_queue(vcpu);
9109 kvm_clear_exception_queue(vcpu);
664f8e26 9110 vcpu->arch.exception.pending = false;
448fa4a9 9111
42dbaa5a 9112 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 9113 kvm_update_dr0123(vcpu);
6f43ed01 9114 vcpu->arch.dr6 = DR6_INIT;
73aaf249 9115 kvm_update_dr6(vcpu);
42dbaa5a 9116 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 9117 kvm_update_dr7(vcpu);
42dbaa5a 9118
1119022c
NA		 9119 vcpu->arch.cr2 = 0;
9120
3842d135 9121 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 9122 vcpu->arch.apf.msr_val = 0;
c9aaa895 9123 vcpu->arch.st.msr_val = 0;
3842d135 9124
12f9a48f
GC		 9125 kvmclock_reset(vcpu);
9126
af585b92
GN		 9127 kvm_clear_async_pf_completion_queue(vcpu);
9128 kvm_async_pf_hash_reset(vcpu);
9129 vcpu->arch.apf.halted = false;
3842d135 9130
a554d207
WL		 9131 if (kvm_mpx_supported()) {
9132 void *mpx_state_buffer;
9133
9134 /*
9135 * To avoid have the INIT path from kvm_apic_has_events() that be
9136 * called with loaded FPU and does not let userspace fix the state.
9137 */
f775b13e
RR		 9138 if (init_event)
9139 kvm_put_guest_fpu(vcpu);
b666a4b6 9140 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
abd16d68 9141 XFEATURE_BNDREGS);
a554d207
WL		 9142 if (mpx_state_buffer)
9143 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
b666a4b6 9144 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
abd16d68 9145 XFEATURE_BNDCSR);
a554d207
WL		 9146 if (mpx_state_buffer)
9147 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
f775b13e
RR		 9148 if (init_event)
9149 kvm_load_guest_fpu(vcpu);
a554d207
WL		 9150 }
9151
64d60670 9152 if (!init_event) {
d28bc9dd 9153 kvm_pmu_reset(vcpu);
64d60670 9154 vcpu->arch.smbase = 0x30000;
db2336a8 9155
db2336a8 9156 vcpu->arch.msr_misc_features_enables = 0;
a554d207
WL		 9157
9158 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
64d60670 9159 }
f5132b01 9160
66f7b72e
JS		 9161 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
9162 vcpu->arch.regs_avail = ~0;
9163 vcpu->arch.regs_dirty = ~0;
9164
a554d207
WL		 9165 vcpu->arch.ia32_xss = 0;
9166
d28bc9dd 9167 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 9168}
9169
2b4a273b 9170void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 9171{
9172 struct kvm_segment cs;
9173
9174 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
9175 cs.selector = vector << 8;
9176 cs.base = vector << 12;
9177 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
9178 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 9179}
9180
13a34e06 9181int kvm_arch_hardware_enable(void)
e9b11c17 9182{
ca84d1a2
ZA		 9183 struct kvm *kvm;
9184 struct kvm_vcpu *vcpu;
9185 int i;
0dd6a6ed
ZA		 9186 int ret;
9187 u64 local_tsc;
9188 u64 max_tsc = 0;
9189 bool stable, backwards_tsc = false;
18863bdd
AK		 9190
9191 kvm_shared_msr_cpu_online();
13a34e06 9192 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 9193 if (ret != 0)
9194 return ret;
9195
4ea1636b 9196 local_tsc = rdtsc();
b0c39dc6 9197 stable = !kvm_check_tsc_unstable();
0dd6a6ed
ZA		 9198 list_for_each_entry(kvm, &vm_list, vm_list) {
9199 kvm_for_each_vcpu(i, vcpu, kvm) {
9200 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 9201 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 9202 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
9203 backwards_tsc = true;
9204 if (vcpu->arch.last_host_tsc > max_tsc)
9205 max_tsc = vcpu->arch.last_host_tsc;
9206 }
9207 }
9208 }
9209
9210 /*
9211 * Sometimes, even reliable TSCs go backwards. This happens on
9212 * platforms that reset TSC during suspend or hibernate actions, but
9213 * maintain synchronization. We must compensate. Fortunately, we can
9214 * detect that condition here, which happens early in CPU bringup,
9215 * before any KVM threads can be running. Unfortunately, we can't
9216 * bring the TSCs fully up to date with real time, as we aren't yet far
9217 * enough into CPU bringup that we know how much real time has actually
9285ec4c 9218 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot
0dd6a6ed
ZA		 9219 * variables that haven't been updated yet.
9220 *
9221 * So we simply find the maximum observed TSC above, then record the
9222 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
9223 * the adjustment will be applied. Note that we accumulate
9224 * adjustments, in case multiple suspend cycles happen before some VCPU
9225 * gets a chance to run again. In the event that no KVM threads get a
9226 * chance to run, we will miss the entire elapsed period, as we'll have
9227 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
9228 * loose cycle time. This isn't too big a deal, since the loss will be
9229 * uniform across all VCPUs (not to mention the scenario is extremely
9230 * unlikely). It is possible that a second hibernate recovery happens
9231 * much faster than a first, causing the observed TSC here to be
9232 * smaller; this would require additional padding adjustment, which is
9233 * why we set last_host_tsc to the local tsc observed here.
9234 *
9235 * N.B. - this code below runs only on platforms with reliable TSC,
9236 * as that is the only way backwards_tsc is set above. Also note
9237 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
9238 * have the same delta_cyc adjustment applied if backwards_tsc
9239 * is detected. Note further, this adjustment is only done once,
9240 * as we reset last_host_tsc on all VCPUs to stop this from being
9241 * called multiple times (one for each physical CPU bringup).
9242 *
4a969980 9243 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 9244 * will be compensated by the logic in vcpu_load, which sets the TSC to
9245 * catchup mode. This will catchup all VCPUs to real time, but cannot
9246 * guarantee that they stay in perfect synchronization.
9247 */
9248 if (backwards_tsc) {
9249 u64 delta_cyc = max_tsc - local_tsc;
9250 list_for_each_entry(kvm, &vm_list, vm_list) {
a826faf1 9251 kvm->arch.backwards_tsc_observed = true;
0dd6a6ed
ZA		 9252 kvm_for_each_vcpu(i, vcpu, kvm) {
9253 vcpu->arch.tsc_offset_adjustment += delta_cyc;
9254 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 9255 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 9256 }
9257
9258 /*
9259 * We have to disable TSC offset matching.. if you were
9260 * booting a VM while issuing an S4 host suspend....
9261 * you may have some problem. Solving this issue is
9262 * left as an exercise to the reader.
9263 */
9264 kvm->arch.last_tsc_nsec = 0;
9265 kvm->arch.last_tsc_write = 0;
9266 }
9267
9268 }
9269 return 0;
e9b11c17
ZX		 9270}
9271
13a34e06 9272void kvm_arch_hardware_disable(void)
e9b11c17 9273{
13a34e06
RK		 9274 kvm_x86_ops->hardware_disable();
9275 drop_user_return_notifiers();
e9b11c17
ZX		 9276}
9277
9278int kvm_arch_hardware_setup(void)
9279{
9e9c3fe4
NA		 9280 int r;
9281
9282 r = kvm_x86_ops->hardware_setup();
9283 if (r != 0)
9284 return r;
9285
35181e86
HZ		 9286 if (kvm_has_tsc_control) {
9287 /*
9288 * Make sure the user can only configure tsc_khz values that
9289 * fit into a signed integer.
273ba457 9290 * A min value is not calculated because it will always
35181e86
HZ		 9291 * be 1 on all machines.
9292 */
9293 u64 max = min(0x7fffffffULL,
9294 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
9295 kvm_max_guest_tsc_khz = max;
9296
ad721883 9297 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 9298 }
ad721883 9299
9e9c3fe4
NA		 9300 kvm_init_msr_list();
9301 return 0;
e9b11c17
ZX		 9302}
9303
9304void kvm_arch_hardware_unsetup(void)
9305{
9306 kvm_x86_ops->hardware_unsetup();
9307}
9308
f257d6dc 9309int kvm_arch_check_processor_compat(void)
e9b11c17 9310{
f257d6dc 9311 return kvm_x86_ops->check_processor_compatibility();
d71ba788
PB		 9312}
9313
9314bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
9315{
9316 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
9317}
9318EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
9319
9320bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
9321{
9322 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 9323}
9324
54e9818f 9325struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 9326EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 9327
e9b11c17
ZX		 9328int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
9329{
9330 struct page *page;
e9b11c17
ZX		 9331 int r;
9332
9aabc88f 9333 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
26de7988 9334 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 9335 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 9336 else
a4535290 9337 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 9338
9339 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
9340 if (!page) {
9341 r = -ENOMEM;
9342 goto fail;
9343 }
ad312c7c 9344 vcpu->arch.pio_data = page_address(page);
e9b11c17 9345
cc578287 9346 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 9347
e9b11c17
ZX		 9348 r = kvm_mmu_create(vcpu);
9349 if (r < 0)
9350 goto fail_free_pio_data;
9351
26de7988 9352 if (irqchip_in_kernel(vcpu->kvm)) {
f7589cca 9353 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
39497d76 9354 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns);
e9b11c17
ZX		 9355 if (r < 0)
9356 goto fail_mmu_destroy;
54e9818f
GN		 9357 } else
9358 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 9359
890ca9ae 9360 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
254272ce 9361 GFP_KERNEL_ACCOUNT);
890ca9ae
HY		 9362 if (!vcpu->arch.mce_banks) {
9363 r = -ENOMEM;
443c39bc 9364 goto fail_free_lapic;
890ca9ae
HY		 9365 }
9366 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
9367
254272ce
BG		 9368 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
9369 GFP_KERNEL_ACCOUNT)) {
f1797359 9370 r = -ENOMEM;
f5f48ee1 9371 goto fail_free_mce_banks;
f1797359 9372 }
f5f48ee1 9373
0ee6a517 9374 fx_init(vcpu);
66f7b72e 9375
4344ee98 9376 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 9377
5a4f55cd
EK		 9378 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
9379
74545705
RK		 9380 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
9381
af585b92 9382 kvm_async_pf_hash_reset(vcpu);
f5132b01 9383 kvm_pmu_init(vcpu);
af585b92 9384
1c1a9ce9 9385 vcpu->arch.pending_external_vector = -1;
de63ad4c 9386 vcpu->arch.preempted_in_kernel = false;
1c1a9ce9 9387
5c919412
AS		 9388 kvm_hv_vcpu_init(vcpu);
9389
e9b11c17 9390 return 0;
0ee6a517 9391
f5f48ee1
SY		 9392fail_free_mce_banks:
9393 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 9394fail_free_lapic:
9395 kvm_free_lapic(vcpu);
e9b11c17
ZX		 9396fail_mmu_destroy:
9397 kvm_mmu_destroy(vcpu);
9398fail_free_pio_data:
ad312c7c 9399 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 9400fail:
9401 return r;
9402}
9403
9404void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
9405{
f656ce01
MT		 9406 int idx;
9407
1f4b34f8 9408 kvm_hv_vcpu_uninit(vcpu);
f5132b01 9409 kvm_pmu_destroy(vcpu);
36cb93fd 9410 kfree(vcpu->arch.mce_banks);
e9b11c17 9411 kvm_free_lapic(vcpu);
f656ce01 9412 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 9413 kvm_mmu_destroy(vcpu);
f656ce01 9414 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 9415 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 9416 if (!lapic_in_kernel(vcpu))
54e9818f 9417 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 9418}
d19a9cd2 9419
e790d9ef
RK		 9420void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
9421{
c595ceee 9422 vcpu->arch.l1tf_flush_l1d = true;
ae97a3b8 9423 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 9424}
9425
e08b9637 9426int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 9427{
e08b9637
CO		 9428 if (type)
9429 return -EINVAL;
9430
6ef768fa 9431 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 9432 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
10605204 9433 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 9434 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 9435 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 9436
5550af4d
SY		 9437 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
9438 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 9439 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
9440 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
9441 &kvm->arch.irq_sources_bitmap);
5550af4d 9442
038f8c11 9443 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 9444 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 9445 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
9446
9285ec4c 9447 kvm->arch.kvmclock_offset = -ktime_get_boottime_ns();
d828199e 9448 pvclock_update_vm_gtod_copy(kvm);
53f658b3 9449
6fbbde9a
DS		 9450 kvm->arch.guest_can_read_msr_platform_info = true;
9451
7e44e449 9452 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 9453 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 9454
cbc0236a 9455 kvm_hv_init_vm(kvm);
0eb05bf2 9456 kvm_page_track_init(kvm);
13d268ca 9457 kvm_mmu_init_vm(kvm);
0eb05bf2 9458
92735b1b 9459 return kvm_x86_ops->vm_init(kvm);
d19a9cd2
ZX		 9460}
9461
9462static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
9463{
ec7660cc 9464 vcpu_load(vcpu);
d19a9cd2
ZX		 9465 kvm_mmu_unload(vcpu);
9466 vcpu_put(vcpu);
9467}
9468
9469static void kvm_free_vcpus(struct kvm *kvm)
9470{
9471 unsigned int i;
988a2cae 9472 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 9473
9474 /*
9475 * Unpin any mmu pages first.
9476 */
af585b92
GN		 9477 kvm_for_each_vcpu(i, vcpu, kvm) {
9478 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 9479 kvm_unload_vcpu_mmu(vcpu);
af585b92 9480 }
988a2cae
GN		 9481 kvm_for_each_vcpu(i, vcpu, kvm)
9482 kvm_arch_vcpu_free(vcpu);
9483
9484 mutex_lock(&kvm->lock);
9485 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
9486 kvm->vcpus[i] = NULL;
d19a9cd2 9487
988a2cae
GN		 9488 atomic_set(&kvm->online_vcpus, 0);
9489 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 9490}
9491
ad8ba2cd
SY		 9492void kvm_arch_sync_events(struct kvm *kvm)
9493{
332967a3 9494 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 9495 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 9496 kvm_free_pit(kvm);
ad8ba2cd
SY		 9497}
9498
1d8007bd 9499int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 9500{
9501 int i, r;
25188b99 9502 unsigned long hva;
f0d648bd
PB		 9503 struct kvm_memslots *slots = kvm_memslots(kvm);
9504 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 9505
9506 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 9507 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
9508 return -EINVAL;
9da0e4d5 9509
f0d648bd
PB		 9510 slot = id_to_memslot(slots, id);
9511 if (size) {
b21629da 9512 if (slot->npages)
f0d648bd
PB		 9513 return -EEXIST;
9514
9515 /*
9516 * MAP_SHARED to prevent internal slot pages from being moved
9517 * by fork()/COW.
9518 */
9519 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
9520 MAP_SHARED | MAP_ANONYMOUS, 0);
9521 if (IS_ERR((void *)hva))
9522 return PTR_ERR((void *)hva);
9523 } else {
9524 if (!slot->npages)
9525 return 0;
9526
9527 hva = 0;
9528 }
9529
9530 old = *slot;
9da0e4d5 9531 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 9532 struct kvm_userspace_memory_region m;
9da0e4d5 9533
1d8007bd
PB		 9534 m.slot = id | (i << 16);
9535 m.flags = 0;
9536 m.guest_phys_addr = gpa;
f0d648bd 9537 m.userspace_addr = hva;
1d8007bd 9538 m.memory_size = size;
9da0e4d5
PB		 9539 r = __kvm_set_memory_region(kvm, &m);
9540 if (r < 0)
9541 return r;
9542 }
9543
103c763c
EB		 9544 if (!size)
9545 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
f0d648bd 9546
9da0e4d5
PB		 9547 return 0;
9548}
9549EXPORT_SYMBOL_GPL(__x86_set_memory_region);
9550
1d8007bd 9551int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 9552{
9553 int r;
9554
9555 mutex_lock(&kvm->slots_lock);
1d8007bd 9556 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 9557 mutex_unlock(&kvm->slots_lock);
9558
9559 return r;
9560}
9561EXPORT_SYMBOL_GPL(x86_set_memory_region);
9562
d19a9cd2
ZX		 9563void kvm_arch_destroy_vm(struct kvm *kvm)
9564{
27469d29
AH		 9565 if (current->mm == kvm->mm) {
9566 /*
9567 * Free memory regions allocated on behalf of userspace,
9568 * unless the the memory map has changed due to process exit
9569 * or fd copying.
9570 */
1d8007bd
PB		 9571 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
9572 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
9573 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 9574 }
03543133
SS		 9575 if (kvm_x86_ops->vm_destroy)
9576 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 9577 kvm_pic_destroy(kvm);
9578 kvm_ioapic_destroy(kvm);
d19a9cd2 9579 kvm_free_vcpus(kvm);
af1bae54 9580 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
66bb8a06 9581 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1));
13d268ca 9582 kvm_mmu_uninit_vm(kvm);
2beb6dad 9583 kvm_page_track_cleanup(kvm);
cbc0236a 9584 kvm_hv_destroy_vm(kvm);
d19a9cd2 9585}
0de10343 9586
5587027c 9587void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 9588 struct kvm_memory_slot *dont)
9589{
9590 int i;
9591
d89cc617
TY		 9592 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9593 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 9594 kvfree(free->arch.rmap[i]);
d89cc617 9595 free->arch.rmap[i] = NULL;
77d11309 9596 }
d89cc617
TY		 9597 if (i == 0)
9598 continue;
9599
9600 if (!dont || free->arch.lpage_info[i - 1] !=
9601 dont->arch.lpage_info[i - 1]) {
548ef284 9602 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 9603 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 9604 }
9605 }
21ebbeda
XG		 9606
9607 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 9608}
9609
5587027c
AK		 9610int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
9611 unsigned long npages)
db3fe4eb
TY		 9612{
9613 int i;
9614
d89cc617 9615 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 9616 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 9617 unsigned long ugfn;
9618 int lpages;
d89cc617 9619 int level = i + 1;
db3fe4eb
TY		 9620
9621 lpages = gfn_to_index(slot->base_gfn + npages - 1,
9622 slot->base_gfn, level) + 1;
9623
d89cc617 9624 slot->arch.rmap[i] =
778e1cdd 9625 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
254272ce 9626 GFP_KERNEL_ACCOUNT);
d89cc617 9627 if (!slot->arch.rmap[i])
77d11309 9628 goto out_free;
d89cc617
TY		 9629 if (i == 0)
9630 continue;
77d11309 9631
254272ce 9632 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
92f94f1e 9633 if (!linfo)
db3fe4eb
TY		 9634 goto out_free;
9635
92f94f1e
XG		 9636 slot->arch.lpage_info[i - 1] = linfo;
9637
db3fe4eb 9638 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 9639 linfo[0].disallow_lpage = 1;
db3fe4eb 9640 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 9641 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 9642 ugfn = slot->userspace_addr >> PAGE_SHIFT;
9643 /*
9644 * If the gfn and userspace address are not aligned wrt each
9645 * other, or if explicitly asked to, disable large page
9646 * support for this slot
9647 */
9648 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
9649 !kvm_largepages_enabled()) {
9650 unsigned long j;
9651
9652 for (j = 0; j < lpages; ++j)
92f94f1e 9653 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 9654 }
9655 }
9656
21ebbeda
XG		 9657 if (kvm_page_track_create_memslot(slot, npages))
9658 goto out_free;
9659
db3fe4eb
TY		 9660 return 0;
9661
9662out_free:
d89cc617 9663 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 9664 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 9665 slot->arch.rmap[i] = NULL;
9666 if (i == 0)
9667 continue;
9668
548ef284 9669 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 9670 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 9671 }
9672 return -ENOMEM;
9673}
9674
15248258 9675void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
e59dbe09 9676{
e6dff7d1
TY		 9677 /*
9678 * memslots->generation has been incremented.
9679 * mmio generation may have reached its maximum value.
9680 */
15248258 9681 kvm_mmu_invalidate_mmio_sptes(kvm, gen);
e59dbe09
TY		 9682}
9683
f7784b8e
MT		 9684int kvm_arch_prepare_memory_region(struct kvm *kvm,
9685 struct kvm_memory_slot *memslot,
09170a49 9686 const struct kvm_userspace_memory_region *mem,
7b6195a9 9687 enum kvm_mr_change change)
0de10343 9688{
f7784b8e
MT		 9689 return 0;
9690}
9691
88178fd4
KH		 9692static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
9693 struct kvm_memory_slot *new)
9694{
9695 /* Still write protect RO slot */
9696 if (new->flags & KVM_MEM_READONLY) {
9697 kvm_mmu_slot_remove_write_access(kvm, new);
9698 return;
9699 }
9700
9701 /*
9702 * Call kvm_x86_ops dirty logging hooks when they are valid.
9703 *
9704 * kvm_x86_ops->slot_disable_log_dirty is called when:
9705 *
9706 * - KVM_MR_CREATE with dirty logging is disabled
9707 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
9708 *
9709 * The reason is, in case of PML, we need to set D-bit for any slots
9710 * with dirty logging disabled in order to eliminate unnecessary GPA
9711 * logging in PML buffer (and potential PML buffer full VMEXT). This
9712 * guarantees leaving PML enabled during guest's lifetime won't have
bdd303cb 9713 * any additional overhead from PML when guest is running with dirty
88178fd4
KH		 9714 * logging disabled for memory slots.
9715 *
9716 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
9717 * to dirty logging mode.
9718 *
9719 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
9720 *
9721 * In case of write protect:
9722 *
9723 * Write protect all pages for dirty logging.
9724 *
9725 * All the sptes including the large sptes which point to this
9726 * slot are set to readonly. We can not create any new large
9727 * spte on this slot until the end of the logging.
9728 *
9729 * See the comments in fast_page_fault().
9730 */
9731 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
9732 if (kvm_x86_ops->slot_enable_log_dirty)
9733 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
9734 else
9735 kvm_mmu_slot_remove_write_access(kvm, new);
9736 } else {
9737 if (kvm_x86_ops->slot_disable_log_dirty)
9738 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
9739 }
9740}
9741
f7784b8e 9742void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 9743 const struct kvm_userspace_memory_region *mem,
8482644a 9744 const struct kvm_memory_slot *old,
f36f3f28 9745 const struct kvm_memory_slot *new,
8482644a 9746 enum kvm_mr_change change)
f7784b8e 9747{
48c0e4e9 9748 if (!kvm->arch.n_requested_mmu_pages)
4d66623c
WY		 9749 kvm_mmu_change_mmu_pages(kvm,
9750 kvm_mmu_calculate_default_mmu_pages(kvm));
1c91cad4 9751
3ea3b7fa
WL		 9752 /*
9753 * Dirty logging tracks sptes in 4k granularity, meaning that large
9754 * sptes have to be split. If live migration is successful, the guest
9755 * in the source machine will be destroyed and large sptes will be
9756 * created in the destination. However, if the guest continues to run
9757 * in the source machine (for example if live migration fails), small
9758 * sptes will remain around and cause bad performance.
9759 *
9760 * Scan sptes if dirty logging has been stopped, dropping those
9761 * which can be collapsed into a single large-page spte. Later
9762 * page faults will create the large-page sptes.
319109a2
SC		 9763 *
9764 * There is no need to do this in any of the following cases:
9765 * CREATE: No dirty mappings will already exist.
9766 * MOVE/DELETE: The old mappings will already have been cleaned up by
9767 * kvm_arch_flush_shadow_memslot()
3ea3b7fa 9768 */
319109a2 9769 if (change == KVM_MR_FLAGS_ONLY &&
3ea3b7fa
WL		 9770 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
9771 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
9772 kvm_mmu_zap_collapsible_sptes(kvm, new);
9773
c972f3b1 9774 /*
88178fd4 9775 * Set up write protection and/or dirty logging for the new slot.
c126d94f 9776 *
88178fd4
KH		 9777 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
9778 * been zapped so no dirty logging staff is needed for old slot. For
9779 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
9780 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 9781 *
9782 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 9783 */
88178fd4 9784 if (change != KVM_MR_DELETE)
f36f3f28 9785 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 9786}
1d737c8a 9787
2df72e9b 9788void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 9789{
7390de1e 9790 kvm_mmu_zap_all(kvm);
34d4cb8f
MT		 9791}
9792
2df72e9b
MT		 9793void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
9794 struct kvm_memory_slot *slot)
9795{
ae7cd873 9796 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 9797}
9798
e6c67d8c
LA		 9799static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
9800{
9801 return (is_guest_mode(vcpu) &&
9802 kvm_x86_ops->guest_apic_has_interrupt &&
9803 kvm_x86_ops->guest_apic_has_interrupt(vcpu));
9804}
9805
5d9bc648
PB		 9806static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
9807{
9808 if (!list_empty_careful(&vcpu->async_pf.done))
9809 return true;
9810
9811 if (kvm_apic_has_events(vcpu))
9812 return true;
9813
9814 if (vcpu->arch.pv.pv_unhalted)
9815 return true;
9816
a5f01f8e
WL		 9817 if (vcpu->arch.exception.pending)
9818 return true;
9819
47a66eed
Z		 9820 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
9821 (vcpu->arch.nmi_pending &&
9822 kvm_x86_ops->nmi_allowed(vcpu)))
5d9bc648
PB		 9823 return true;
9824
47a66eed
Z		 9825 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
9826 (vcpu->arch.smi_pending && !is_smm(vcpu)))
73917739
PB		 9827 return true;
9828
5d9bc648 9829 if (kvm_arch_interrupt_allowed(vcpu) &&
e6c67d8c
LA		 9830 (kvm_cpu_has_interrupt(vcpu) ||
9831 kvm_guest_apic_has_interrupt(vcpu)))
5d9bc648
PB		 9832 return true;
9833
1f4b34f8
AS		 9834 if (kvm_hv_has_stimer_pending(vcpu))
9835 return true;
9836
5d9bc648
PB		 9837 return false;
9838}
9839
1d737c8a
ZX		 9840int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
9841{
5d9bc648 9842 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 9843}
5736199a 9844
17e433b5
WL		 9845bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu)
9846{
9847 if (READ_ONCE(vcpu->arch.pv.pv_unhalted))
9848 return true;
9849
9850 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
9851 kvm_test_request(KVM_REQ_SMI, vcpu) ||
9852 kvm_test_request(KVM_REQ_EVENT, vcpu))
9853 return true;
9854
9855 if (vcpu->arch.apicv_active && kvm_x86_ops->dy_apicv_has_pending_interrupt(vcpu))
9856 return true;
9857
9858 return false;
9859}
9860
199b5763
LM		 9861bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
9862{
de63ad4c 9863 return vcpu->arch.preempted_in_kernel;
199b5763
LM		 9864}
9865
b6d33834 9866int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 9867{
b6d33834 9868 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 9869}
78646121
GN		 9870
9871int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
9872{
9873 return kvm_x86_ops->interrupt_allowed(vcpu);
9874}
229456fc 9875
82b32774 9876unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 9877{
82b32774
NA		 9878 if (is_64_bit_mode(vcpu))
9879 return kvm_rip_read(vcpu);
9880 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
9881 kvm_rip_read(vcpu));
9882}
9883EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 9884
82b32774
NA		 9885bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
9886{
9887 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 9888}
9889EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
9890
94fe45da
JK		 9891unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
9892{
9893 unsigned long rflags;
9894
9895 rflags = kvm_x86_ops->get_rflags(vcpu);
9896 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 9897 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 9898 return rflags;
9899}
9900EXPORT_SYMBOL_GPL(kvm_get_rflags);
9901
6addfc42 9902static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 9903{
9904 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 9905 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 9906 rflags |= X86_EFLAGS_TF;
94fe45da 9907 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 9908}
9909
9910void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9911{
9912 __kvm_set_rflags(vcpu, rflags);
3842d135 9913 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 9914}
9915EXPORT_SYMBOL_GPL(kvm_set_rflags);
9916
56028d08
GN		 9917void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
9918{
9919 int r;
9920
44dd3ffa 9921 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
f2e10669 9922 work->wakeup_all)
56028d08
GN		 9923 return;
9924
9925 r = kvm_mmu_reload(vcpu);
9926 if (unlikely(r))
9927 return;
9928
44dd3ffa
VK		 9929 if (!vcpu->arch.mmu->direct_map &&
9930 work->arch.cr3 != vcpu->arch.mmu->get_cr3(vcpu))
fb67e14f
XG		 9931 return;
9932
44dd3ffa 9933 vcpu->arch.mmu->page_fault(vcpu, work->gva, 0, true);
56028d08
GN		 9934}
9935
af585b92
GN		 9936static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
9937{
9938 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
9939}
9940
9941static inline u32 kvm_async_pf_next_probe(u32 key)
9942{
9943 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
9944}
9945
9946static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9947{
9948 u32 key = kvm_async_pf_hash_fn(gfn);
9949
9950 while (vcpu->arch.apf.gfns[key] != ~0)
9951 key = kvm_async_pf_next_probe(key);
9952
9953 vcpu->arch.apf.gfns[key] = gfn;
9954}
9955
9956static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
9957{
9958 int i;
9959 u32 key = kvm_async_pf_hash_fn(gfn);
9960
9961 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 9962 (vcpu->arch.apf.gfns[key] != gfn &&
9963 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 9964 key = kvm_async_pf_next_probe(key);
9965
9966 return key;
9967}
9968
9969bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9970{
9971 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
9972}
9973
9974static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9975{
9976 u32 i, j, k;
9977
9978 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
9979 while (true) {
9980 vcpu->arch.apf.gfns[i] = ~0;
9981 do {
9982 j = kvm_async_pf_next_probe(j);
9983 if (vcpu->arch.apf.gfns[j] == ~0)
9984 return;
9985 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
9986 /*
9987 * k lies cyclically in ]i,j]
9988 * | i.k.j |
9989 * |....j i.k.| or |.k..j i...|
9990 */
9991 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
9992 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
9993 i = j;
9994 }
9995}
9996
7c90705b
GN		 9997static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
9998{
4e335d9e
PB		 9999
10000 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
10001 sizeof(val));
7c90705b
GN		 10002}
10003
9a6e7c39
WL		 10004static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
10005{
10006
10007 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
10008 sizeof(u32));
10009}
10010
1dfdb45e
PB		 10011static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu)
10012{
10013 if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu))
10014 return false;
10015
10016 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
10017 (vcpu->arch.apf.send_user_only &&
10018 kvm_x86_ops->get_cpl(vcpu) == 0))
10019 return false;
10020
10021 return true;
10022}
10023
10024bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
10025{
10026 if (unlikely(!lapic_in_kernel(vcpu) ||
10027 kvm_event_needs_reinjection(vcpu) ||
10028 vcpu->arch.exception.pending))
10029 return false;
10030
10031 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu))
10032 return false;
10033
10034 /*
10035 * If interrupts are off we cannot even use an artificial
10036 * halt state.
10037 */
10038 return kvm_x86_ops->interrupt_allowed(vcpu);
10039}
10040
af585b92
GN		 10041void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
10042 struct kvm_async_pf *work)
10043{
6389ee94
AK		 10044 struct x86_exception fault;
10045
7c90705b 10046 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 10047 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b 10048
1dfdb45e
PB		 10049 if (kvm_can_deliver_async_pf(vcpu) &&
10050 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 10051 fault.vector = PF_VECTOR;
10052 fault.error_code_valid = true;
10053 fault.error_code = 0;
10054 fault.nested_page_fault = false;
10055 fault.address = work->arch.token;
adfe20fb 10056 fault.async_page_fault = true;
6389ee94 10057 kvm_inject_page_fault(vcpu, &fault);
1dfdb45e
PB		 10058 } else {
10059 /*
10060 * It is not possible to deliver a paravirtualized asynchronous
10061 * page fault, but putting the guest in an artificial halt state
10062 * can be beneficial nevertheless: if an interrupt arrives, we
10063 * can deliver it timely and perhaps the guest will schedule
10064 * another process. When the instruction that triggered a page
10065 * fault is retried, hopefully the page will be ready in the host.
10066 */
10067 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7c90705b 10068 }
af585b92
GN		 10069}
10070
10071void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
10072 struct kvm_async_pf *work)
10073{
6389ee94 10074 struct x86_exception fault;
9a6e7c39 10075 u32 val;
6389ee94 10076
f2e10669 10077 if (work->wakeup_all)
7c90705b
GN		 10078 work->arch.token = ~0; /* broadcast wakeup */
10079 else
10080 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 10081 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b 10082
9a6e7c39
WL		 10083 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
10084 !apf_get_user(vcpu, &val)) {
10085 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
10086 vcpu->arch.exception.pending &&
10087 vcpu->arch.exception.nr == PF_VECTOR &&
10088 !apf_put_user(vcpu, 0)) {
10089 vcpu->arch.exception.injected = false;
10090 vcpu->arch.exception.pending = false;
10091 vcpu->arch.exception.nr = 0;
10092 vcpu->arch.exception.has_error_code = false;
10093 vcpu->arch.exception.error_code = 0;
c851436a
JM		 10094 vcpu->arch.exception.has_payload = false;
10095 vcpu->arch.exception.payload = 0;
9a6e7c39
WL		 10096 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
10097 fault.vector = PF_VECTOR;
10098 fault.error_code_valid = true;
10099 fault.error_code = 0;
10100 fault.nested_page_fault = false;
10101 fault.address = work->arch.token;
10102 fault.async_page_fault = true;
10103 kvm_inject_page_fault(vcpu, &fault);
10104 }
7c90705b 10105 }
e6d53e3b 10106 vcpu->arch.apf.halted = false;
a4fa1635 10107 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 10108}
10109
10110bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
10111{
10112 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
10113 return true;
10114 else
9bc1f09f 10115 return kvm_can_do_async_pf(vcpu);
af585b92
GN		 10116}
10117
5544eb9b
PB		 10118void kvm_arch_start_assignment(struct kvm *kvm)
10119{
10120 atomic_inc(&kvm->arch.assigned_device_count);
10121}
10122EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
10123
10124void kvm_arch_end_assignment(struct kvm *kvm)
10125{
10126 atomic_dec(&kvm->arch.assigned_device_count);
10127}
10128EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
10129
10130bool kvm_arch_has_assigned_device(struct kvm *kvm)
10131{
10132 return atomic_read(&kvm->arch.assigned_device_count);
10133}
10134EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
10135
e0f0bbc5
AW		 10136void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
10137{
10138 atomic_inc(&kvm->arch.noncoherent_dma_count);
10139}
10140EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
10141
10142void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
10143{
10144 atomic_dec(&kvm->arch.noncoherent_dma_count);
10145}
10146EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
10147
10148bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
10149{
10150 return atomic_read(&kvm->arch.noncoherent_dma_count);
10151}
10152EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
10153
14717e20
AW		 10154bool kvm_arch_has_irq_bypass(void)
10155{
92735b1b 10156 return true;
14717e20
AW		 10157}
10158
87276880
FW		 10159int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
10160 struct irq_bypass_producer *prod)
10161{
10162 struct kvm_kernel_irqfd *irqfd =
10163 container_of(cons, struct kvm_kernel_irqfd, consumer);
10164
14717e20 10165 irqfd->producer = prod;
87276880 10166
14717e20
AW		 10167 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
10168 prod->irq, irqfd->gsi, 1);
87276880
FW		 10169}
10170
10171void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
10172 struct irq_bypass_producer *prod)
10173{
10174 int ret;
10175 struct kvm_kernel_irqfd *irqfd =
10176 container_of(cons, struct kvm_kernel_irqfd, consumer);
10177
87276880
FW		 10178 WARN_ON(irqfd->producer != prod);
10179 irqfd->producer = NULL;
10180
10181 /*
10182 * When producer of consumer is unregistered, we change back to
10183 * remapped mode, so we can re-use the current implementation
bb3541f1 10184 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 10185 * int this case doesn't want to receive the interrupts.
10186 */
10187 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
10188 if (ret)
10189 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
10190 " fails: %d\n", irqfd->consumer.token, ret);
10191}
10192
10193int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
10194 uint32_t guest_irq, bool set)
10195{
87276880
FW		 10196 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
10197}
10198
52004014
FW		 10199bool kvm_vector_hashing_enabled(void)
10200{
10201 return vector_hashing;
10202}
10203EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
10204
2d5ba19b
MT		 10205bool kvm_arch_no_poll(struct kvm_vcpu *vcpu)
10206{
10207 return (vcpu->arch.msr_kvm_poll_control & 1) == 0;
10208}
10209EXPORT_SYMBOL_GPL(kvm_arch_no_poll);
10210
10211
229456fc 10212EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 10213EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 10214EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
10215EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
10216EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
10217EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 10218EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 10219EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 10220EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 10221EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
5497b955 10222EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed);
ec1ff790 10223EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 10224EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 10225EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 10226EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
4f75bcc3 10227EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update);
843e4330 10228EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 10229EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 10230EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
10231EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
Linux 6.x block layer and io_uring tree(s)