[linux-2.6-block.git] / arch / x86 / include / uapi / asm / kvm.h

#ifndef _ASM_X86_KVM_H
#define _ASM_X86_KVM_H

/*
 * KVM x86 specific structures and definitions
 *
 */

#include <linux/types.h>
#include <linux/ioctl.h>

#define DE_VECTOR 0
#define DB_VECTOR 1
#define BP_VECTOR 3
#define OF_VECTOR 4
#define BR_VECTOR 5
#define UD_VECTOR 6
#define NM_VECTOR 7
#define DF_VECTOR 8
#define TS_VECTOR 10
#define NP_VECTOR 11
#define SS_VECTOR 12
#define GP_VECTOR 13
#define PF_VECTOR 14
#define MF_VECTOR 16
#define AC_VECTOR 17
#define MC_VECTOR 18
#define XM_VECTOR 19
#define VE_VECTOR 20

/* Select x86 specific features in <linux/kvm.h> */
#define __KVM_HAVE_PIT
#define __KVM_HAVE_IOAPIC
#define __KVM_HAVE_IRQ_LINE
#define __KVM_HAVE_MSI
#define __KVM_HAVE_USER_NMI
#define __KVM_HAVE_GUEST_DEBUG
#define __KVM_HAVE_MSIX
#define __KVM_HAVE_MCE
#define __KVM_HAVE_PIT_STATE2
#define __KVM_HAVE_XEN_HVM
#define __KVM_HAVE_VCPU_EVENTS
#define __KVM_HAVE_DEBUGREGS
#define __KVM_HAVE_XSAVE
#define __KVM_HAVE_XCRS
#define __KVM_HAVE_READONLY_MEM

/* Architectural interrupt line count. */
#define KVM_NR_INTERRUPTS 256

struct kvm_memory_alias {
	__u32 slot;  /* this has a different namespace than memory slots */
	__u32 flags;
	__u64 guest_phys_addr;
	__u64 memory_size;
	__u64 target_phys_addr;
};

/* for KVM_GET_IRQCHIP and KVM_SET_IRQCHIP */
struct kvm_pic_state {
	__u8 last_irr;	/* edge detection */
	__u8 irr;		/* interrupt request register */
	__u8 imr;		/* interrupt mask register */
	__u8 isr;		/* interrupt service register */
	__u8 priority_add;	/* highest irq priority */
	__u8 irq_base;
	__u8 read_reg_select;
	__u8 poll;
	__u8 special_mask;
	__u8 init_state;
	__u8 auto_eoi;
	__u8 rotate_on_auto_eoi;
	__u8 special_fully_nested_mode;
	__u8 init4;		/* true if 4 byte init */
	__u8 elcr;		/* PIIX edge/trigger selection */
	__u8 elcr_mask;
};

#define KVM_IOAPIC_NUM_PINS  24
struct kvm_ioapic_state {
	__u64 base_address;
	__u32 ioregsel;
	__u32 id;
	__u32 irr;
	__u32 pad;
	union {
		__u64 bits;
		struct {
			__u8 vector;
			__u8 delivery_mode:3;
			__u8 dest_mode:1;
			__u8 delivery_status:1;
			__u8 polarity:1;
			__u8 remote_irr:1;
			__u8 trig_mode:1;
			__u8 mask:1;
			__u8 reserve:7;
			__u8 reserved[4];
			__u8 dest_id;
		} fields;
	} redirtbl[KVM_IOAPIC_NUM_PINS];
};

#define KVM_IRQCHIP_PIC_MASTER   0
#define KVM_IRQCHIP_PIC_SLAVE    1
#define KVM_IRQCHIP_IOAPIC       2
#define KVM_NR_IRQCHIPS          3

#define KVM_RUN_X86_SMM		 (1 << 0)

/* for KVM_GET_REGS and KVM_SET_REGS */
struct kvm_regs {
	/* out (KVM_GET_REGS) / in (KVM_SET_REGS) */
	__u64 rax, rbx, rcx, rdx;
	__u64 rsi, rdi, rsp, rbp;
	__u64 r8,  r9,  r10, r11;
	__u64 r12, r13, r14, r15;
	__u64 rip, rflags;
};

/* for KVM_GET_LAPIC and KVM_SET_LAPIC */
#define KVM_APIC_REG_SIZE 0x400
struct kvm_lapic_state {
	char regs[KVM_APIC_REG_SIZE];
};

struct kvm_segment {
	__u64 base;
	__u32 limit;
	__u16 selector;
	__u8  type;
	__u8  present, dpl, db, s, l, g, avl;
	__u8  unusable;
	__u8  padding;
};

struct kvm_dtable {
	__u64 base;
	__u16 limit;
	__u16 padding[3];
};


/* for KVM_GET_SREGS and KVM_SET_SREGS */
struct kvm_sregs {
	/* out (KVM_GET_SREGS) / in (KVM_SET_SREGS) */
	struct kvm_segment cs, ds, es, fs, gs, ss;
	struct kvm_segment tr, ldt;
	struct kvm_dtable gdt, idt;
	__u64 cr0, cr2, cr3, cr4, cr8;
	__u64 efer;
	__u64 apic_base;
	__u64 interrupt_bitmap[(KVM_NR_INTERRUPTS + 63) / 64];
};

/* for KVM_GET_FPU and KVM_SET_FPU */
struct kvm_fpu {
	__u8  fpr[8][16];
	__u16 fcw;
	__u16 fsw;
	__u8  ftwx;  /* in fxsave format */
	__u8  pad1;
	__u16 last_opcode;
	__u64 last_ip;
	__u64 last_dp;
	__u8  xmm[16][16];
	__u32 mxcsr;
	__u32 pad2;
};

struct kvm_msr_entry {
	__u32 index;
	__u32 reserved;
	__u64 data;
};

/* for KVM_GET_MSRS and KVM_SET_MSRS */
struct kvm_msrs {
	__u32 nmsrs; /* number of msrs in entries */
	__u32 pad;

	struct kvm_msr_entry entries[0];
};

/* for KVM_GET_MSR_INDEX_LIST */
struct kvm_msr_list {
	__u32 nmsrs; /* number of msrs in entries */
	__u32 indices[0];
};


struct kvm_cpuid_entry {
	__u32 function;
	__u32 eax;
	__u32 ebx;
	__u32 ecx;
	__u32 edx;
	__u32 padding;
};

/* for KVM_SET_CPUID */
struct kvm_cpuid {
	__u32 nent;
	__u32 padding;
	struct kvm_cpuid_entry entries[0];
};

struct kvm_cpuid_entry2 {
	__u32 function;
	__u32 index;
	__u32 flags;
	__u32 eax;
	__u32 ebx;
	__u32 ecx;
	__u32 edx;
	__u32 padding[3];
};

#define KVM_CPUID_FLAG_SIGNIFCANT_INDEX		BIT(0)
#define KVM_CPUID_FLAG_STATEFUL_FUNC		BIT(1)
#define KVM_CPUID_FLAG_STATE_READ_NEXT		BIT(2)

/* for KVM_SET_CPUID2 */
struct kvm_cpuid2 {
	__u32 nent;
	__u32 padding;
	struct kvm_cpuid_entry2 entries[0];
};

/* for KVM_GET_PIT and KVM_SET_PIT */
struct kvm_pit_channel_state {
	__u32 count; /* can be 65536 */
	__u16 latched_count;
	__u8 count_latched;
	__u8 status_latched;
	__u8 status;
	__u8 read_state;
	__u8 write_state;
	__u8 write_latch;
	__u8 rw_mode;
	__u8 mode;
	__u8 bcd;
	__u8 gate;
	__s64 count_load_time;
};

struct kvm_debug_exit_arch {
	__u32 exception;
	__u32 pad;
	__u64 pc;
	__u64 dr6;
	__u64 dr7;
};

#define KVM_GUESTDBG_USE_SW_BP		0x00010000
#define KVM_GUESTDBG_USE_HW_BP		0x00020000
#define KVM_GUESTDBG_INJECT_DB		0x00040000
#define KVM_GUESTDBG_INJECT_BP		0x00080000

/* for KVM_SET_GUEST_DEBUG */
struct kvm_guest_debug_arch {
	__u64 debugreg[8];
};

struct kvm_pit_state {
	struct kvm_pit_channel_state channels[3];
};

#define KVM_PIT_FLAGS_HPET_LEGACY  0x00000001

struct kvm_pit_state2 {
	struct kvm_pit_channel_state channels[3];
	__u32 flags;
	__u32 reserved[9];
};

struct kvm_reinject_control {
	__u8 pit_reinject;
	__u8 reserved[31];
};

/* When set in flags, include corresponding fields on KVM_SET_VCPU_EVENTS */
#define KVM_VCPUEVENT_VALID_NMI_PENDING	0x00000001
#define KVM_VCPUEVENT_VALID_SIPI_VECTOR	0x00000002
#define KVM_VCPUEVENT_VALID_SHADOW	0x00000004
#define KVM_VCPUEVENT_VALID_SMM		0x00000008

/* Interrupt shadow states */
#define KVM_X86_SHADOW_INT_MOV_SS	0x01
#define KVM_X86_SHADOW_INT_STI		0x02

/* for KVM_GET/SET_VCPU_EVENTS */
struct kvm_vcpu_events {
	struct {
		__u8 injected;
		__u8 nr;
		__u8 has_error_code;
		__u8 pad;
		__u32 error_code;
	} exception;
	struct {
		__u8 injected;
		__u8 nr;
		__u8 soft;
		__u8 shadow;
	} interrupt;
	struct {
		__u8 injected;
		__u8 pending;
		__u8 masked;
		__u8 pad;
	} nmi;
	__u32 sipi_vector;
	__u32 flags;
	struct {
		__u8 smm;
		__u8 pending;
		__u8 smm_inside_nmi;
		__u8 latched_init;
	} smi;
	__u32 reserved[9];
};

/* for KVM_GET/SET_DEBUGREGS */
struct kvm_debugregs {
	__u64 db[4];
	__u64 dr6;
	__u64 dr7;
	__u64 flags;
	__u64 reserved[9];
};

/* for KVM_CAP_XSAVE */
struct kvm_xsave {
	__u32 region[1024];
};

#define KVM_MAX_XCRS	16

struct kvm_xcr {
	__u32 xcr;
	__u32 reserved;
	__u64 value;
};

struct kvm_xcrs {
	__u32 nr_xcrs;
	__u32 flags;
	struct kvm_xcr xcrs[KVM_MAX_XCRS];
	__u64 padding[16];
};

/* definition of registers in kvm_run */
struct kvm_sync_regs {
};

#define KVM_X86_QUIRK_LINT0_REENABLED	(1 << 0)
#define KVM_X86_QUIRK_CD_NW_CLEARED	(1 << 1)

#endif /* _ASM_X86_KVM_H */
Commit	Line	Data
1965aae3 PA	1	#ifndef _ASM_X86_KVM_H
1965aae3 PA	2	#define _ASM_X86_KVM_H
f6a40e3b JY	3
	4	/*
	5	* KVM x86 specific structures and definitions
	6	*
	7	*/
	8
cef37678	9	#include <linux/types.h>
f6a40e3b JY	10	#include <linux/ioctl.h>
f6a40e3b JY	11
26bf264e XG	12	#define DE_VECTOR 0
	13	#define DB_VECTOR 1
	14	#define BP_VECTOR 3
	15	#define OF_VECTOR 4
	16	#define BR_VECTOR 5
	17	#define UD_VECTOR 6
	18	#define NM_VECTOR 7
	19	#define DF_VECTOR 8
	20	#define TS_VECTOR 10
	21	#define NP_VECTOR 11
	22	#define SS_VECTOR 12
	23	#define GP_VECTOR 13
	24	#define PF_VECTOR 14
	25	#define MF_VECTOR 16
c9cdd085	26	#define AC_VECTOR 17
26bf264e	27	#define MC_VECTOR 18
c9cdd085 NA	28	#define XM_VECTOR 19
c9cdd085 NA	29	#define VE_VECTOR 20
26bf264e	30
7a0eb196 AK	31	/* Select x86 specific features in <linux/kvm.h> */
	32	#define __KVM_HAVE_PIT
	33	#define __KVM_HAVE_IOAPIC
a1e4ccb9	34	#define __KVM_HAVE_IRQ_LINE
7a0eb196 AK	35	#define __KVM_HAVE_MSI
7a0eb196 AK	36	#define __KVM_HAVE_USER_NMI
91b2ae77	37	#define __KVM_HAVE_GUEST_DEBUG
d510d6cc	38	#define __KVM_HAVE_MSIX
890ca9ae	39	#define __KVM_HAVE_MCE
e9f42757	40	#define __KVM_HAVE_PIT_STATE2
ffde22ac	41	#define __KVM_HAVE_XEN_HVM
3cfc3092	42	#define __KVM_HAVE_VCPU_EVENTS
a1efbe77	43	#define __KVM_HAVE_DEBUGREGS
2d5b5a66 SY	44	#define __KVM_HAVE_XSAVE
2d5b5a66 SY	45	#define __KVM_HAVE_XCRS
4d8b81ab	46	#define __KVM_HAVE_READONLY_MEM
7a0eb196	47
244d57ec JY	48	/* Architectural interrupt line count. */
	49	#define KVM_NR_INTERRUPTS 256
	50
f6a40e3b JY	51	struct kvm_memory_alias {
	52	__u32 slot; /* this has a different namespace than memory slots */
	53	__u32 flags;
	54	__u64 guest_phys_addr;
	55	__u64 memory_size;
	56	__u64 target_phys_addr;
	57	};
	58
da1386a5 JY	59	/* for KVM_GET_IRQCHIP and KVM_SET_IRQCHIP */
	60	struct kvm_pic_state {
	61	__u8 last_irr; /* edge detection */
	62	__u8 irr; /* interrupt request register */
	63	__u8 imr; /* interrupt mask register */
	64	__u8 isr; /* interrupt service register */
	65	__u8 priority_add; /* highest irq priority */
	66	__u8 irq_base;
	67	__u8 read_reg_select;
	68	__u8 poll;
	69	__u8 special_mask;
	70	__u8 init_state;
	71	__u8 auto_eoi;
	72	__u8 rotate_on_auto_eoi;
	73	__u8 special_fully_nested_mode;
	74	__u8 init4; /* true if 4 byte init */
	75	__u8 elcr; /* PIIX edge/trigger selection */
	76	__u8 elcr_mask;
	77	};
	78
	79	#define KVM_IOAPIC_NUM_PINS 24
	80	struct kvm_ioapic_state {
	81	__u64 base_address;
	82	__u32 ioregsel;
	83	__u32 id;
	84	__u32 irr;
	85	__u32 pad;
	86	union {
	87	__u64 bits;
	88	struct {
	89	__u8 vector;
	90	__u8 delivery_mode:3;
	91	__u8 dest_mode:1;
	92	__u8 delivery_status:1;
	93	__u8 polarity:1;
	94	__u8 remote_irr:1;
	95	__u8 trig_mode:1;
	96	__u8 mask:1;
	97	__u8 reserve:7;
	98	__u8 reserved[4];
	99	__u8 dest_id;
	100	} fields;
	101	} redirtbl[KVM_IOAPIC_NUM_PINS];
	102	};
	103
	104	#define KVM_IRQCHIP_PIC_MASTER 0
	105	#define KVM_IRQCHIP_PIC_SLAVE 1
	106	#define KVM_IRQCHIP_IOAPIC 2
3e71f88b	107	#define KVM_NR_IRQCHIPS 3
da1386a5	108
f077825a PB	109	#define KVM_RUN_X86_SMM (1 << 0)
f077825a PB	110
19d30b16 JY	111	/* for KVM_GET_REGS and KVM_SET_REGS */
	112	struct kvm_regs {
	113	/* out (KVM_GET_REGS) / in (KVM_SET_REGS) */
	114	__u64 rax, rbx, rcx, rdx;
	115	__u64 rsi, rdi, rsp, rbp;
	116	__u64 r8, r9, r10, r11;
	117	__u64 r12, r13, r14, r15;
	118	__u64 rip, rflags;
	119	};
	120
d9ecf928 JY	121	/* for KVM_GET_LAPIC and KVM_SET_LAPIC */
	122	#define KVM_APIC_REG_SIZE 0x400
	123	struct kvm_lapic_state {
	124	char regs[KVM_APIC_REG_SIZE];
	125	};
	126
3a56b201 JY	127	struct kvm_segment {
	128	__u64 base;
	129	__u32 limit;
	130	__u16 selector;
	131	__u8 type;
	132	__u8 present, dpl, db, s, l, g, avl;
	133	__u8 unusable;
	134	__u8 padding;
	135	};
	136
	137	struct kvm_dtable {
	138	__u64 base;
	139	__u16 limit;
	140	__u16 padding[3];
	141	};
	142
	143
244d57ec JY	144	/* for KVM_GET_SREGS and KVM_SET_SREGS */
	145	struct kvm_sregs {
	146	/* out (KVM_GET_SREGS) / in (KVM_SET_SREGS) */
	147	struct kvm_segment cs, ds, es, fs, gs, ss;
	148	struct kvm_segment tr, ldt;
	149	struct kvm_dtable gdt, idt;
	150	__u64 cr0, cr2, cr3, cr4, cr8;
	151	__u64 efer;
	152	__u64 apic_base;
	153	__u64 interrupt_bitmap[(KVM_NR_INTERRUPTS + 63) / 64];
	154	};
	155
6f723c79 CE	156	/* for KVM_GET_FPU and KVM_SET_FPU */
	157	struct kvm_fpu {
	158	__u8 fpr[8][16];
	159	__u16 fcw;
	160	__u16 fsw;
	161	__u8 ftwx; /* in fxsave format */
	162	__u8 pad1;
	163	__u16 last_opcode;
	164	__u64 last_ip;
	165	__u64 last_dp;
	166	__u8 xmm[16][16];
	167	__u32 mxcsr;
	168	__u32 pad2;
	169	};
	170
244d57ec JY	171	struct kvm_msr_entry {
	172	__u32 index;
	173	__u32 reserved;
	174	__u64 data;
	175	};
	176
	177	/* for KVM_GET_MSRS and KVM_SET_MSRS */
	178	struct kvm_msrs {
	179	__u32 nmsrs; /* number of msrs in entries */
	180	__u32 pad;
	181
	182	struct kvm_msr_entry entries[0];
	183	};
	184
	185	/* for KVM_GET_MSR_INDEX_LIST */
	186	struct kvm_msr_list {
	187	__u32 nmsrs; /* number of msrs in entries */
	188	__u32 indices[0];
	189	};
	190
	191
a162dd58 JY	192	struct kvm_cpuid_entry {
	193	__u32 function;
	194	__u32 eax;
	195	__u32 ebx;
	196	__u32 ecx;
	197	__u32 edx;
	198	__u32 padding;
	199	};
	200
	201	/* for KVM_SET_CPUID */
	202	struct kvm_cpuid {
	203	__u32 nent;
	204	__u32 padding;
	205	struct kvm_cpuid_entry entries[0];
	206	};
	207
07716717 DK	208	struct kvm_cpuid_entry2 {
	209	__u32 function;
	210	__u32 index;
	211	__u32 flags;
	212	__u32 eax;
	213	__u32 ebx;
	214	__u32 ecx;
	215	__u32 edx;
	216	__u32 padding[3];
	217	};
	218
9c15bb1d BP	219	#define KVM_CPUID_FLAG_SIGNIFCANT_INDEX BIT(0)
	220	#define KVM_CPUID_FLAG_STATEFUL_FUNC BIT(1)
	221	#define KVM_CPUID_FLAG_STATE_READ_NEXT BIT(2)
07716717 DK	222
	223	/* for KVM_SET_CPUID2 */
	224	struct kvm_cpuid2 {
	225	__u32 nent;
	226	__u32 padding;
	227	struct kvm_cpuid_entry2 entries[0];
	228	};
a162dd58	229
e0f63cb9 SY	230	/* for KVM_GET_PIT and KVM_SET_PIT */
	231	struct kvm_pit_channel_state {
	232	__u32 count; /* can be 65536 */
	233	__u16 latched_count;
	234	__u8 count_latched;
	235	__u8 status_latched;
	236	__u8 status;
	237	__u8 read_state;
	238	__u8 write_state;
	239	__u8 write_latch;
	240	__u8 rw_mode;
	241	__u8 mode;
	242	__u8 bcd;
	243	__u8 gate;
	244	__s64 count_load_time;
	245	};
	246
d0bfb940 JK	247	struct kvm_debug_exit_arch {
	248	__u32 exception;
	249	__u32 pad;
	250	__u64 pc;
	251	__u64 dr6;
	252	__u64 dr7;
	253	};
	254
	255	#define KVM_GUESTDBG_USE_SW_BP 0x00010000
	256	#define KVM_GUESTDBG_USE_HW_BP 0x00020000
	257	#define KVM_GUESTDBG_INJECT_DB 0x00040000
	258	#define KVM_GUESTDBG_INJECT_BP 0x00080000
	259
	260	/* for KVM_SET_GUEST_DEBUG */
	261	struct kvm_guest_debug_arch {
	262	__u64 debugreg[8];
	263	};
	264
e0f63cb9 SY	265	struct kvm_pit_state {
	266	struct kvm_pit_channel_state channels[3];
	267	};
52d939a0	268
e9f42757 BK	269	#define KVM_PIT_FLAGS_HPET_LEGACY 0x00000001
	270
	271	struct kvm_pit_state2 {
	272	struct kvm_pit_channel_state channels[3];
	273	__u32 flags;
	274	__u32 reserved[9];
	275	};
	276
52d939a0 MT	277	struct kvm_reinject_control {
	278	__u8 pit_reinject;
	279	__u8 reserved[31];
	280	};
3cfc3092	281
dab4b911 JK	282	/* When set in flags, include corresponding fields on KVM_SET_VCPU_EVENTS */
	283	#define KVM_VCPUEVENT_VALID_NMI_PENDING 0x00000001
	284	#define KVM_VCPUEVENT_VALID_SIPI_VECTOR 0x00000002
48005f64	285	#define KVM_VCPUEVENT_VALID_SHADOW 0x00000004
f077825a	286	#define KVM_VCPUEVENT_VALID_SMM 0x00000008
48005f64 JK	287
	288	/* Interrupt shadow states */
	289	#define KVM_X86_SHADOW_INT_MOV_SS 0x01
	290	#define KVM_X86_SHADOW_INT_STI 0x02
dab4b911	291
3cfc3092 JK	292	/* for KVM_GET/SET_VCPU_EVENTS */
	293	struct kvm_vcpu_events {
	294	struct {
	295	__u8 injected;
	296	__u8 nr;
	297	__u8 has_error_code;
	298	__u8 pad;
	299	__u32 error_code;
	300	} exception;
	301	struct {
	302	__u8 injected;
	303	__u8 nr;
	304	__u8 soft;
48005f64	305	__u8 shadow;
3cfc3092 JK	306	} interrupt;
	307	struct {
	308	__u8 injected;
	309	__u8 pending;
	310	__u8 masked;
	311	__u8 pad;
	312	} nmi;
	313	__u32 sipi_vector;
	314	__u32 flags;
f077825a PB	315	struct {
	316	__u8 smm;
	317	__u8 pending;
	318	__u8 smm_inside_nmi;
	319	__u8 latched_init;
	320	} smi;
	321	__u32 reserved[9];
3cfc3092 JK	322	};
3cfc3092 JK	323
a1efbe77 JK	324	/* for KVM_GET/SET_DEBUGREGS */
	325	struct kvm_debugregs {
	326	__u64 db[4];
	327	__u64 dr6;
	328	__u64 dr7;
	329	__u64 flags;
	330	__u64 reserved[9];
	331	};
	332
2d5b5a66 SY	333	/* for KVM_CAP_XSAVE */
	334	struct kvm_xsave {
	335	__u32 region[1024];
	336	};
	337
	338	#define KVM_MAX_XCRS 16
	339
	340	struct kvm_xcr {
	341	__u32 xcr;
	342	__u32 reserved;
	343	__u64 value;
	344	};
	345
	346	struct kvm_xcrs {
	347	__u32 nr_xcrs;
	348	__u32 flags;
	349	struct kvm_xcr xcrs[KVM_MAX_XCRS];
	350	__u64 padding[16];
	351	};
	352
b9e5dc8d CB	353	/* definition of registers in kvm_run */
	354	struct kvm_sync_regs {
	355	};
	356
0da029ed PB	357	#define KVM_X86_QUIRK_LINT0_REENABLED (1 << 0)
0da029ed PB	358	#define KVM_X86_QUIRK_CD_NW_CLEARED (1 << 1)
90de4a18	359
1965aae3	360	#endif /* _ASM_X86_KVM_H */