Commit | Line | Data |
---|---|---|
b00dc837 | 1 | /* |
1da177e4 LT |
2 | * VISsave.S: Code for saving FPU register state for |
3 | * VIS routines. One should not call this directly, | |
4 | * but use macros provided in <asm/visasm.h>. | |
5 | * | |
6 | * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz) | |
7 | */ | |
8 | ||
9 | #include <asm/asi.h> | |
10 | #include <asm/page.h> | |
11 | #include <asm/ptrace.h> | |
12 | #include <asm/visasm.h> | |
13 | #include <asm/thread_info.h> | |
14 | ||
15 | .text | |
16 | .globl VISenter, VISenterhalf | |
17 | ||
18 | /* On entry: %o5=current FPRS value, %g7 is callers address */ | |
19 | /* May clobber %o5, %g1, %g2, %g3, %g7, %icc, %xcc */ | |
20 | ||
21 | /* Nothing special need be done here to handle pre-emption, this | |
22 | * FPU save/restore mechanism is already preemption safe. | |
23 | */ | |
24 | ||
25 | .align 32 | |
26 | VISenter: | |
27 | ldub [%g6 + TI_FPDEPTH], %g1 | |
28 | brnz,a,pn %g1, 1f | |
29 | cmp %g1, 1 | |
30 | stb %g0, [%g6 + TI_FPSAVED] | |
31 | stx %fsr, [%g6 + TI_XFSR] | |
32 | 9: jmpl %g7 + %g0, %g0 | |
33 | nop | |
34 | 1: bne,pn %icc, 2f | |
35 | ||
36 | srl %g1, 1, %g1 | |
37 | vis1: ldub [%g6 + TI_FPSAVED], %g3 | |
38 | stx %fsr, [%g6 + TI_XFSR] | |
39 | or %g3, %o5, %g3 | |
40 | stb %g3, [%g6 + TI_FPSAVED] | |
41 | rd %gsr, %g3 | |
42 | clr %g1 | |
43 | ba,pt %xcc, 3f | |
44 | ||
45 | stx %g3, [%g6 + TI_GSR] | |
46 | 2: add %g6, %g1, %g3 | |
44922150 DM |
47 | mov FPRS_DU | FPRS_DL | FPRS_FEF, %o5 |
48 | sll %g1, 3, %g1 | |
1da177e4 LT |
49 | stb %o5, [%g3 + TI_FPSAVED] |
50 | rd %gsr, %g2 | |
51 | add %g6, %g1, %g3 | |
52 | stx %g2, [%g3 + TI_GSR] | |
53 | ||
54 | add %g6, %g1, %g2 | |
55 | stx %fsr, [%g2 + TI_XFSR] | |
56 | sll %g1, 5, %g1 | |
57 | 3: andcc %o5, FPRS_DL|FPRS_DU, %g0 | |
58 | be,pn %icc, 9b | |
59 | add %g6, TI_FPREGS, %g2 | |
60 | andcc %o5, FPRS_DL, %g0 | |
1da177e4 LT |
61 | |
62 | be,pn %icc, 4f | |
63 | add %g6, TI_FPREGS+0x40, %g3 | |
ba639933 | 64 | membar #Sync |
1da177e4 LT |
65 | stda %f0, [%g2 + %g1] ASI_BLK_P |
66 | stda %f16, [%g3 + %g1] ASI_BLK_P | |
ba639933 | 67 | membar #Sync |
1da177e4 LT |
68 | andcc %o5, FPRS_DU, %g0 |
69 | be,pn %icc, 5f | |
70 | 4: add %g1, 128, %g1 | |
ba639933 | 71 | membar #Sync |
1da177e4 LT |
72 | stda %f32, [%g2 + %g1] ASI_BLK_P |
73 | ||
74 | stda %f48, [%g3 + %g1] ASI_BLK_P | |
75 | 5: membar #Sync | |
b445e26c DM |
76 | ba,pt %xcc, 80f |
77 | nop | |
78 | ||
79 | .align 32 | |
80 | 80: jmpl %g7 + %g0, %g0 | |
1da177e4 | 81 | nop |