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1 | /* |
2 | * SH5-101/SH5-103 CPU Setup | |
3 | * | |
4 | * Copyright (C) 2009 Paul Mundt | |
5 | * | |
6 | * This file is subject to the terms and conditions of the GNU General Public | |
7 | * License. See the file "COPYING" in the main directory of this archive | |
8 | * for more details. | |
9 | */ | |
10 | #include <linux/platform_device.h> | |
11 | #include <linux/init.h> | |
12 | #include <linux/serial.h> | |
13 | #include <linux/serial_sci.h> | |
14 | #include <linux/io.h> | |
15 | #include <linux/mm.h> | |
add47067 | 16 | #include <linux/sh_timer.h> |
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17 | #include <asm/addrspace.h> |
18 | ||
d8d3fbb0 MD |
19 | static struct plat_sci_port scif0_platform_data = { |
20 | .mapbase = PHYS_PERIPHERAL_BLOCK + 0x01030000, | |
21 | .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, | |
22 | .type = PORT_SCIF, | |
23 | .irqs = { 39, 40, 42, 0 }, | |
0fb849b9 PM |
24 | }; |
25 | ||
d8d3fbb0 | 26 | static struct platform_device scif0_device = { |
0fb849b9 | 27 | .name = "sh-sci", |
d8d3fbb0 | 28 | .id = 0, |
0fb849b9 | 29 | .dev = { |
d8d3fbb0 | 30 | .platform_data = &scif0_platform_data, |
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31 | }, |
32 | }; | |
33 | ||
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34 | static struct resource rtc_resources[] = { |
35 | [0] = { | |
36 | .start = PHYS_PERIPHERAL_BLOCK + 0x01040000, | |
37 | .end = PHYS_PERIPHERAL_BLOCK + 0x01040000 + 0x58 - 1, | |
38 | .flags = IORESOURCE_IO, | |
39 | }, | |
40 | [1] = { | |
41 | /* Period IRQ */ | |
42 | .start = IRQ_PRI, | |
43 | .flags = IORESOURCE_IRQ, | |
44 | }, | |
45 | [2] = { | |
46 | /* Carry IRQ */ | |
47 | .start = IRQ_CUI, | |
48 | .flags = IORESOURCE_IRQ, | |
49 | }, | |
50 | [3] = { | |
51 | /* Alarm IRQ */ | |
52 | .start = IRQ_ATI, | |
53 | .flags = IORESOURCE_IRQ, | |
54 | }, | |
55 | }; | |
56 | ||
57 | static struct platform_device rtc_device = { | |
58 | .name = "sh-rtc", | |
59 | .id = -1, | |
60 | .num_resources = ARRAY_SIZE(rtc_resources), | |
61 | .resource = rtc_resources, | |
62 | }; | |
63 | ||
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64 | #define TMU_BLOCK_OFF 0x01020000 |
65 | #define TMU_BASE PHYS_PERIPHERAL_BLOCK + TMU_BLOCK_OFF | |
66 | #define TMU0_BASE (TMU_BASE + 0x8 + (0xc * 0x0)) | |
67 | #define TMU1_BASE (TMU_BASE + 0x8 + (0xc * 0x1)) | |
68 | #define TMU2_BASE (TMU_BASE + 0x8 + (0xc * 0x2)) | |
69 | ||
70 | static struct sh_timer_config tmu0_platform_data = { | |
add47067 PM |
71 | .channel_offset = 0x04, |
72 | .timer_bit = 0, | |
add47067 PM |
73 | .clockevent_rating = 200, |
74 | }; | |
75 | ||
76 | static struct resource tmu0_resources[] = { | |
77 | [0] = { | |
add47067 PM |
78 | .start = TMU0_BASE, |
79 | .end = TMU0_BASE + 0xc - 1, | |
80 | .flags = IORESOURCE_MEM, | |
81 | }, | |
82 | [1] = { | |
83 | .start = IRQ_TUNI0, | |
84 | .flags = IORESOURCE_IRQ, | |
85 | }, | |
86 | }; | |
87 | ||
88 | static struct platform_device tmu0_device = { | |
89 | .name = "sh_tmu", | |
90 | .id = 0, | |
91 | .dev = { | |
92 | .platform_data = &tmu0_platform_data, | |
93 | }, | |
94 | .resource = tmu0_resources, | |
95 | .num_resources = ARRAY_SIZE(tmu0_resources), | |
96 | }; | |
97 | ||
98 | static struct sh_timer_config tmu1_platform_data = { | |
add47067 PM |
99 | .channel_offset = 0x10, |
100 | .timer_bit = 1, | |
add47067 PM |
101 | .clocksource_rating = 200, |
102 | }; | |
103 | ||
104 | static struct resource tmu1_resources[] = { | |
105 | [0] = { | |
add47067 PM |
106 | .start = TMU1_BASE, |
107 | .end = TMU1_BASE + 0xc - 1, | |
108 | .flags = IORESOURCE_MEM, | |
109 | }, | |
110 | [1] = { | |
111 | .start = IRQ_TUNI1, | |
112 | .flags = IORESOURCE_IRQ, | |
113 | }, | |
114 | }; | |
115 | ||
116 | static struct platform_device tmu1_device = { | |
117 | .name = "sh_tmu", | |
118 | .id = 1, | |
119 | .dev = { | |
120 | .platform_data = &tmu1_platform_data, | |
121 | }, | |
122 | .resource = tmu1_resources, | |
123 | .num_resources = ARRAY_SIZE(tmu1_resources), | |
124 | }; | |
125 | ||
126 | static struct sh_timer_config tmu2_platform_data = { | |
add47067 PM |
127 | .channel_offset = 0x1c, |
128 | .timer_bit = 2, | |
add47067 PM |
129 | }; |
130 | ||
131 | static struct resource tmu2_resources[] = { | |
132 | [0] = { | |
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133 | .start = TMU2_BASE, |
134 | .end = TMU2_BASE + 0xc - 1, | |
135 | .flags = IORESOURCE_MEM, | |
136 | }, | |
137 | [1] = { | |
138 | .start = IRQ_TUNI2, | |
139 | .flags = IORESOURCE_IRQ, | |
140 | }, | |
141 | }; | |
142 | ||
143 | static struct platform_device tmu2_device = { | |
144 | .name = "sh_tmu", | |
145 | .id = 2, | |
146 | .dev = { | |
147 | .platform_data = &tmu2_platform_data, | |
148 | }, | |
149 | .resource = tmu2_resources, | |
150 | .num_resources = ARRAY_SIZE(tmu2_resources), | |
151 | }; | |
152 | ||
153 | static struct platform_device *sh5_early_devices[] __initdata = { | |
d8d3fbb0 | 154 | &scif0_device, |
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155 | &tmu0_device, |
156 | &tmu1_device, | |
157 | &tmu2_device, | |
158 | }; | |
159 | ||
0fb849b9 | 160 | static struct platform_device *sh5_devices[] __initdata = { |
c2ecb4c4 | 161 | &rtc_device, |
0fb849b9 PM |
162 | }; |
163 | ||
164 | static int __init sh5_devices_setup(void) | |
165 | { | |
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166 | int ret; |
167 | ||
168 | ret = platform_add_devices(sh5_early_devices, | |
169 | ARRAY_SIZE(sh5_early_devices)); | |
170 | if (unlikely(ret != 0)) | |
171 | return ret; | |
172 | ||
0fb849b9 PM |
173 | return platform_add_devices(sh5_devices, |
174 | ARRAY_SIZE(sh5_devices)); | |
175 | } | |
ba9a6337 | 176 | arch_initcall(sh5_devices_setup); |
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177 | |
178 | void __init plat_early_device_setup(void) | |
179 | { | |
180 | early_platform_add_devices(sh5_early_devices, | |
181 | ARRAY_SIZE(sh5_early_devices)); | |
182 | } |