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0207a2ef KM |
1 | /* |
2 | * SH7724 Setup | |
3 | * | |
4 | * Copyright (C) 2009 Renesas Solutions Corp. | |
5 | * | |
6 | * Kuninori Morimoto <morimoto.kuninori@renesas.com> | |
7 | * | |
8 | * Based on SH7723 Setup | |
9 | * Copyright (C) 2008 Paul Mundt | |
10 | * | |
11 | * This file is subject to the terms and conditions of the GNU General Public | |
12 | * License. See the file "COPYING" in the main directory of this archive | |
13 | * for more details. | |
14 | */ | |
15 | #include <linux/platform_device.h> | |
16 | #include <linux/init.h> | |
17 | #include <linux/serial.h> | |
18 | #include <linux/mm.h> | |
19 | #include <linux/serial_sci.h> | |
20 | #include <linux/uio_driver.h> | |
46a12f74 | 21 | #include <linux/sh_timer.h> |
0207a2ef | 22 | #include <linux/io.h> |
da14909e MD |
23 | #include <linux/notifier.h> |
24 | #include <asm/suspend.h> | |
0207a2ef KM |
25 | #include <asm/clock.h> |
26 | #include <asm/mmzone.h> | |
593a0c89 | 27 | #include <cpu/sh7724.h> |
0207a2ef KM |
28 | |
29 | /* Serial */ | |
bcac24d0 MD |
30 | static struct plat_sci_port scif0_platform_data = { |
31 | .mapbase = 0xffe00000, | |
32 | .flags = UPF_BOOT_AUTOCONF, | |
33 | .type = PORT_SCIF, | |
34 | .irqs = { 80, 80, 80, 80 }, | |
35 | .clk = "scif0", | |
36 | }; | |
37 | ||
38 | static struct platform_device scif0_device = { | |
0207a2ef | 39 | .name = "sh-sci", |
bcac24d0 MD |
40 | .id = 0, |
41 | .dev = { | |
42 | .platform_data = &scif0_platform_data, | |
43 | }, | |
44 | }; | |
45 | ||
46 | static struct plat_sci_port scif1_platform_data = { | |
47 | .mapbase = 0xffe10000, | |
48 | .flags = UPF_BOOT_AUTOCONF, | |
49 | .type = PORT_SCIF, | |
50 | .irqs = { 81, 81, 81, 81 }, | |
51 | .clk = "scif1", | |
52 | }; | |
53 | ||
54 | static struct platform_device scif1_device = { | |
55 | .name = "sh-sci", | |
56 | .id = 1, | |
57 | .dev = { | |
58 | .platform_data = &scif1_platform_data, | |
59 | }, | |
60 | }; | |
61 | ||
62 | static struct plat_sci_port scif2_platform_data = { | |
63 | .mapbase = 0xffe20000, | |
64 | .flags = UPF_BOOT_AUTOCONF, | |
65 | .type = PORT_SCIF, | |
66 | .irqs = { 82, 82, 82, 82 }, | |
67 | .clk = "scif2", | |
68 | }; | |
69 | ||
70 | static struct platform_device scif2_device = { | |
71 | .name = "sh-sci", | |
72 | .id = 2, | |
73 | .dev = { | |
74 | .platform_data = &scif2_platform_data, | |
75 | }, | |
76 | }; | |
77 | ||
78 | static struct plat_sci_port scif3_platform_data = { | |
79 | .mapbase = 0xa4e30000, | |
80 | .flags = UPF_BOOT_AUTOCONF, | |
81 | .type = PORT_SCIFA, | |
82 | .irqs = { 56, 56, 56, 56 }, | |
83 | .clk = "scif3", | |
84 | }; | |
85 | ||
86 | static struct platform_device scif3_device = { | |
87 | .name = "sh-sci", | |
88 | .id = 3, | |
89 | .dev = { | |
90 | .platform_data = &scif3_platform_data, | |
91 | }, | |
92 | }; | |
93 | ||
94 | static struct plat_sci_port scif4_platform_data = { | |
95 | .mapbase = 0xa4e40000, | |
96 | .flags = UPF_BOOT_AUTOCONF, | |
97 | .type = PORT_SCIFA, | |
98 | .irqs = { 88, 88, 88, 88 }, | |
99 | .clk = "scif4", | |
100 | }; | |
101 | ||
102 | static struct platform_device scif4_device = { | |
103 | .name = "sh-sci", | |
104 | .id = 4, | |
105 | .dev = { | |
106 | .platform_data = &scif4_platform_data, | |
107 | }, | |
108 | }; | |
109 | ||
110 | static struct plat_sci_port scif5_platform_data = { | |
111 | .mapbase = 0xa4e50000, | |
112 | .flags = UPF_BOOT_AUTOCONF, | |
113 | .type = PORT_SCIFA, | |
114 | .irqs = { 109, 109, 109, 109 }, | |
115 | .clk = "scif5", | |
116 | }; | |
117 | ||
118 | static struct platform_device scif5_device = { | |
119 | .name = "sh-sci", | |
120 | .id = 5, | |
0207a2ef | 121 | .dev = { |
bcac24d0 | 122 | .platform_data = &scif5_platform_data, |
0207a2ef KM |
123 | }, |
124 | }; | |
125 | ||
126 | /* RTC */ | |
127 | static struct resource rtc_resources[] = { | |
128 | [0] = { | |
129 | .start = 0xa465fec0, | |
130 | .end = 0xa465fec0 + 0x58 - 1, | |
131 | .flags = IORESOURCE_IO, | |
132 | }, | |
133 | [1] = { | |
134 | /* Period IRQ */ | |
135 | .start = 69, | |
136 | .flags = IORESOURCE_IRQ, | |
137 | }, | |
138 | [2] = { | |
139 | /* Carry IRQ */ | |
140 | .start = 70, | |
141 | .flags = IORESOURCE_IRQ, | |
142 | }, | |
143 | [3] = { | |
144 | /* Alarm IRQ */ | |
145 | .start = 68, | |
146 | .flags = IORESOURCE_IRQ, | |
147 | }, | |
148 | }; | |
149 | ||
150 | static struct platform_device rtc_device = { | |
151 | .name = "sh-rtc", | |
152 | .id = -1, | |
153 | .num_resources = ARRAY_SIZE(rtc_resources), | |
154 | .resource = rtc_resources, | |
593a0c89 MD |
155 | .archdata = { |
156 | .hwblk_id = HWBLK_RTC, | |
157 | }, | |
0207a2ef KM |
158 | }; |
159 | ||
40c7e8be KM |
160 | /* I2C0 */ |
161 | static struct resource iic0_resources[] = { | |
162 | [0] = { | |
163 | .name = "IIC0", | |
164 | .start = 0x04470000, | |
165 | .end = 0x04470018 - 1, | |
166 | .flags = IORESOURCE_MEM, | |
167 | }, | |
168 | [1] = { | |
169 | .start = 96, | |
170 | .end = 99, | |
171 | .flags = IORESOURCE_IRQ, | |
172 | }, | |
173 | }; | |
174 | ||
175 | static struct platform_device iic0_device = { | |
176 | .name = "i2c-sh_mobile", | |
177 | .id = 0, /* "i2c0" clock */ | |
178 | .num_resources = ARRAY_SIZE(iic0_resources), | |
179 | .resource = iic0_resources, | |
593a0c89 MD |
180 | .archdata = { |
181 | .hwblk_id = HWBLK_IIC0, | |
182 | }, | |
40c7e8be KM |
183 | }; |
184 | ||
185 | /* I2C1 */ | |
186 | static struct resource iic1_resources[] = { | |
187 | [0] = { | |
188 | .name = "IIC1", | |
189 | .start = 0x04750000, | |
190 | .end = 0x04750018 - 1, | |
191 | .flags = IORESOURCE_MEM, | |
192 | }, | |
193 | [1] = { | |
194 | .start = 92, | |
195 | .end = 95, | |
196 | .flags = IORESOURCE_IRQ, | |
197 | }, | |
198 | }; | |
199 | ||
200 | static struct platform_device iic1_device = { | |
201 | .name = "i2c-sh_mobile", | |
202 | .id = 1, /* "i2c1" clock */ | |
203 | .num_resources = ARRAY_SIZE(iic1_resources), | |
204 | .resource = iic1_resources, | |
593a0c89 MD |
205 | .archdata = { |
206 | .hwblk_id = HWBLK_IIC1, | |
207 | }, | |
40c7e8be KM |
208 | }; |
209 | ||
cd5b9ef7 KM |
210 | /* VPU */ |
211 | static struct uio_info vpu_platform_data = { | |
212 | .name = "VPU5F", | |
213 | .version = "0", | |
214 | .irq = 60, | |
215 | }; | |
216 | ||
217 | static struct resource vpu_resources[] = { | |
218 | [0] = { | |
219 | .name = "VPU", | |
220 | .start = 0xfe900000, | |
221 | .end = 0xfe902807, | |
222 | .flags = IORESOURCE_MEM, | |
223 | }, | |
224 | [1] = { | |
225 | /* place holder for contiguous memory */ | |
226 | }, | |
227 | }; | |
228 | ||
229 | static struct platform_device vpu_device = { | |
230 | .name = "uio_pdrv_genirq", | |
231 | .id = 0, | |
232 | .dev = { | |
233 | .platform_data = &vpu_platform_data, | |
234 | }, | |
235 | .resource = vpu_resources, | |
236 | .num_resources = ARRAY_SIZE(vpu_resources), | |
593a0c89 MD |
237 | .archdata = { |
238 | .hwblk_id = HWBLK_VPU, | |
239 | }, | |
cd5b9ef7 KM |
240 | }; |
241 | ||
ad95b78c KM |
242 | /* VEU0 */ |
243 | static struct uio_info veu0_platform_data = { | |
244 | .name = "VEU3F0", | |
245 | .version = "0", | |
246 | .irq = 83, | |
247 | }; | |
248 | ||
249 | static struct resource veu0_resources[] = { | |
250 | [0] = { | |
251 | .name = "VEU3F0", | |
252 | .start = 0xfe920000, | |
7e213481 | 253 | .end = 0xfe9200cb, |
ad95b78c KM |
254 | .flags = IORESOURCE_MEM, |
255 | }, | |
256 | [1] = { | |
257 | /* place holder for contiguous memory */ | |
258 | }, | |
259 | }; | |
260 | ||
261 | static struct platform_device veu0_device = { | |
262 | .name = "uio_pdrv_genirq", | |
263 | .id = 1, | |
264 | .dev = { | |
265 | .platform_data = &veu0_platform_data, | |
266 | }, | |
267 | .resource = veu0_resources, | |
268 | .num_resources = ARRAY_SIZE(veu0_resources), | |
593a0c89 MD |
269 | .archdata = { |
270 | .hwblk_id = HWBLK_VEU0, | |
271 | }, | |
ad95b78c KM |
272 | }; |
273 | ||
274 | /* VEU1 */ | |
275 | static struct uio_info veu1_platform_data = { | |
276 | .name = "VEU3F1", | |
277 | .version = "0", | |
278 | .irq = 54, | |
279 | }; | |
280 | ||
281 | static struct resource veu1_resources[] = { | |
282 | [0] = { | |
283 | .name = "VEU3F1", | |
284 | .start = 0xfe924000, | |
7e213481 | 285 | .end = 0xfe9240cb, |
ad95b78c KM |
286 | .flags = IORESOURCE_MEM, |
287 | }, | |
288 | [1] = { | |
289 | /* place holder for contiguous memory */ | |
290 | }, | |
291 | }; | |
292 | ||
293 | static struct platform_device veu1_device = { | |
294 | .name = "uio_pdrv_genirq", | |
295 | .id = 2, | |
296 | .dev = { | |
297 | .platform_data = &veu1_platform_data, | |
298 | }, | |
299 | .resource = veu1_resources, | |
300 | .num_resources = ARRAY_SIZE(veu1_resources), | |
593a0c89 MD |
301 | .archdata = { |
302 | .hwblk_id = HWBLK_VEU1, | |
303 | }, | |
ad95b78c KM |
304 | }; |
305 | ||
46a12f74 | 306 | static struct sh_timer_config cmt_platform_data = { |
6a3395be PM |
307 | .name = "CMT", |
308 | .channel_offset = 0x60, | |
309 | .timer_bit = 5, | |
310 | .clk = "cmt0", | |
311 | .clockevent_rating = 125, | |
312 | .clocksource_rating = 200, | |
313 | }; | |
314 | ||
315 | static struct resource cmt_resources[] = { | |
316 | [0] = { | |
317 | .name = "CMT", | |
318 | .start = 0x044a0060, | |
319 | .end = 0x044a006b, | |
320 | .flags = IORESOURCE_MEM, | |
321 | }, | |
322 | [1] = { | |
323 | .start = 104, | |
324 | .flags = IORESOURCE_IRQ, | |
325 | }, | |
326 | }; | |
327 | ||
328 | static struct platform_device cmt_device = { | |
329 | .name = "sh_cmt", | |
330 | .id = 0, | |
331 | .dev = { | |
332 | .platform_data = &cmt_platform_data, | |
333 | }, | |
334 | .resource = cmt_resources, | |
335 | .num_resources = ARRAY_SIZE(cmt_resources), | |
593a0c89 MD |
336 | .archdata = { |
337 | .hwblk_id = HWBLK_CMT, | |
338 | }, | |
6a3395be PM |
339 | }; |
340 | ||
6a3501b6 MD |
341 | static struct sh_timer_config tmu0_platform_data = { |
342 | .name = "TMU0", | |
343 | .channel_offset = 0x04, | |
344 | .timer_bit = 0, | |
345 | .clk = "tmu0", | |
346 | .clockevent_rating = 200, | |
347 | }; | |
348 | ||
349 | static struct resource tmu0_resources[] = { | |
350 | [0] = { | |
351 | .name = "TMU0", | |
352 | .start = 0xffd80008, | |
353 | .end = 0xffd80013, | |
354 | .flags = IORESOURCE_MEM, | |
355 | }, | |
356 | [1] = { | |
357 | .start = 16, | |
358 | .flags = IORESOURCE_IRQ, | |
359 | }, | |
360 | }; | |
361 | ||
362 | static struct platform_device tmu0_device = { | |
363 | .name = "sh_tmu", | |
364 | .id = 0, | |
365 | .dev = { | |
366 | .platform_data = &tmu0_platform_data, | |
367 | }, | |
368 | .resource = tmu0_resources, | |
369 | .num_resources = ARRAY_SIZE(tmu0_resources), | |
593a0c89 MD |
370 | .archdata = { |
371 | .hwblk_id = HWBLK_TMU0, | |
372 | }, | |
6a3501b6 MD |
373 | }; |
374 | ||
375 | static struct sh_timer_config tmu1_platform_data = { | |
376 | .name = "TMU1", | |
377 | .channel_offset = 0x10, | |
378 | .timer_bit = 1, | |
379 | .clk = "tmu0", | |
380 | .clocksource_rating = 200, | |
381 | }; | |
382 | ||
383 | static struct resource tmu1_resources[] = { | |
384 | [0] = { | |
385 | .name = "TMU1", | |
386 | .start = 0xffd80014, | |
387 | .end = 0xffd8001f, | |
388 | .flags = IORESOURCE_MEM, | |
389 | }, | |
390 | [1] = { | |
391 | .start = 17, | |
392 | .flags = IORESOURCE_IRQ, | |
393 | }, | |
394 | }; | |
395 | ||
396 | static struct platform_device tmu1_device = { | |
397 | .name = "sh_tmu", | |
398 | .id = 1, | |
399 | .dev = { | |
400 | .platform_data = &tmu1_platform_data, | |
401 | }, | |
402 | .resource = tmu1_resources, | |
403 | .num_resources = ARRAY_SIZE(tmu1_resources), | |
593a0c89 MD |
404 | .archdata = { |
405 | .hwblk_id = HWBLK_TMU0, | |
406 | }, | |
6a3501b6 MD |
407 | }; |
408 | ||
409 | static struct sh_timer_config tmu2_platform_data = { | |
410 | .name = "TMU2", | |
411 | .channel_offset = 0x1c, | |
412 | .timer_bit = 2, | |
413 | .clk = "tmu0", | |
414 | }; | |
415 | ||
416 | static struct resource tmu2_resources[] = { | |
417 | [0] = { | |
418 | .name = "TMU2", | |
419 | .start = 0xffd80020, | |
420 | .end = 0xffd8002b, | |
421 | .flags = IORESOURCE_MEM, | |
422 | }, | |
423 | [1] = { | |
424 | .start = 18, | |
425 | .flags = IORESOURCE_IRQ, | |
426 | }, | |
427 | }; | |
428 | ||
429 | static struct platform_device tmu2_device = { | |
430 | .name = "sh_tmu", | |
431 | .id = 2, | |
432 | .dev = { | |
433 | .platform_data = &tmu2_platform_data, | |
434 | }, | |
435 | .resource = tmu2_resources, | |
436 | .num_resources = ARRAY_SIZE(tmu2_resources), | |
593a0c89 MD |
437 | .archdata = { |
438 | .hwblk_id = HWBLK_TMU0, | |
439 | }, | |
6a3501b6 MD |
440 | }; |
441 | ||
442 | ||
443 | static struct sh_timer_config tmu3_platform_data = { | |
444 | .name = "TMU3", | |
445 | .channel_offset = 0x04, | |
446 | .timer_bit = 0, | |
447 | .clk = "tmu1", | |
448 | }; | |
449 | ||
450 | static struct resource tmu3_resources[] = { | |
451 | [0] = { | |
452 | .name = "TMU3", | |
453 | .start = 0xffd90008, | |
454 | .end = 0xffd90013, | |
455 | .flags = IORESOURCE_MEM, | |
456 | }, | |
457 | [1] = { | |
458 | .start = 57, | |
459 | .flags = IORESOURCE_IRQ, | |
460 | }, | |
461 | }; | |
462 | ||
463 | static struct platform_device tmu3_device = { | |
464 | .name = "sh_tmu", | |
465 | .id = 3, | |
466 | .dev = { | |
467 | .platform_data = &tmu3_platform_data, | |
468 | }, | |
469 | .resource = tmu3_resources, | |
470 | .num_resources = ARRAY_SIZE(tmu3_resources), | |
593a0c89 MD |
471 | .archdata = { |
472 | .hwblk_id = HWBLK_TMU1, | |
473 | }, | |
6a3501b6 MD |
474 | }; |
475 | ||
476 | static struct sh_timer_config tmu4_platform_data = { | |
477 | .name = "TMU4", | |
478 | .channel_offset = 0x10, | |
479 | .timer_bit = 1, | |
480 | .clk = "tmu1", | |
481 | }; | |
482 | ||
483 | static struct resource tmu4_resources[] = { | |
484 | [0] = { | |
485 | .name = "TMU4", | |
486 | .start = 0xffd90014, | |
487 | .end = 0xffd9001f, | |
488 | .flags = IORESOURCE_MEM, | |
489 | }, | |
490 | [1] = { | |
491 | .start = 58, | |
492 | .flags = IORESOURCE_IRQ, | |
493 | }, | |
494 | }; | |
495 | ||
496 | static struct platform_device tmu4_device = { | |
497 | .name = "sh_tmu", | |
498 | .id = 4, | |
499 | .dev = { | |
500 | .platform_data = &tmu4_platform_data, | |
501 | }, | |
502 | .resource = tmu4_resources, | |
503 | .num_resources = ARRAY_SIZE(tmu4_resources), | |
593a0c89 MD |
504 | .archdata = { |
505 | .hwblk_id = HWBLK_TMU1, | |
506 | }, | |
6a3501b6 MD |
507 | }; |
508 | ||
509 | static struct sh_timer_config tmu5_platform_data = { | |
510 | .name = "TMU5", | |
511 | .channel_offset = 0x1c, | |
512 | .timer_bit = 2, | |
513 | .clk = "tmu1", | |
514 | }; | |
515 | ||
516 | static struct resource tmu5_resources[] = { | |
517 | [0] = { | |
518 | .name = "TMU5", | |
519 | .start = 0xffd90020, | |
520 | .end = 0xffd9002b, | |
521 | .flags = IORESOURCE_MEM, | |
522 | }, | |
523 | [1] = { | |
524 | .start = 57, | |
525 | .flags = IORESOURCE_IRQ, | |
526 | }, | |
527 | }; | |
528 | ||
529 | static struct platform_device tmu5_device = { | |
530 | .name = "sh_tmu", | |
531 | .id = 5, | |
532 | .dev = { | |
533 | .platform_data = &tmu5_platform_data, | |
534 | }, | |
535 | .resource = tmu5_resources, | |
536 | .num_resources = ARRAY_SIZE(tmu5_resources), | |
593a0c89 MD |
537 | .archdata = { |
538 | .hwblk_id = HWBLK_TMU1, | |
539 | }, | |
6a3501b6 MD |
540 | }; |
541 | ||
f168dd00 KM |
542 | /* JPU */ |
543 | static struct uio_info jpu_platform_data = { | |
544 | .name = "JPU", | |
545 | .version = "0", | |
546 | .irq = 27, | |
547 | }; | |
548 | ||
549 | static struct resource jpu_resources[] = { | |
550 | [0] = { | |
551 | .name = "JPU", | |
552 | .start = 0xfe980000, | |
553 | .end = 0xfe9902d3, | |
554 | .flags = IORESOURCE_MEM, | |
555 | }, | |
556 | [1] = { | |
557 | /* place holder for contiguous memory */ | |
558 | }, | |
559 | }; | |
560 | ||
561 | static struct platform_device jpu_device = { | |
562 | .name = "uio_pdrv_genirq", | |
563 | .id = 3, | |
564 | .dev = { | |
565 | .platform_data = &jpu_platform_data, | |
566 | }, | |
567 | .resource = jpu_resources, | |
568 | .num_resources = ARRAY_SIZE(jpu_resources), | |
593a0c89 MD |
569 | .archdata = { |
570 | .hwblk_id = HWBLK_JPU, | |
571 | }, | |
f168dd00 KM |
572 | }; |
573 | ||
2de33923 KM |
574 | /* SPU2DSP0 */ |
575 | static struct uio_info spu0_platform_data = { | |
576 | .name = "SPU2DSP0", | |
577 | .version = "0", | |
578 | .irq = 86, | |
579 | }; | |
580 | ||
581 | static struct resource spu0_resources[] = { | |
582 | [0] = { | |
583 | .name = "SPU2DSP0", | |
584 | .start = 0xFE200000, | |
585 | .end = 0xFE2FFFFF, | |
586 | .flags = IORESOURCE_MEM, | |
587 | }, | |
588 | [1] = { | |
589 | /* place holder for contiguous memory */ | |
590 | }, | |
591 | }; | |
592 | ||
593 | static struct platform_device spu0_device = { | |
594 | .name = "uio_pdrv_genirq", | |
595 | .id = 4, | |
596 | .dev = { | |
597 | .platform_data = &spu0_platform_data, | |
598 | }, | |
599 | .resource = spu0_resources, | |
600 | .num_resources = ARRAY_SIZE(spu0_resources), | |
601 | .archdata = { | |
602 | .hwblk_id = HWBLK_SPU, | |
603 | }, | |
604 | }; | |
605 | ||
606 | /* SPU2DSP1 */ | |
607 | static struct uio_info spu1_platform_data = { | |
608 | .name = "SPU2DSP1", | |
609 | .version = "0", | |
610 | .irq = 87, | |
611 | }; | |
612 | ||
613 | static struct resource spu1_resources[] = { | |
614 | [0] = { | |
615 | .name = "SPU2DSP1", | |
616 | .start = 0xFE300000, | |
617 | .end = 0xFE3FFFFF, | |
618 | .flags = IORESOURCE_MEM, | |
619 | }, | |
620 | [1] = { | |
621 | /* place holder for contiguous memory */ | |
622 | }, | |
623 | }; | |
624 | ||
625 | static struct platform_device spu1_device = { | |
626 | .name = "uio_pdrv_genirq", | |
627 | .id = 5, | |
628 | .dev = { | |
629 | .platform_data = &spu1_platform_data, | |
630 | }, | |
631 | .resource = spu1_resources, | |
632 | .num_resources = ARRAY_SIZE(spu1_resources), | |
633 | .archdata = { | |
634 | .hwblk_id = HWBLK_SPU, | |
635 | }, | |
636 | }; | |
637 | ||
0207a2ef | 638 | static struct platform_device *sh7724_devices[] __initdata = { |
bcac24d0 MD |
639 | &scif0_device, |
640 | &scif1_device, | |
641 | &scif2_device, | |
642 | &scif3_device, | |
643 | &scif4_device, | |
644 | &scif5_device, | |
6a3395be | 645 | &cmt_device, |
6a3501b6 MD |
646 | &tmu0_device, |
647 | &tmu1_device, | |
648 | &tmu2_device, | |
649 | &tmu3_device, | |
650 | &tmu4_device, | |
651 | &tmu5_device, | |
0207a2ef | 652 | &rtc_device, |
40c7e8be KM |
653 | &iic0_device, |
654 | &iic1_device, | |
cd5b9ef7 | 655 | &vpu_device, |
ad95b78c KM |
656 | &veu0_device, |
657 | &veu1_device, | |
f168dd00 | 658 | &jpu_device, |
2de33923 KM |
659 | &spu0_device, |
660 | &spu1_device, | |
0207a2ef KM |
661 | }; |
662 | ||
663 | static int __init sh7724_devices_setup(void) | |
664 | { | |
cd5b9ef7 | 665 | platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20); |
ad95b78c KM |
666 | platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20); |
667 | platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20); | |
f168dd00 | 668 | platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20); |
2de33923 KM |
669 | platform_resource_setup_memory(&spu0_device, "spu0", 2 << 20); |
670 | platform_resource_setup_memory(&spu1_device, "spu1", 2 << 20); | |
0207a2ef KM |
671 | |
672 | return platform_add_devices(sh7724_devices, | |
673 | ARRAY_SIZE(sh7724_devices)); | |
674 | } | |
955c9863 | 675 | arch_initcall(sh7724_devices_setup); |
0207a2ef | 676 | |
8fb2bae4 | 677 | static struct platform_device *sh7724_early_devices[] __initdata = { |
bcac24d0 MD |
678 | &scif0_device, |
679 | &scif1_device, | |
680 | &scif2_device, | |
681 | &scif3_device, | |
682 | &scif4_device, | |
683 | &scif5_device, | |
8fb2bae4 | 684 | &cmt_device, |
6a3501b6 MD |
685 | &tmu0_device, |
686 | &tmu1_device, | |
687 | &tmu2_device, | |
688 | &tmu3_device, | |
689 | &tmu4_device, | |
690 | &tmu5_device, | |
8fb2bae4 PM |
691 | }; |
692 | ||
693 | void __init plat_early_device_setup(void) | |
694 | { | |
695 | early_platform_add_devices(sh7724_early_devices, | |
696 | ARRAY_SIZE(sh7724_early_devices)); | |
697 | } | |
698 | ||
b4bd9eb0 KM |
699 | #define RAMCR_CACHE_L2FC 0x0002 |
700 | #define RAMCR_CACHE_L2E 0x0001 | |
701 | #define L2_CACHE_ENABLE (RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC) | |
702 | void __uses_jump_to_uncached l2_cache_init(void) | |
703 | { | |
704 | /* Enable L2 cache */ | |
705 | ctrl_outl(L2_CACHE_ENABLE, RAMCR); | |
706 | } | |
707 | ||
0207a2ef KM |
708 | enum { |
709 | UNUSED = 0, | |
710 | ||
711 | /* interrupt sources */ | |
712 | IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, | |
713 | HUDI, | |
714 | DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3, | |
c5eeff1f | 715 | _2DG_TRI, _2DG_INI, _2DG_CEI, |
0207a2ef | 716 | DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3, |
c5eeff1f KM |
717 | VIO_CEU0, VIO_BEU0, VIO_VEU1, VIO_VOU, |
718 | SCIFA3, | |
719 | VPU, | |
720 | TPU, | |
721 | CEU1, | |
722 | BEU1, | |
723 | USB0, USB1, | |
0207a2ef KM |
724 | ATAPI, |
725 | RTC_ATI, RTC_PRI, RTC_CUI, | |
726 | DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR, | |
727 | DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR, | |
c5eeff1f | 728 | KEYSC, |
0207a2ef | 729 | SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2, |
c5eeff1f | 730 | VEU0, |
0207a2ef KM |
731 | MSIOF_MSIOFI0, MSIOF_MSIOFI1, |
732 | SPU_SPUI0, SPU_SPUI1, | |
c5eeff1f KM |
733 | SCIFA4, |
734 | ICB, | |
0207a2ef KM |
735 | ETHI, |
736 | I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI, | |
737 | I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI, | |
c5eeff1f KM |
738 | SDHI0_SDHII0, SDHI0_SDHII1, SDHI0_SDHII2, SDHI0_SDHII3, |
739 | CMT, | |
740 | TSIF, | |
741 | FSI, | |
742 | SCIFA5, | |
0207a2ef | 743 | TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2, |
c5eeff1f | 744 | IRDA, |
0207a2ef | 745 | SDHI1_SDHII0, SDHI1_SDHII1, SDHI1_SDHII2, |
c5eeff1f KM |
746 | JPU, |
747 | _2DDMAC, | |
748 | MMC_MMC2I, MMC_MMC3I, | |
749 | LCDC, | |
0207a2ef KM |
750 | TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2, |
751 | ||
752 | /* interrupt groups */ | |
c5eeff1f KM |
753 | DMAC1A, _2DG, DMAC0A, VIO, USB, RTC, |
754 | DMAC1B, DMAC0B, I2C0, I2C1, SDHI0, SDHI1, SPU, MMCIF, | |
0207a2ef KM |
755 | }; |
756 | ||
757 | static struct intc_vect vectors[] __initdata = { | |
758 | INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620), | |
759 | INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660), | |
760 | INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0), | |
761 | INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0), | |
762 | ||
763 | INTC_VECT(DMAC1A_DEI0, 0x700), | |
764 | INTC_VECT(DMAC1A_DEI1, 0x720), | |
765 | INTC_VECT(DMAC1A_DEI2, 0x740), | |
766 | INTC_VECT(DMAC1A_DEI3, 0x760), | |
767 | ||
768 | INTC_VECT(_2DG_TRI, 0x780), | |
769 | INTC_VECT(_2DG_INI, 0x7A0), | |
770 | INTC_VECT(_2DG_CEI, 0x7C0), | |
0207a2ef KM |
771 | |
772 | INTC_VECT(DMAC0A_DEI0, 0x800), | |
773 | INTC_VECT(DMAC0A_DEI1, 0x820), | |
774 | INTC_VECT(DMAC0A_DEI2, 0x840), | |
775 | INTC_VECT(DMAC0A_DEI3, 0x860), | |
776 | ||
c5eeff1f KM |
777 | INTC_VECT(VIO_CEU0, 0x880), |
778 | INTC_VECT(VIO_BEU0, 0x8A0), | |
779 | INTC_VECT(VIO_VEU1, 0x8C0), | |
780 | INTC_VECT(VIO_VOU, 0x8E0), | |
0207a2ef | 781 | |
c5eeff1f KM |
782 | INTC_VECT(SCIFA3, 0x900), |
783 | INTC_VECT(VPU, 0x980), | |
784 | INTC_VECT(TPU, 0x9A0), | |
785 | INTC_VECT(CEU1, 0x9E0), | |
786 | INTC_VECT(BEU1, 0xA00), | |
787 | INTC_VECT(USB0, 0xA20), | |
788 | INTC_VECT(USB1, 0xA40), | |
789 | INTC_VECT(ATAPI, 0xA60), | |
0207a2ef KM |
790 | |
791 | INTC_VECT(RTC_ATI, 0xA80), | |
792 | INTC_VECT(RTC_PRI, 0xAA0), | |
793 | INTC_VECT(RTC_CUI, 0xAC0), | |
794 | ||
795 | INTC_VECT(DMAC1B_DEI4, 0xB00), | |
796 | INTC_VECT(DMAC1B_DEI5, 0xB20), | |
797 | INTC_VECT(DMAC1B_DADERR, 0xB40), | |
798 | ||
799 | INTC_VECT(DMAC0B_DEI4, 0xB80), | |
800 | INTC_VECT(DMAC0B_DEI5, 0xBA0), | |
801 | INTC_VECT(DMAC0B_DADERR, 0xBC0), | |
802 | ||
c5eeff1f | 803 | INTC_VECT(KEYSC, 0xBE0), |
0207a2ef KM |
804 | INTC_VECT(SCIF_SCIF0, 0xC00), |
805 | INTC_VECT(SCIF_SCIF1, 0xC20), | |
806 | INTC_VECT(SCIF_SCIF2, 0xC40), | |
c5eeff1f | 807 | INTC_VECT(VEU0, 0xC60), |
0207a2ef KM |
808 | INTC_VECT(MSIOF_MSIOFI0, 0xC80), |
809 | INTC_VECT(MSIOF_MSIOFI1, 0xCA0), | |
810 | INTC_VECT(SPU_SPUI0, 0xCC0), | |
811 | INTC_VECT(SPU_SPUI1, 0xCE0), | |
c5eeff1f | 812 | INTC_VECT(SCIFA4, 0xD00), |
0207a2ef | 813 | |
c5eeff1f | 814 | INTC_VECT(ICB, 0xD20), |
0207a2ef KM |
815 | INTC_VECT(ETHI, 0xD60), |
816 | ||
817 | INTC_VECT(I2C1_ALI, 0xD80), | |
818 | INTC_VECT(I2C1_TACKI, 0xDA0), | |
819 | INTC_VECT(I2C1_WAITI, 0xDC0), | |
820 | INTC_VECT(I2C1_DTEI, 0xDE0), | |
821 | ||
822 | INTC_VECT(I2C0_ALI, 0xE00), | |
823 | INTC_VECT(I2C0_TACKI, 0xE20), | |
824 | INTC_VECT(I2C0_WAITI, 0xE40), | |
825 | INTC_VECT(I2C0_DTEI, 0xE60), | |
826 | ||
827 | INTC_VECT(SDHI0_SDHII0, 0xE80), | |
828 | INTC_VECT(SDHI0_SDHII1, 0xEA0), | |
829 | INTC_VECT(SDHI0_SDHII2, 0xEC0), | |
c5eeff1f | 830 | INTC_VECT(SDHI0_SDHII3, 0xEE0), |
0207a2ef | 831 | |
c5eeff1f KM |
832 | INTC_VECT(CMT, 0xF00), |
833 | INTC_VECT(TSIF, 0xF20), | |
834 | INTC_VECT(FSI, 0xF80), | |
835 | INTC_VECT(SCIFA5, 0xFA0), | |
0207a2ef KM |
836 | |
837 | INTC_VECT(TMU0_TUNI0, 0x400), | |
838 | INTC_VECT(TMU0_TUNI1, 0x420), | |
839 | INTC_VECT(TMU0_TUNI2, 0x440), | |
840 | ||
c5eeff1f | 841 | INTC_VECT(IRDA, 0x480), |
0207a2ef KM |
842 | |
843 | INTC_VECT(SDHI1_SDHII0, 0x4E0), | |
844 | INTC_VECT(SDHI1_SDHII1, 0x500), | |
845 | INTC_VECT(SDHI1_SDHII2, 0x520), | |
846 | ||
c5eeff1f KM |
847 | INTC_VECT(JPU, 0x560), |
848 | INTC_VECT(_2DDMAC, 0x4A0), | |
0207a2ef | 849 | |
c5eeff1f KM |
850 | INTC_VECT(MMC_MMC2I, 0x5A0), |
851 | INTC_VECT(MMC_MMC3I, 0x5C0), | |
0207a2ef | 852 | |
c5eeff1f | 853 | INTC_VECT(LCDC, 0xF40), |
0207a2ef KM |
854 | |
855 | INTC_VECT(TMU1_TUNI0, 0x920), | |
856 | INTC_VECT(TMU1_TUNI1, 0x940), | |
857 | INTC_VECT(TMU1_TUNI2, 0x960), | |
858 | }; | |
859 | ||
860 | static struct intc_group groups[] __initdata = { | |
861 | INTC_GROUP(DMAC1A, DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3), | |
c5eeff1f | 862 | INTC_GROUP(_2DG, _2DG_TRI, _2DG_INI, _2DG_CEI), |
0207a2ef | 863 | INTC_GROUP(DMAC0A, DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3), |
c5eeff1f KM |
864 | INTC_GROUP(VIO, VIO_CEU0, VIO_BEU0, VIO_VEU1, VIO_VOU), |
865 | INTC_GROUP(USB, USB0, USB1), | |
0207a2ef KM |
866 | INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI), |
867 | INTC_GROUP(DMAC1B, DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR), | |
868 | INTC_GROUP(DMAC0B, DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR), | |
869 | INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI), | |
870 | INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI), | |
c5eeff1f | 871 | INTC_GROUP(SDHI0, SDHI0_SDHII0, SDHI0_SDHII1, SDHI0_SDHII2, SDHI0_SDHII3), |
0207a2ef KM |
872 | INTC_GROUP(SDHI1, SDHI1_SDHII0, SDHI1_SDHII1, SDHI1_SDHII2), |
873 | INTC_GROUP(SPU, SPU_SPUI0, SPU_SPUI1), | |
c5eeff1f | 874 | INTC_GROUP(MMCIF, MMC_MMC2I, MMC_MMC3I), |
0207a2ef KM |
875 | }; |
876 | ||
0207a2ef KM |
877 | static struct intc_mask_reg mask_registers[] __initdata = { |
878 | { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */ | |
879 | { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0, | |
c5eeff1f | 880 | 0, SDHI1_SDHII2, SDHI1_SDHII1, SDHI1_SDHII0 } }, |
0207a2ef | 881 | { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */ |
c5eeff1f | 882 | { VIO_VOU, VIO_VEU1, VIO_BEU0, VIO_CEU0, |
0207a2ef KM |
883 | DMAC0A_DEI3, DMAC0A_DEI2, DMAC0A_DEI1, DMAC0A_DEI0 } }, |
884 | { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */ | |
c5eeff1f | 885 | { 0, 0, 0, VPU, ATAPI, ETHI, 0, SCIFA3 } }, |
0207a2ef KM |
886 | { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */ |
887 | { DMAC1A_DEI3, DMAC1A_DEI2, DMAC1A_DEI1, DMAC1A_DEI0, | |
c5eeff1f | 888 | SPU_SPUI1, SPU_SPUI0, BEU1, IRDA } }, |
0207a2ef KM |
889 | { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */ |
890 | { 0, TMU0_TUNI2, TMU0_TUNI1, TMU0_TUNI0, | |
c5eeff1f | 891 | JPU, 0, 0, LCDC } }, |
0207a2ef | 892 | { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */ |
c5eeff1f KM |
893 | { KEYSC, DMAC0B_DADERR, DMAC0B_DEI5, DMAC0B_DEI4, |
894 | VEU0, SCIF_SCIF2, SCIF_SCIF1, SCIF_SCIF0 } }, | |
0207a2ef | 895 | { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */ |
c5eeff1f KM |
896 | { 0, 0, ICB, SCIFA4, |
897 | CEU1, 0, MSIOF_MSIOFI1, MSIOF_MSIOFI0 } }, | |
0207a2ef KM |
898 | { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */ |
899 | { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI, | |
900 | I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI } }, | |
901 | { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ | |
c5eeff1f KM |
902 | { SDHI0_SDHII3, SDHI0_SDHII2, SDHI0_SDHII1, SDHI0_SDHII0, |
903 | 0, 0, SCIFA5, FSI } }, | |
0207a2ef | 904 | { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ |
c5eeff1f | 905 | { 0, 0, 0, CMT, 0, USB1, USB0, 0 } }, |
0207a2ef KM |
906 | { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */ |
907 | { 0, DMAC1B_DADERR, DMAC1B_DEI5, DMAC1B_DEI4, | |
c5eeff1f | 908 | 0, RTC_CUI, RTC_PRI, RTC_ATI } }, |
0207a2ef | 909 | { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */ |
c5eeff1f KM |
910 | { 0, _2DG_CEI, _2DG_INI, _2DG_TRI, |
911 | 0, TPU, 0, TSIF } }, | |
0207a2ef | 912 | { 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */ |
c5eeff1f | 913 | { 0, 0, MMC_MMC3I, MMC_MMC2I, 0, 0, 0, _2DDMAC } }, |
0207a2ef KM |
914 | { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */ |
915 | { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, | |
916 | }; | |
917 | ||
918 | static struct intc_prio_reg prio_registers[] __initdata = { | |
919 | { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1, | |
c5eeff1f KM |
920 | TMU0_TUNI2, IRDA } }, |
921 | { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, DMAC1A, BEU1 } }, | |
0207a2ef KM |
922 | { 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1, |
923 | TMU1_TUNI2, SPU } }, | |
c5eeff1f KM |
924 | { 0xa408000c, 0, 16, 4, /* IPRD */ { 0, MMCIF, 0, ATAPI } }, |
925 | { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0A, VIO, SCIFA3, VPU } }, | |
926 | { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC0B, USB, CMT } }, | |
0207a2ef | 927 | { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1, |
c5eeff1f | 928 | SCIF_SCIF2, VEU0 } }, |
0207a2ef KM |
929 | { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0, MSIOF_MSIOFI1, |
930 | I2C1, I2C0 } }, | |
c5eeff1f KM |
931 | { 0xa4080020, 0, 16, 4, /* IPRI */ { SCIFA4, ICB, TSIF, _2DG } }, |
932 | { 0xa4080024, 0, 16, 4, /* IPRJ */ { CEU1, ETHI, FSI, SDHI1 } }, | |
933 | { 0xa4080028, 0, 16, 4, /* IPRK */ { RTC, DMAC1B, 0, SDHI0 } }, | |
934 | { 0xa408002c, 0, 16, 4, /* IPRL */ { SCIFA5, 0, TPU, _2DDMAC } }, | |
0207a2ef KM |
935 | { 0xa4140010, 0, 32, 4, /* INTPRI00 */ |
936 | { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, | |
937 | }; | |
938 | ||
939 | static struct intc_sense_reg sense_registers[] __initdata = { | |
940 | { 0xa414001c, 16, 2, /* ICR1 */ | |
941 | { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, | |
942 | }; | |
943 | ||
944 | static struct intc_mask_reg ack_registers[] __initdata = { | |
945 | { 0xa4140024, 0, 8, /* INTREQ00 */ | |
946 | { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, | |
947 | }; | |
948 | ||
949 | static DECLARE_INTC_DESC_ACK(intc_desc, "sh7724", vectors, groups, | |
950 | mask_registers, prio_registers, sense_registers, | |
951 | ack_registers); | |
952 | ||
953 | void __init plat_irq_setup(void) | |
954 | { | |
955 | register_intc_controller(&intc_desc); | |
956 | } | |
da14909e MD |
957 | |
958 | static struct { | |
959 | /* BSC */ | |
960 | unsigned long mmselr; | |
961 | unsigned long cs0bcr; | |
962 | unsigned long cs4bcr; | |
963 | unsigned long cs5abcr; | |
964 | unsigned long cs5bbcr; | |
965 | unsigned long cs6abcr; | |
966 | unsigned long cs6bbcr; | |
967 | unsigned long cs4wcr; | |
968 | unsigned long cs5awcr; | |
969 | unsigned long cs5bwcr; | |
970 | unsigned long cs6awcr; | |
971 | unsigned long cs6bwcr; | |
972 | /* INTC */ | |
973 | unsigned short ipra; | |
974 | unsigned short iprb; | |
975 | unsigned short iprc; | |
976 | unsigned short iprd; | |
977 | unsigned short ipre; | |
978 | unsigned short iprf; | |
979 | unsigned short iprg; | |
980 | unsigned short iprh; | |
981 | unsigned short ipri; | |
982 | unsigned short iprj; | |
983 | unsigned short iprk; | |
984 | unsigned short iprl; | |
985 | unsigned char imr0; | |
986 | unsigned char imr1; | |
987 | unsigned char imr2; | |
988 | unsigned char imr3; | |
989 | unsigned char imr4; | |
990 | unsigned char imr5; | |
991 | unsigned char imr6; | |
992 | unsigned char imr7; | |
993 | unsigned char imr8; | |
994 | unsigned char imr9; | |
995 | unsigned char imr10; | |
996 | unsigned char imr11; | |
997 | unsigned char imr12; | |
c4b973f5 MD |
998 | /* RWDT */ |
999 | unsigned short rwtcnt; | |
1000 | unsigned short rwtcsr; | |
2ebe0ff7 MD |
1001 | /* CPG */ |
1002 | unsigned long irdaclk; | |
1003 | unsigned long spuclk; | |
da14909e MD |
1004 | } sh7724_rstandby_state; |
1005 | ||
1006 | static int sh7724_pre_sleep_notifier_call(struct notifier_block *nb, | |
1007 | unsigned long flags, void *unused) | |
1008 | { | |
1009 | if (!(flags & SUSP_SH_RSTANDBY)) | |
1010 | return NOTIFY_DONE; | |
1011 | ||
1012 | /* BCR */ | |
1013 | sh7724_rstandby_state.mmselr = __raw_readl(0xff800020); /* MMSELR */ | |
1014 | sh7724_rstandby_state.mmselr |= 0xa5a50000; | |
1015 | sh7724_rstandby_state.cs0bcr = __raw_readl(0xfec10004); /* CS0BCR */ | |
1016 | sh7724_rstandby_state.cs4bcr = __raw_readl(0xfec10010); /* CS4BCR */ | |
1017 | sh7724_rstandby_state.cs5abcr = __raw_readl(0xfec10014); /* CS5ABCR */ | |
1018 | sh7724_rstandby_state.cs5bbcr = __raw_readl(0xfec10018); /* CS5BBCR */ | |
1019 | sh7724_rstandby_state.cs6abcr = __raw_readl(0xfec1001c); /* CS6ABCR */ | |
1020 | sh7724_rstandby_state.cs6bbcr = __raw_readl(0xfec10020); /* CS6BBCR */ | |
1021 | sh7724_rstandby_state.cs4wcr = __raw_readl(0xfec10030); /* CS4WCR */ | |
1022 | sh7724_rstandby_state.cs5awcr = __raw_readl(0xfec10034); /* CS5AWCR */ | |
1023 | sh7724_rstandby_state.cs5bwcr = __raw_readl(0xfec10038); /* CS5BWCR */ | |
1024 | sh7724_rstandby_state.cs6awcr = __raw_readl(0xfec1003c); /* CS6AWCR */ | |
1025 | sh7724_rstandby_state.cs6bwcr = __raw_readl(0xfec10040); /* CS6BWCR */ | |
1026 | ||
1027 | /* INTC */ | |
1028 | sh7724_rstandby_state.ipra = __raw_readw(0xa4080000); /* IPRA */ | |
1029 | sh7724_rstandby_state.iprb = __raw_readw(0xa4080004); /* IPRB */ | |
1030 | sh7724_rstandby_state.iprc = __raw_readw(0xa4080008); /* IPRC */ | |
1031 | sh7724_rstandby_state.iprd = __raw_readw(0xa408000c); /* IPRD */ | |
1032 | sh7724_rstandby_state.ipre = __raw_readw(0xa4080010); /* IPRE */ | |
1033 | sh7724_rstandby_state.iprf = __raw_readw(0xa4080014); /* IPRF */ | |
1034 | sh7724_rstandby_state.iprg = __raw_readw(0xa4080018); /* IPRG */ | |
1035 | sh7724_rstandby_state.iprh = __raw_readw(0xa408001c); /* IPRH */ | |
1036 | sh7724_rstandby_state.ipri = __raw_readw(0xa4080020); /* IPRI */ | |
1037 | sh7724_rstandby_state.iprj = __raw_readw(0xa4080024); /* IPRJ */ | |
1038 | sh7724_rstandby_state.iprk = __raw_readw(0xa4080028); /* IPRK */ | |
1039 | sh7724_rstandby_state.iprl = __raw_readw(0xa408002c); /* IPRL */ | |
1040 | sh7724_rstandby_state.imr0 = __raw_readb(0xa4080080); /* IMR0 */ | |
1041 | sh7724_rstandby_state.imr1 = __raw_readb(0xa4080084); /* IMR1 */ | |
1042 | sh7724_rstandby_state.imr2 = __raw_readb(0xa4080088); /* IMR2 */ | |
1043 | sh7724_rstandby_state.imr3 = __raw_readb(0xa408008c); /* IMR3 */ | |
1044 | sh7724_rstandby_state.imr4 = __raw_readb(0xa4080090); /* IMR4 */ | |
1045 | sh7724_rstandby_state.imr5 = __raw_readb(0xa4080094); /* IMR5 */ | |
1046 | sh7724_rstandby_state.imr6 = __raw_readb(0xa4080098); /* IMR6 */ | |
1047 | sh7724_rstandby_state.imr7 = __raw_readb(0xa408009c); /* IMR7 */ | |
1048 | sh7724_rstandby_state.imr8 = __raw_readb(0xa40800a0); /* IMR8 */ | |
1049 | sh7724_rstandby_state.imr9 = __raw_readb(0xa40800a4); /* IMR9 */ | |
1050 | sh7724_rstandby_state.imr10 = __raw_readb(0xa40800a8); /* IMR10 */ | |
1051 | sh7724_rstandby_state.imr11 = __raw_readb(0xa40800ac); /* IMR11 */ | |
1052 | sh7724_rstandby_state.imr12 = __raw_readb(0xa40800b0); /* IMR12 */ | |
1053 | ||
c4b973f5 MD |
1054 | /* RWDT */ |
1055 | sh7724_rstandby_state.rwtcnt = __raw_readb(0xa4520000); /* RWTCNT */ | |
1056 | sh7724_rstandby_state.rwtcnt |= 0x5a00; | |
1057 | sh7724_rstandby_state.rwtcsr = __raw_readb(0xa4520004); /* RWTCSR */ | |
1058 | sh7724_rstandby_state.rwtcsr |= 0xa500; | |
1059 | __raw_writew(sh7724_rstandby_state.rwtcsr & 0x07, 0xa4520004); | |
1060 | ||
2ebe0ff7 MD |
1061 | /* CPG */ |
1062 | sh7724_rstandby_state.irdaclk = __raw_readl(0xa4150018); /* IRDACLKCR */ | |
1063 | sh7724_rstandby_state.spuclk = __raw_readl(0xa415003c); /* SPUCLKCR */ | |
1064 | ||
da14909e MD |
1065 | return NOTIFY_DONE; |
1066 | } | |
1067 | ||
1068 | static int sh7724_post_sleep_notifier_call(struct notifier_block *nb, | |
1069 | unsigned long flags, void *unused) | |
1070 | { | |
1071 | if (!(flags & SUSP_SH_RSTANDBY)) | |
1072 | return NOTIFY_DONE; | |
1073 | ||
1074 | /* BCR */ | |
1075 | __raw_writel(sh7724_rstandby_state.mmselr, 0xff800020); /* MMSELR */ | |
1076 | __raw_writel(sh7724_rstandby_state.cs0bcr, 0xfec10004); /* CS0BCR */ | |
1077 | __raw_writel(sh7724_rstandby_state.cs4bcr, 0xfec10010); /* CS4BCR */ | |
1078 | __raw_writel(sh7724_rstandby_state.cs5abcr, 0xfec10014); /* CS5ABCR */ | |
1079 | __raw_writel(sh7724_rstandby_state.cs5bbcr, 0xfec10018); /* CS5BBCR */ | |
1080 | __raw_writel(sh7724_rstandby_state.cs6abcr, 0xfec1001c); /* CS6ABCR */ | |
1081 | __raw_writel(sh7724_rstandby_state.cs6bbcr, 0xfec10020); /* CS6BBCR */ | |
1082 | __raw_writel(sh7724_rstandby_state.cs4wcr, 0xfec10030); /* CS4WCR */ | |
1083 | __raw_writel(sh7724_rstandby_state.cs5awcr, 0xfec10034); /* CS5AWCR */ | |
1084 | __raw_writel(sh7724_rstandby_state.cs5bwcr, 0xfec10038); /* CS5BWCR */ | |
1085 | __raw_writel(sh7724_rstandby_state.cs6awcr, 0xfec1003c); /* CS6AWCR */ | |
1086 | __raw_writel(sh7724_rstandby_state.cs6bwcr, 0xfec10040); /* CS6BWCR */ | |
1087 | ||
1088 | /* INTC */ | |
1089 | __raw_writew(sh7724_rstandby_state.ipra, 0xa4080000); /* IPRA */ | |
1090 | __raw_writew(sh7724_rstandby_state.iprb, 0xa4080004); /* IPRB */ | |
1091 | __raw_writew(sh7724_rstandby_state.iprc, 0xa4080008); /* IPRC */ | |
1092 | __raw_writew(sh7724_rstandby_state.iprd, 0xa408000c); /* IPRD */ | |
1093 | __raw_writew(sh7724_rstandby_state.ipre, 0xa4080010); /* IPRE */ | |
1094 | __raw_writew(sh7724_rstandby_state.iprf, 0xa4080014); /* IPRF */ | |
1095 | __raw_writew(sh7724_rstandby_state.iprg, 0xa4080018); /* IPRG */ | |
1096 | __raw_writew(sh7724_rstandby_state.iprh, 0xa408001c); /* IPRH */ | |
1097 | __raw_writew(sh7724_rstandby_state.ipri, 0xa4080020); /* IPRI */ | |
1098 | __raw_writew(sh7724_rstandby_state.iprj, 0xa4080024); /* IPRJ */ | |
1099 | __raw_writew(sh7724_rstandby_state.iprk, 0xa4080028); /* IPRK */ | |
1100 | __raw_writew(sh7724_rstandby_state.iprl, 0xa408002c); /* IPRL */ | |
1101 | __raw_writeb(sh7724_rstandby_state.imr0, 0xa4080080); /* IMR0 */ | |
1102 | __raw_writeb(sh7724_rstandby_state.imr1, 0xa4080084); /* IMR1 */ | |
1103 | __raw_writeb(sh7724_rstandby_state.imr2, 0xa4080088); /* IMR2 */ | |
1104 | __raw_writeb(sh7724_rstandby_state.imr3, 0xa408008c); /* IMR3 */ | |
1105 | __raw_writeb(sh7724_rstandby_state.imr4, 0xa4080090); /* IMR4 */ | |
1106 | __raw_writeb(sh7724_rstandby_state.imr5, 0xa4080094); /* IMR5 */ | |
1107 | __raw_writeb(sh7724_rstandby_state.imr6, 0xa4080098); /* IMR6 */ | |
1108 | __raw_writeb(sh7724_rstandby_state.imr7, 0xa408009c); /* IMR7 */ | |
1109 | __raw_writeb(sh7724_rstandby_state.imr8, 0xa40800a0); /* IMR8 */ | |
1110 | __raw_writeb(sh7724_rstandby_state.imr9, 0xa40800a4); /* IMR9 */ | |
1111 | __raw_writeb(sh7724_rstandby_state.imr10, 0xa40800a8); /* IMR10 */ | |
1112 | __raw_writeb(sh7724_rstandby_state.imr11, 0xa40800ac); /* IMR11 */ | |
1113 | __raw_writeb(sh7724_rstandby_state.imr12, 0xa40800b0); /* IMR12 */ | |
1114 | ||
c4b973f5 MD |
1115 | /* RWDT */ |
1116 | __raw_writew(sh7724_rstandby_state.rwtcnt, 0xa4520000); /* RWTCNT */ | |
1117 | __raw_writew(sh7724_rstandby_state.rwtcsr, 0xa4520004); /* RWTCSR */ | |
1118 | ||
2ebe0ff7 MD |
1119 | /* CPG */ |
1120 | __raw_writel(sh7724_rstandby_state.irdaclk, 0xa4150018); /* IRDACLKCR */ | |
1121 | __raw_writel(sh7724_rstandby_state.spuclk, 0xa415003c); /* SPUCLKCR */ | |
1122 | ||
da14909e MD |
1123 | return NOTIFY_DONE; |
1124 | } | |
1125 | ||
1126 | static struct notifier_block sh7724_pre_sleep_notifier = { | |
1127 | .notifier_call = sh7724_pre_sleep_notifier_call, | |
1128 | .priority = SH_MOBILE_PRE(SH_MOBILE_SLEEP_CPU), | |
1129 | }; | |
1130 | ||
1131 | static struct notifier_block sh7724_post_sleep_notifier = { | |
1132 | .notifier_call = sh7724_post_sleep_notifier_call, | |
1133 | .priority = SH_MOBILE_POST(SH_MOBILE_SLEEP_CPU), | |
1134 | }; | |
1135 | ||
1136 | static int __init sh7724_sleep_setup(void) | |
1137 | { | |
1138 | atomic_notifier_chain_register(&sh_mobile_pre_sleep_notifier_list, | |
1139 | &sh7724_pre_sleep_notifier); | |
1140 | ||
1141 | atomic_notifier_chain_register(&sh_mobile_post_sleep_notifier_list, | |
1142 | &sh7724_post_sleep_notifier); | |
1143 | return 0; | |
1144 | } | |
1145 | arch_initcall(sh7724_sleep_setup); | |
1146 |