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2b1bd1ac PM |
1 | /* |
2 | * arch/sh/kernel/cpu/sh4/clock-shx3.c | |
3 | * | |
4 | * SH-X3 support for the clock framework | |
5 | * | |
6 | * Copyright (C) 2006-2007 Renesas Technology Corp. | |
7 | * Copyright (C) 2006-2007 Renesas Solutions Corp. | |
8 | * Copyright (C) 2006-2007 Paul Mundt | |
9 | * | |
10 | * This file is subject to the terms and conditions of the GNU General Public | |
11 | * License. See the file "COPYING" in the main directory of this archive | |
12 | * for more details. | |
13 | */ | |
14 | #include <linux/init.h> | |
15 | #include <linux/kernel.h> | |
16 | #include <asm/clock.h> | |
17 | #include <asm/freq.h> | |
18 | #include <asm/io.h> | |
19 | ||
20 | static int ifc_divisors[] = { 1, 2, 4 ,6 }; | |
21 | static int bfc_divisors[] = { 1, 1, 1, 1, 1, 12, 16, 18, 24, 32, 36, 48 }; | |
22 | static int pfc_divisors[] = { 1, 1, 1, 1, 1, 1, 1, 18, 24, 32, 36, 48 }; | |
23 | static int cfc_divisors[] = { 1, 1, 4, 6 }; | |
24 | ||
25 | #define IFC_POS 28 | |
26 | #define IFC_MSK 0x0003 | |
27 | #define BFC_MSK 0x000f | |
28 | #define PFC_MSK 0x000f | |
29 | #define CFC_MSK 0x0003 | |
30 | #define BFC_POS 16 | |
31 | #define PFC_POS 0 | |
32 | #define CFC_POS 20 | |
33 | ||
34 | static void master_clk_init(struct clk *clk) | |
35 | { | |
36 | clk->rate *= pfc_divisors[(ctrl_inl(FRQCR) >> PFC_POS) & PFC_MSK]; | |
37 | } | |
38 | ||
39 | static struct clk_ops shx3_master_clk_ops = { | |
40 | .init = master_clk_init, | |
41 | }; | |
42 | ||
b68d8201 | 43 | static unsigned long module_clk_recalc(struct clk *clk) |
2b1bd1ac PM |
44 | { |
45 | int idx = ((ctrl_inl(FRQCR) >> PFC_POS) & PFC_MSK); | |
b68d8201 | 46 | return clk->parent->rate / pfc_divisors[idx]; |
2b1bd1ac PM |
47 | } |
48 | ||
49 | static struct clk_ops shx3_module_clk_ops = { | |
50 | .recalc = module_clk_recalc, | |
51 | }; | |
52 | ||
b68d8201 | 53 | static unsigned long bus_clk_recalc(struct clk *clk) |
2b1bd1ac PM |
54 | { |
55 | int idx = ((ctrl_inl(FRQCR) >> BFC_POS) & BFC_MSK); | |
b68d8201 | 56 | return clk->parent->rate / bfc_divisors[idx]; |
2b1bd1ac PM |
57 | } |
58 | ||
59 | static struct clk_ops shx3_bus_clk_ops = { | |
60 | .recalc = bus_clk_recalc, | |
61 | }; | |
62 | ||
b68d8201 | 63 | static unsigned long cpu_clk_recalc(struct clk *clk) |
2b1bd1ac PM |
64 | { |
65 | int idx = ((ctrl_inl(FRQCR) >> IFC_POS) & IFC_MSK); | |
b68d8201 | 66 | return clk->parent->rate / ifc_divisors[idx]; |
2b1bd1ac PM |
67 | } |
68 | ||
69 | static struct clk_ops shx3_cpu_clk_ops = { | |
70 | .recalc = cpu_clk_recalc, | |
71 | }; | |
72 | ||
73 | static struct clk_ops *shx3_clk_ops[] = { | |
74 | &shx3_master_clk_ops, | |
75 | &shx3_module_clk_ops, | |
76 | &shx3_bus_clk_ops, | |
77 | &shx3_cpu_clk_ops, | |
78 | }; | |
79 | ||
80 | void __init arch_init_clk_ops(struct clk_ops **ops, int idx) | |
81 | { | |
82 | if (idx < ARRAY_SIZE(shx3_clk_ops)) | |
83 | *ops = shx3_clk_ops[idx]; | |
84 | } | |
85 | ||
b68d8201 | 86 | static unsigned long shyway_clk_recalc(struct clk *clk) |
2b1bd1ac PM |
87 | { |
88 | int idx = ((ctrl_inl(FRQCR) >> CFC_POS) & CFC_MSK); | |
b68d8201 | 89 | return clk->parent->rate / cfc_divisors[idx]; |
2b1bd1ac PM |
90 | } |
91 | ||
92 | static struct clk_ops shx3_shyway_clk_ops = { | |
93 | .recalc = shyway_clk_recalc, | |
94 | }; | |
95 | ||
96 | static struct clk shx3_shyway_clk = { | |
97 | .name = "shyway_clk", | |
4ff29ff8 | 98 | .flags = CLK_ENABLE_ON_INIT, |
2b1bd1ac PM |
99 | .ops = &shx3_shyway_clk_ops, |
100 | }; | |
101 | ||
102 | /* | |
103 | * Additional SHx3-specific on-chip clocks that aren't already part of the | |
104 | * clock framework | |
105 | */ | |
106 | static struct clk *shx3_onchip_clocks[] = { | |
107 | &shx3_shyway_clk, | |
108 | }; | |
109 | ||
9fe5ee0e | 110 | int __init arch_clk_init(void) |
2b1bd1ac | 111 | { |
253b0887 | 112 | struct clk *clk; |
f5c84cf5 | 113 | int i, ret = 0; |
2b1bd1ac | 114 | |
253b0887 PM |
115 | cpg_clk_init(); |
116 | ||
117 | clk = clk_get(NULL, "master_clk"); | |
2b1bd1ac PM |
118 | for (i = 0; i < ARRAY_SIZE(shx3_onchip_clocks); i++) { |
119 | struct clk *clkp = shx3_onchip_clocks[i]; | |
120 | ||
121 | clkp->parent = clk; | |
f5c84cf5 | 122 | ret |= clk_register(clkp); |
2b1bd1ac PM |
123 | } |
124 | ||
2b1bd1ac PM |
125 | clk_put(clk); |
126 | ||
f5c84cf5 | 127 | return ret; |
2b1bd1ac | 128 | } |