[linux-2.6-block.git] / arch / sh / kernel / cpu / sh4 / setup-sh7760.c

/*
 * SH7760 Setup
 *
 *  Copyright (C) 2006  Paul Mundt
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/platform_device.h>
#include <linux/init.h>
#include <linux/serial.h>
#include <linux/sh_timer.h>
#include <linux/serial_sci.h>
#include <linux/io.h>

enum {
	UNUSED = 0,

	/* interrupt sources */
	IRL0, IRL1, IRL2, IRL3,
	HUDI, GPIOI, DMAC,
	IRQ4, IRQ5, IRQ6, IRQ7,
	HCAN20, HCAN21,
	SSI0, SSI1,
	HAC0, HAC1,
	I2C0, I2C1,
	USB, LCDC,
	DMABRG0, DMABRG1, DMABRG2,
	SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
	SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
	SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI,
	SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
	HSPI,
	MMCIF0, MMCIF1, MMCIF2, MMCIF3,
	MFI, ADC, CMT,
	TMU0, TMU1, TMU2,
	WDT, REF,

	/* interrupt groups */
	DMABRG, SCIF0, SCIF1, SCIF2, SIM, MMCIF,
};

static struct intc_vect vectors[] __initdata = {
	INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
	INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
	INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
	INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0),
	INTC_VECT(DMAC, 0x7c0), INTC_VECT(DMAC, 0x7e0),
	INTC_VECT(DMAC, 0x6c0),
	INTC_VECT(IRQ4, 0x800), INTC_VECT(IRQ5, 0x820),
	INTC_VECT(IRQ6, 0x840), INTC_VECT(IRQ6, 0x860),
	INTC_VECT(HCAN20, 0x900), INTC_VECT(HCAN21, 0x920),
	INTC_VECT(SSI0, 0x940), INTC_VECT(SSI1, 0x960),
	INTC_VECT(HAC0, 0x980), INTC_VECT(HAC1, 0x9a0),
	INTC_VECT(I2C0, 0x9c0), INTC_VECT(I2C1, 0x9e0),
	INTC_VECT(USB, 0xa00), INTC_VECT(LCDC, 0xa20),
	INTC_VECT(DMABRG0, 0xa80), INTC_VECT(DMABRG1, 0xaa0),
	INTC_VECT(DMABRG2, 0xac0),
	INTC_VECT(SCIF0_ERI, 0x880), INTC_VECT(SCIF0_RXI, 0x8a0),
	INTC_VECT(SCIF0_BRI, 0x8c0), INTC_VECT(SCIF0_TXI, 0x8e0),
	INTC_VECT(SCIF1_ERI, 0xb00), INTC_VECT(SCIF1_RXI, 0xb20),
	INTC_VECT(SCIF1_BRI, 0xb40), INTC_VECT(SCIF1_TXI, 0xb60),
	INTC_VECT(SCIF2_ERI, 0xb80), INTC_VECT(SCIF2_RXI, 0xba0),
	INTC_VECT(SCIF2_BRI, 0xbc0), INTC_VECT(SCIF2_TXI, 0xbe0),
	INTC_VECT(SIM_ERI, 0xc00), INTC_VECT(SIM_RXI, 0xc20),
	INTC_VECT(SIM_TXI, 0xc40), INTC_VECT(SIM_TEI, 0xc60),
	INTC_VECT(HSPI, 0xc80),
	INTC_VECT(MMCIF0, 0xd00), INTC_VECT(MMCIF1, 0xd20),
	INTC_VECT(MMCIF2, 0xd40), INTC_VECT(MMCIF3, 0xd60),
	INTC_VECT(MFI, 0xe80), /* 0xf80 according to data sheet */
	INTC_VECT(ADC, 0xf80), INTC_VECT(CMT, 0xfa0),
	INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
	INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
	INTC_VECT(WDT, 0x560),
	INTC_VECT(REF, 0x580), INTC_VECT(REF, 0x5a0),
};

static struct intc_group groups[] __initdata = {
	INTC_GROUP(DMABRG, DMABRG0, DMABRG1, DMABRG2),
	INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
	INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
	INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI),
	INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI),
	INTC_GROUP(MMCIF, MMCIF0, MMCIF1, MMCIF2, MMCIF3),
};

static struct intc_mask_reg mask_registers[] __initdata = {
	{ 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */
	  { IRQ4, IRQ5, IRQ6, IRQ7, 0, 0, HCAN20, HCAN21,
	    SSI0, SSI1, HAC0, HAC1, I2C0, I2C1, USB, LCDC,
	    0, DMABRG0, DMABRG1, DMABRG2,
	    SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
	    SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
	    SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI, } },
	{ 0xfe080044, 0xfe080064, 32, /* INTMSK04 / INTMSKCLR04 */
	  { 0, 0, 0, 0, 0, 0, 0, 0,
	    SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
	    HSPI, MMCIF0, MMCIF1, MMCIF2,
	    MMCIF3, 0, 0, 0, 0, 0, 0, 0,
	    0, MFI, 0, 0, 0, 0, ADC, CMT, } },
};

static struct intc_prio_reg prio_registers[] __initdata = {
	{ 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } },
	{ 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } },
	{ 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, 0, HUDI } },
	{ 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
	{ 0xfe080000, 0, 32, 4, /* INTPRI00 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
	{ 0xfe080004, 0, 32, 4, /* INTPRI04 */ { HCAN20, HCAN21, SSI0, SSI1,
						 HAC0, HAC1, I2C0, I2C1 } },
	{ 0xfe080008, 0, 32, 4, /* INTPRI08 */ { USB, LCDC, DMABRG, SCIF0,
						 SCIF1, SCIF2, SIM, HSPI } },
	{ 0xfe08000c, 0, 32, 4, /* INTPRI0C */ { 0, 0, MMCIF, 0,
						 MFI, 0, ADC, CMT } },
};

static DECLARE_INTC_DESC(intc_desc, "sh7760", vectors, groups,
			 mask_registers, prio_registers, NULL);

static struct intc_vect vectors_irq[] __initdata = {
	INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
	INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
};

static DECLARE_INTC_DESC(intc_desc_irq, "sh7760-irq", vectors_irq, groups,
			 mask_registers, prio_registers, NULL);

static struct plat_sci_port scif0_platform_data = {
	.mapbase	= 0xfe600000,
	.flags		= UPF_BOOT_AUTOCONF,
	.type		= PORT_SCIF,
	.irqs		= { 52, 53, 55, 54 },
};

static struct platform_device scif0_device = {
	.name		= "sh-sci",
	.id		= 0,
	.dev		= {
		.platform_data	= &scif0_platform_data,
	},
};

static struct plat_sci_port scif1_platform_data = {
	.mapbase	= 0xfe610000,
	.flags		= UPF_BOOT_AUTOCONF,
	.type		= PORT_SCIF,
	.irqs		= { 72, 73, 75, 74 },
};

static struct platform_device scif1_device = {
	.name		= "sh-sci",
	.id		= 1,
	.dev		= {
		.platform_data	= &scif1_platform_data,
	},
};

static struct plat_sci_port scif2_platform_data = {
	.mapbase	= 0xfe620000,
	.flags		= UPF_BOOT_AUTOCONF,
	.type		= PORT_SCIF,
	.irqs		= { 76, 77, 79, 78 },
};

static struct platform_device scif2_device = {
	.name		= "sh-sci",
	.id		= 2,
	.dev		= {
		.platform_data	= &scif2_platform_data,
	},
};

static struct plat_sci_port scif3_platform_data = {
	.mapbase	= 0xfe480000,
	.flags		= UPF_BOOT_AUTOCONF,
	.type		= PORT_SCI,
	.irqs		= { 80, 81, 82, 0 },
};

static struct platform_device scif3_device = {
	.name		= "sh-sci",
	.id		= 3,
	.dev		= {
		.platform_data	= &scif3_platform_data,
	},
};

static struct sh_timer_config tmu0_platform_data = {
	.channel_offset = 0x04,
	.timer_bit = 0,
	.clockevent_rating = 200,
};

static struct resource tmu0_resources[] = {
	[0] = {
		.start	= 0xffd80008,
		.end	= 0xffd80013,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= 16,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device tmu0_device = {
	.name		= "sh_tmu",
	.id		= 0,
	.dev = {
		.platform_data	= &tmu0_platform_data,
	},
	.resource	= tmu0_resources,
	.num_resources	= ARRAY_SIZE(tmu0_resources),
};

static struct sh_timer_config tmu1_platform_data = {
	.channel_offset = 0x10,
	.timer_bit = 1,
	.clocksource_rating = 200,
};

static struct resource tmu1_resources[] = {
	[0] = {
		.start	= 0xffd80014,
		.end	= 0xffd8001f,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= 17,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device tmu1_device = {
	.name		= "sh_tmu",
	.id		= 1,
	.dev = {
		.platform_data	= &tmu1_platform_data,
	},
	.resource	= tmu1_resources,
	.num_resources	= ARRAY_SIZE(tmu1_resources),
};

static struct sh_timer_config tmu2_platform_data = {
	.channel_offset = 0x1c,
	.timer_bit = 2,
};

static struct resource tmu2_resources[] = {
	[0] = {
		.start	= 0xffd80020,
		.end	= 0xffd8002f,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= 18,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device tmu2_device = {
	.name		= "sh_tmu",
	.id		= 2,
	.dev = {
		.platform_data	= &tmu2_platform_data,
	},
	.resource	= tmu2_resources,
	.num_resources	= ARRAY_SIZE(tmu2_resources),
};


static struct platform_device *sh7760_devices[] __initdata = {
	&scif0_device,
	&scif1_device,
	&scif2_device,
	&scif3_device,
	&tmu0_device,
	&tmu1_device,
	&tmu2_device,
};

static int __init sh7760_devices_setup(void)
{
	return platform_add_devices(sh7760_devices,
				    ARRAY_SIZE(sh7760_devices));
}
arch_initcall(sh7760_devices_setup);

static struct platform_device *sh7760_early_devices[] __initdata = {
	&scif0_device,
	&scif1_device,
	&scif2_device,
	&scif3_device,
	&tmu0_device,
	&tmu1_device,
	&tmu2_device,
};

void __init plat_early_device_setup(void)
{
	early_platform_add_devices(sh7760_early_devices,
				   ARRAY_SIZE(sh7760_early_devices));
}

#define INTC_ICR	0xffd00000UL
#define INTC_ICR_IRLM	(1 << 7)

void __init plat_irq_setup_pins(int mode)
{
	switch (mode) {
	case IRQ_MODE_IRQ:
		__raw_writew(__raw_readw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
		register_intc_controller(&intc_desc_irq);
		break;
	default:
		BUG();
	}
}

void __init plat_irq_setup(void)
{
	register_intc_controller(&intc_desc);
}
Commit	Line	Data
7dec62e9 PM	1	/*
	2	* SH7760 Setup
	3	*
	4	* Copyright (C) 2006 Paul Mundt
	5	*
	6	* This file is subject to the terms and conditions of the GNU General Public
	7	* License. See the file "COPYING" in the main directory of this archive
	8	* for more details.
	9	*/
	10	#include <linux/platform_device.h>
	11	#include <linux/init.h>
	12	#include <linux/serial.h>
c42f32dc	13	#include <linux/sh_timer.h>
96de1a8f	14	#include <linux/serial_sci.h>
53abf911	15	#include <linux/io.h>
7dec62e9	16
e29bfbc4 MD	17	enum {
	18	UNUSED = 0,
	19
	20	/* interrupt sources */
	21	IRL0, IRL1, IRL2, IRL3,
3d6ad460	22	HUDI, GPIOI, DMAC,
e29bfbc4 MD	23	IRQ4, IRQ5, IRQ6, IRQ7,
	24	HCAN20, HCAN21,
	25	SSI0, SSI1,
	26	HAC0, HAC1,
	27	I2C0, I2C1,
	28	USB, LCDC,
	29	DMABRG0, DMABRG1, DMABRG2,
	30	SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
	31	SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
	32	SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI,
	33	SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
	34	HSPI,
	35	MMCIF0, MMCIF1, MMCIF2, MMCIF3,
	36	MFI, ADC, CMT,
3d6ad460 MD	37	TMU0, TMU1, TMU2,
3d6ad460 MD	38	WDT, REF,
e29bfbc4 MD	39
e29bfbc4 MD	40	/* interrupt groups */
3d6ad460	41	DMABRG, SCIF0, SCIF1, SCIF2, SIM, MMCIF,
e29bfbc4 MD	42	};
e29bfbc4 MD	43
5c37e025	44	static struct intc_vect vectors[] __initdata = {
e29bfbc4	45	INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
3d6ad460 MD	46	INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
	47	INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
	48	INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0),
	49	INTC_VECT(DMAC, 0x7c0), INTC_VECT(DMAC, 0x7e0),
	50	INTC_VECT(DMAC, 0x6c0),
e29bfbc4 MD	51	INTC_VECT(IRQ4, 0x800), INTC_VECT(IRQ5, 0x820),
	52	INTC_VECT(IRQ6, 0x840), INTC_VECT(IRQ6, 0x860),
	53	INTC_VECT(HCAN20, 0x900), INTC_VECT(HCAN21, 0x920),
	54	INTC_VECT(SSI0, 0x940), INTC_VECT(SSI1, 0x960),
	55	INTC_VECT(HAC0, 0x980), INTC_VECT(HAC1, 0x9a0),
	56	INTC_VECT(I2C0, 0x9c0), INTC_VECT(I2C1, 0x9e0),
	57	INTC_VECT(USB, 0xa00), INTC_VECT(LCDC, 0xa20),
	58	INTC_VECT(DMABRG0, 0xa80), INTC_VECT(DMABRG1, 0xaa0),
	59	INTC_VECT(DMABRG2, 0xac0),
	60	INTC_VECT(SCIF0_ERI, 0x880), INTC_VECT(SCIF0_RXI, 0x8a0),
	61	INTC_VECT(SCIF0_BRI, 0x8c0), INTC_VECT(SCIF0_TXI, 0x8e0),
	62	INTC_VECT(SCIF1_ERI, 0xb00), INTC_VECT(SCIF1_RXI, 0xb20),
	63	INTC_VECT(SCIF1_BRI, 0xb40), INTC_VECT(SCIF1_TXI, 0xb60),
	64	INTC_VECT(SCIF2_ERI, 0xb80), INTC_VECT(SCIF2_RXI, 0xba0),
	65	INTC_VECT(SCIF2_BRI, 0xbc0), INTC_VECT(SCIF2_TXI, 0xbe0),
	66	INTC_VECT(SIM_ERI, 0xc00), INTC_VECT(SIM_RXI, 0xc20),
	67	INTC_VECT(SIM_TXI, 0xc40), INTC_VECT(SIM_TEI, 0xc60),
	68	INTC_VECT(HSPI, 0xc80),
	69	INTC_VECT(MMCIF0, 0xd00), INTC_VECT(MMCIF1, 0xd20),
	70	INTC_VECT(MMCIF2, 0xd40), INTC_VECT(MMCIF3, 0xd60),
	71	INTC_VECT(MFI, 0xe80), /* 0xf80 according to data sheet */
	72	INTC_VECT(ADC, 0xf80), INTC_VECT(CMT, 0xfa0),
	73	INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
3d6ad460	74	INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
e29bfbc4	75	INTC_VECT(WDT, 0x560),
3d6ad460	76	INTC_VECT(REF, 0x580), INTC_VECT(REF, 0x5a0),
e29bfbc4 MD	77	};
e29bfbc4 MD	78
5c37e025	79	static struct intc_group groups[] __initdata = {
e29bfbc4 MD	80	INTC_GROUP(DMABRG, DMABRG0, DMABRG1, DMABRG2),
	81	INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
	82	INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
	83	INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI),
	84	INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI),
	85	INTC_GROUP(MMCIF, MMCIF0, MMCIF1, MMCIF2, MMCIF3),
e29bfbc4 MD	86	};
e29bfbc4 MD	87
5c37e025	88	static struct intc_mask_reg mask_registers[] __initdata = {
e29bfbc4 MD	89	{ 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */
	90	{ IRQ4, IRQ5, IRQ6, IRQ7, 0, 0, HCAN20, HCAN21,
	91	SSI0, SSI1, HAC0, HAC1, I2C0, I2C1, USB, LCDC,
	92	0, DMABRG0, DMABRG1, DMABRG2,
	93	SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
	94	SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
	95	SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI, } },
	96	{ 0xfe080044, 0xfe080064, 32, /* INTMSK04 / INTMSKCLR04 */
	97	{ 0, 0, 0, 0, 0, 0, 0, 0,
	98	SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
	99	HSPI, MMCIF0, MMCIF1, MMCIF2,
	100	MMCIF3, 0, 0, 0, 0, 0, 0, 0,
	101	0, MFI, 0, 0, 0, 0, ADC, CMT, } },
	102	};
	103
5c37e025	104	static struct intc_prio_reg prio_registers[] __initdata = {
6ef5fb2c MD	105	{ 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } },
	106	{ 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } },
	107	{ 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, 0, HUDI } },
	108	{ 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
	109	{ 0xfe080000, 0, 32, 4, /* INTPRI00 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
	110	{ 0xfe080004, 0, 32, 4, /* INTPRI04 */ { HCAN20, HCAN21, SSI0, SSI1,
	111	HAC0, HAC1, I2C0, I2C1 } },
	112	{ 0xfe080008, 0, 32, 4, /* INTPRI08 */ { USB, LCDC, DMABRG, SCIF0,
	113	SCIF1, SCIF2, SIM, HSPI } },
	114	{ 0xfe08000c, 0, 32, 4, /* INTPRI0C */ { 0, 0, MMCIF, 0,
	115	MFI, 0, ADC, CMT } },
e29bfbc4 MD	116	};
	117
	118	static DECLARE_INTC_DESC(intc_desc, "sh7760", vectors, groups,
7f3edee8	119	mask_registers, prio_registers, NULL);
e29bfbc4	120
5c37e025	121	static struct intc_vect vectors_irq[] __initdata = {
e29bfbc4 MD	122	INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
	123	INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
	124	};
	125
	126	static DECLARE_INTC_DESC(intc_desc_irq, "sh7760-irq", vectors_irq, groups,
7f3edee8	127	mask_registers, prio_registers, NULL);
e29bfbc4	128
cd5f1076 MD	129	static struct plat_sci_port scif0_platform_data = {
	130	.mapbase = 0xfe600000,
	131	.flags = UPF_BOOT_AUTOCONF,
	132	.type = PORT_SCIF,
	133	.irqs = { 52, 53, 55, 54 },
	134	};
	135
	136	static struct platform_device scif0_device = {
	137	.name = "sh-sci",
	138	.id = 0,
	139	.dev = {
	140	.platform_data = &scif0_platform_data,
	141	},
	142	};
	143
	144	static struct plat_sci_port scif1_platform_data = {
	145	.mapbase = 0xfe610000,
	146	.flags = UPF_BOOT_AUTOCONF,
	147	.type = PORT_SCIF,
	148	.irqs = { 72, 73, 75, 74 },
	149	};
	150
	151	static struct platform_device scif1_device = {
	152	.name = "sh-sci",
	153	.id = 1,
	154	.dev = {
	155	.platform_data = &scif1_platform_data,
	156	},
	157	};
	158
	159	static struct plat_sci_port scif2_platform_data = {
	160	.mapbase = 0xfe620000,
	161	.flags = UPF_BOOT_AUTOCONF,
	162	.type = PORT_SCIF,
	163	.irqs = { 76, 77, 79, 78 },
	164	};
	165
	166	static struct platform_device scif2_device = {
	167	.name = "sh-sci",
	168	.id = 2,
	169	.dev = {
	170	.platform_data = &scif2_platform_data,
	171	},
	172	};
	173
	174	static struct plat_sci_port scif3_platform_data = {
	175	.mapbase = 0xfe480000,
	176	.flags = UPF_BOOT_AUTOCONF,
	177	.type = PORT_SCI,
	178	.irqs = { 80, 81, 82, 0 },
7dec62e9 PM	179	};
7dec62e9 PM	180
cd5f1076	181	static struct platform_device scif3_device = {
7dec62e9	182	.name = "sh-sci",
cd5f1076	183	.id = 3,
7dec62e9	184	.dev = {
cd5f1076	185	.platform_data = &scif3_platform_data,
7dec62e9 PM	186	},
	187	};
	188
c42f32dc	189	static struct sh_timer_config tmu0_platform_data = {
c42f32dc MD	190	.channel_offset = 0x04,
c42f32dc MD	191	.timer_bit = 0,
c42f32dc MD	192	.clockevent_rating = 200,
	193	};
	194
	195	static struct resource tmu0_resources[] = {
	196	[0] = {
c42f32dc MD	197	.start = 0xffd80008,
	198	.end = 0xffd80013,
	199	.flags = IORESOURCE_MEM,
	200	},
	201	[1] = {
	202	.start = 16,
	203	.flags = IORESOURCE_IRQ,
	204	},
	205	};
	206
	207	static struct platform_device tmu0_device = {
	208	.name = "sh_tmu",
	209	.id = 0,
	210	.dev = {
	211	.platform_data = &tmu0_platform_data,
	212	},
	213	.resource = tmu0_resources,
	214	.num_resources = ARRAY_SIZE(tmu0_resources),
	215	};
	216
	217	static struct sh_timer_config tmu1_platform_data = {
c42f32dc MD	218	.channel_offset = 0x10,
c42f32dc MD	219	.timer_bit = 1,
c42f32dc MD	220	.clocksource_rating = 200,
	221	};
	222
	223	static struct resource tmu1_resources[] = {
	224	[0] = {
c42f32dc MD	225	.start = 0xffd80014,
	226	.end = 0xffd8001f,
	227	.flags = IORESOURCE_MEM,
	228	},
	229	[1] = {
	230	.start = 17,
	231	.flags = IORESOURCE_IRQ,
	232	},
	233	};
	234
	235	static struct platform_device tmu1_device = {
	236	.name = "sh_tmu",
	237	.id = 1,
	238	.dev = {
	239	.platform_data = &tmu1_platform_data,
	240	},
	241	.resource = tmu1_resources,
	242	.num_resources = ARRAY_SIZE(tmu1_resources),
	243	};
	244
	245	static struct sh_timer_config tmu2_platform_data = {
c42f32dc MD	246	.channel_offset = 0x1c,
c42f32dc MD	247	.timer_bit = 2,
c42f32dc MD	248	};
	249
	250	static struct resource tmu2_resources[] = {
	251	[0] = {
c42f32dc MD	252	.start = 0xffd80020,
	253	.end = 0xffd8002f,
	254	.flags = IORESOURCE_MEM,
	255	},
	256	[1] = {
	257	.start = 18,
	258	.flags = IORESOURCE_IRQ,
	259	},
	260	};
	261
	262	static struct platform_device tmu2_device = {
	263	.name = "sh_tmu",
	264	.id = 2,
	265	.dev = {
	266	.platform_data = &tmu2_platform_data,
	267	},
	268	.resource = tmu2_resources,
	269	.num_resources = ARRAY_SIZE(tmu2_resources),
	270	};
	271
	272
7dec62e9	273	static struct platform_device *sh7760_devices[] __initdata = {
cd5f1076 MD	274	&scif0_device,
	275	&scif1_device,
	276	&scif2_device,
	277	&scif3_device,
c42f32dc MD	278	&tmu0_device,
	279	&tmu1_device,
	280	&tmu2_device,
7dec62e9 PM	281	};
	282
	283	static int __init sh7760_devices_setup(void)
	284	{
	285	return platform_add_devices(sh7760_devices,
	286	ARRAY_SIZE(sh7760_devices));
	287	}
ba9a6337	288	arch_initcall(sh7760_devices_setup);
66a74057	289
c42f32dc	290	static struct platform_device *sh7760_early_devices[] __initdata = {
cd5f1076 MD	291	&scif0_device,
	292	&scif1_device,
	293	&scif2_device,
	294	&scif3_device,
c42f32dc MD	295	&tmu0_device,
	296	&tmu1_device,
	297	&tmu2_device,
	298	};
	299
	300	void __init plat_early_device_setup(void)
	301	{
	302	early_platform_add_devices(sh7760_early_devices,
	303	ARRAY_SIZE(sh7760_early_devices));
	304	}
	305
53abf911 LS	306	#define INTC_ICR 0xffd00000UL
	307	#define INTC_ICR_IRLM (1 << 7)
	308
e29bfbc4 MD	309	void __init plat_irq_setup_pins(int mode)
	310	{
	311	switch (mode) {
	312	case IRQ_MODE_IRQ:
9d56dd3b	313	__raw_writew(__raw_readw(INTC_ICR) \| INTC_ICR_IRLM, INTC_ICR);
e29bfbc4 MD	314	register_intc_controller(&intc_desc_irq);
	315	break;
	316	default:
	317	BUG();
	318	}
	319	}
6dcda6f1	320
90015c89	321	void __init plat_irq_setup(void)
6dcda6f1	322	{
e29bfbc4	323	register_intc_controller(&intc_desc);
6dcda6f1	324	}