[linux-2.6-block.git] / arch / sh / kernel / cpu / sh2a / setup-sh7206.c

/*
 * SH7206 Setup
 *
 *  Copyright (C) 2006  Yoshinori Sato
 *  Copyright (C) 2009  Paul Mundt
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/platform_device.h>
#include <linux/init.h>
#include <linux/serial.h>
#include <linux/serial_sci.h>
#include <linux/sh_timer.h>
#include <linux/io.h>

enum {
	UNUSED = 0,

	/* interrupt sources */
	IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
	PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
	ADC_ADI0, ADC_ADI1,

	DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7,

	MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU,
	MTU3_ABCD, MTU4_ABCD, MTU5, POE2_12, MTU3S_ABCD, MTU4S_ABCD, MTU5S,
	IIC3,

	CMT0, CMT1, BSC, WDT,

	MTU2_TCI3V, MTU2_TCI4V, MTU2S_TCI3V, MTU2S_TCI4V,

	POE2_OEI3,

	SCIF0, SCIF1, SCIF2, SCIF3,

	/* interrupt groups */
	PINT,
};

static struct intc_vect vectors[] __initdata = {
	INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
	INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
	INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
	INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
	INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
	INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
	INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
	INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
	INTC_IRQ(ADC_ADI0, 92), INTC_IRQ(ADC_ADI1, 96),
	INTC_IRQ(DMAC0, 108), INTC_IRQ(DMAC0, 109),
	INTC_IRQ(DMAC1, 112), INTC_IRQ(DMAC1, 113),
	INTC_IRQ(DMAC2, 116), INTC_IRQ(DMAC2, 117),
	INTC_IRQ(DMAC3, 120), INTC_IRQ(DMAC3, 121),
	INTC_IRQ(DMAC4, 124), INTC_IRQ(DMAC4, 125),
	INTC_IRQ(DMAC5, 128), INTC_IRQ(DMAC5, 129),
	INTC_IRQ(DMAC6, 132), INTC_IRQ(DMAC6, 133),
	INTC_IRQ(DMAC7, 136), INTC_IRQ(DMAC7, 137),
	INTC_IRQ(CMT0, 140), INTC_IRQ(CMT1, 144),
	INTC_IRQ(BSC, 148), INTC_IRQ(WDT, 152),
	INTC_IRQ(MTU0_ABCD, 156), INTC_IRQ(MTU0_ABCD, 157),
	INTC_IRQ(MTU0_ABCD, 158), INTC_IRQ(MTU0_ABCD, 159),
	INTC_IRQ(MTU0_VEF, 160), INTC_IRQ(MTU0_VEF, 161),
	INTC_IRQ(MTU0_VEF, 162),
	INTC_IRQ(MTU1_AB, 164), INTC_IRQ(MTU1_AB, 165),
	INTC_IRQ(MTU1_VU, 168), INTC_IRQ(MTU1_VU, 169),
	INTC_IRQ(MTU2_AB, 172), INTC_IRQ(MTU2_AB, 173),
	INTC_IRQ(MTU2_VU, 176), INTC_IRQ(MTU2_VU, 177),
	INTC_IRQ(MTU3_ABCD, 180), INTC_IRQ(MTU3_ABCD, 181),
	INTC_IRQ(MTU3_ABCD, 182), INTC_IRQ(MTU3_ABCD, 183),
	INTC_IRQ(MTU2_TCI3V, 184),
	INTC_IRQ(MTU4_ABCD, 188), INTC_IRQ(MTU4_ABCD, 189),
	INTC_IRQ(MTU4_ABCD, 190), INTC_IRQ(MTU4_ABCD, 191),
	INTC_IRQ(MTU2_TCI4V, 192),
	INTC_IRQ(MTU5, 196), INTC_IRQ(MTU5, 197),
	INTC_IRQ(MTU5, 198),
	INTC_IRQ(POE2_12, 200), INTC_IRQ(POE2_12, 201),
	INTC_IRQ(MTU3S_ABCD, 204), INTC_IRQ(MTU3S_ABCD, 205),
	INTC_IRQ(MTU3S_ABCD, 206), INTC_IRQ(MTU3S_ABCD, 207),
	INTC_IRQ(MTU2S_TCI3V, 208),
	INTC_IRQ(MTU4S_ABCD, 212), INTC_IRQ(MTU4S_ABCD, 213),
	INTC_IRQ(MTU4S_ABCD, 214), INTC_IRQ(MTU4S_ABCD, 215),
	INTC_IRQ(MTU2S_TCI4V, 216),
	INTC_IRQ(MTU5S, 220), INTC_IRQ(MTU5S, 221),
	INTC_IRQ(MTU5S, 222),
	INTC_IRQ(POE2_OEI3, 224),
	INTC_IRQ(IIC3, 228), INTC_IRQ(IIC3, 229),
	INTC_IRQ(IIC3, 230), INTC_IRQ(IIC3, 231),
	INTC_IRQ(IIC3, 232),
	INTC_IRQ(SCIF0, 240), INTC_IRQ(SCIF0, 241),
	INTC_IRQ(SCIF0, 242), INTC_IRQ(SCIF0, 243),
	INTC_IRQ(SCIF1, 244), INTC_IRQ(SCIF1, 245),
	INTC_IRQ(SCIF1, 246), INTC_IRQ(SCIF1, 247),
	INTC_IRQ(SCIF2, 248), INTC_IRQ(SCIF2, 249),
	INTC_IRQ(SCIF2, 250), INTC_IRQ(SCIF2, 251),
	INTC_IRQ(SCIF3, 252), INTC_IRQ(SCIF3, 253),
	INTC_IRQ(SCIF3, 254), INTC_IRQ(SCIF3, 255),
};

static struct intc_group groups[] __initdata = {
	INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
		   PINT4, PINT5, PINT6, PINT7),
};

static struct intc_prio_reg prio_registers[] __initdata = {
	{ 0xfffe0818, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
	{ 0xfffe081a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
	{ 0xfffe0820, 0, 16, 4, /* IPR05 */ { PINT, 0, ADC_ADI0, ADC_ADI1 } },
	{ 0xfffe0c00, 0, 16, 4, /* IPR06 */ { DMAC0, DMAC1, DMAC2, DMAC3 } },
	{ 0xfffe0c02, 0, 16, 4, /* IPR07 */ { DMAC4, DMAC5, DMAC6, DMAC7 } },
	{ 0xfffe0c04, 0, 16, 4, /* IPR08 */ { CMT0, CMT1, BSC, WDT } },
	{ 0xfffe0c06, 0, 16, 4, /* IPR09 */ { MTU0_ABCD, MTU0_VEF,
					      MTU1_AB, MTU1_VU } },
	{ 0xfffe0c08, 0, 16, 4, /* IPR10 */ { MTU2_AB, MTU2_VU,
					      MTU3_ABCD, MTU2_TCI3V } },
	{ 0xfffe0c0a, 0, 16, 4, /* IPR11 */ { MTU4_ABCD, MTU2_TCI4V,
					      MTU5, POE2_12 } },
	{ 0xfffe0c0c, 0, 16, 4, /* IPR12 */ { MTU3S_ABCD, MTU2S_TCI3V,
					      MTU4S_ABCD, MTU2S_TCI4V } },
	{ 0xfffe0c0e, 0, 16, 4, /* IPR13 */ { MTU5S, POE2_OEI3, IIC3, 0 } },
	{ 0xfffe0c10, 0, 16, 4, /* IPR14 */ { SCIF0, SCIF1, SCIF2, SCIF3 } },
};

static struct intc_mask_reg mask_registers[] __initdata = {
	{ 0xfffe0808, 0, 16, /* PINTER */
	  { 0, 0, 0, 0, 0, 0, 0, 0,
	    PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
};

static DECLARE_INTC_DESC(intc_desc, "sh7206", vectors, groups,
			 mask_registers, prio_registers, NULL);

static struct plat_sci_port scif0_platform_data = {
	.mapbase	= 0xfffe8000,
	.flags		= UPF_BOOT_AUTOCONF,
	.type		= PORT_SCIF,
	.irqs		= { 240, 240, 240, 240 },
};

static struct platform_device scif0_device = {
	.name		= "sh-sci",
	.id		= 0,
	.dev		= {
		.platform_data	= &scif0_platform_data,
	},
};

static struct plat_sci_port scif1_platform_data = {
	.mapbase	= 0xfffe8800,
	.flags		= UPF_BOOT_AUTOCONF,
	.type		= PORT_SCIF,
	.irqs		= { 244, 244, 244, 244 },
};

static struct platform_device scif1_device = {
	.name		= "sh-sci",
	.id		= 1,
	.dev		= {
		.platform_data	= &scif1_platform_data,
	},
};

static struct plat_sci_port scif2_platform_data = {
	.mapbase	= 0xfffe9000,
	.flags		= UPF_BOOT_AUTOCONF,
	.type		= PORT_SCIF,
	.irqs		= { 248, 248, 248, 248 },
};

static struct platform_device scif2_device = {
	.name		= "sh-sci",
	.id		= 2,
	.dev		= {
		.platform_data	= &scif2_platform_data,
	},
};

static struct plat_sci_port scif3_platform_data = {
	.mapbase	= 0xfffe9800,
	.flags		= UPF_BOOT_AUTOCONF,
	.type		= PORT_SCIF,
	.irqs		= { 252, 252, 252, 252 },
};

static struct platform_device scif3_device = {
	.name		= "sh-sci",
	.id		= 3,
	.dev		= {
		.platform_data	= &scif3_platform_data,
	},
};

static struct sh_timer_config cmt0_platform_data = {
	.channel_offset = 0x02,
	.timer_bit = 0,
	.clockevent_rating = 125,
	.clocksource_rating = 0, /* disabled due to code generation issues */
};

static struct resource cmt0_resources[] = {
	[0] = {
		.start	= 0xfffec002,
		.end	= 0xfffec007,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= 140,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device cmt0_device = {
	.name		= "sh_cmt",
	.id		= 0,
	.dev = {
		.platform_data	= &cmt0_platform_data,
	},
	.resource	= cmt0_resources,
	.num_resources	= ARRAY_SIZE(cmt0_resources),
};

static struct sh_timer_config cmt1_platform_data = {
	.channel_offset = 0x08,
	.timer_bit = 1,
	.clockevent_rating = 125,
	.clocksource_rating = 0, /* disabled due to code generation issues */
};

static struct resource cmt1_resources[] = {
	[0] = {
		.start	= 0xfffec008,
		.end	= 0xfffec00d,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= 144,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device cmt1_device = {
	.name		= "sh_cmt",
	.id		= 1,
	.dev = {
		.platform_data	= &cmt1_platform_data,
	},
	.resource	= cmt1_resources,
	.num_resources	= ARRAY_SIZE(cmt1_resources),
};

static struct sh_timer_config mtu2_0_platform_data = {
	.channel_offset = -0x80,
	.timer_bit = 0,
	.clockevent_rating = 200,
};

static struct resource mtu2_0_resources[] = {
	[0] = {
		.start	= 0xfffe4300,
		.end	= 0xfffe4326,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= 156,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device mtu2_0_device = {
	.name		= "sh_mtu2",
	.id		= 0,
	.dev = {
		.platform_data	= &mtu2_0_platform_data,
	},
	.resource	= mtu2_0_resources,
	.num_resources	= ARRAY_SIZE(mtu2_0_resources),
};

static struct sh_timer_config mtu2_1_platform_data = {
	.channel_offset = -0x100,
	.timer_bit = 1,
	.clockevent_rating = 200,
};

static struct resource mtu2_1_resources[] = {
	[0] = {
		.start	= 0xfffe4380,
		.end	= 0xfffe4390,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= 164,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device mtu2_1_device = {
	.name		= "sh_mtu2",
	.id		= 1,
	.dev = {
		.platform_data	= &mtu2_1_platform_data,
	},
	.resource	= mtu2_1_resources,
	.num_resources	= ARRAY_SIZE(mtu2_1_resources),
};

static struct sh_timer_config mtu2_2_platform_data = {
	.channel_offset = 0x80,
	.timer_bit = 2,
	.clockevent_rating = 200,
};

static struct resource mtu2_2_resources[] = {
	[0] = {
		.start	= 0xfffe4000,
		.end	= 0xfffe400a,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= 180,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device mtu2_2_device = {
	.name		= "sh_mtu2",
	.id		= 2,
	.dev = {
		.platform_data	= &mtu2_2_platform_data,
	},
	.resource	= mtu2_2_resources,
	.num_resources	= ARRAY_SIZE(mtu2_2_resources),
};

static struct platform_device *sh7206_devices[] __initdata = {
	&scif0_device,
	&scif1_device,
	&scif2_device,
	&scif3_device,
	&cmt0_device,
	&cmt1_device,
	&mtu2_0_device,
	&mtu2_1_device,
	&mtu2_2_device,
};

static int __init sh7206_devices_setup(void)
{
	return platform_add_devices(sh7206_devices,
				    ARRAY_SIZE(sh7206_devices));
}
arch_initcall(sh7206_devices_setup);

void __init plat_irq_setup(void)
{
	register_intc_controller(&intc_desc);
}

static struct platform_device *sh7206_early_devices[] __initdata = {
	&scif0_device,
	&scif1_device,
	&scif2_device,
	&scif3_device,
	&cmt0_device,
	&cmt1_device,
	&mtu2_0_device,
	&mtu2_1_device,
	&mtu2_2_device,
};

#define STBCR3 0xfffe0408
#define STBCR4 0xfffe040c

void __init plat_early_device_setup(void)
{
	/* enable CMT clock */
	__raw_writeb(__raw_readb(STBCR4) & ~0x04, STBCR4);

	/* enable MTU2 clock */
	__raw_writeb(__raw_readb(STBCR3) & ~0x20, STBCR3);

	early_platform_add_devices(sh7206_early_devices,
				   ARRAY_SIZE(sh7206_early_devices));
}
Commit	Line	Data
9d4436a6 YS	1	/*
	2	* SH7206 Setup
	3	*
	4	* Copyright (C) 2006 Yoshinori Sato
f858abbe	5	* Copyright (C) 2009 Paul Mundt
9d4436a6 YS	6	*
	7	* This file is subject to the terms and conditions of the GNU General Public
	8	* License. See the file "COPYING" in the main directory of this archive
	9	* for more details.
	10	*/
	11	#include <linux/platform_device.h>
	12	#include <linux/init.h>
	13	#include <linux/serial.h>
96de1a8f	14	#include <linux/serial_sci.h>
46a12f74	15	#include <linux/sh_timer.h>
698aa99d	16	#include <linux/io.h>
9d4436a6	17
2eb0303c MD	18	enum {
	19	UNUSED = 0,
	20
	21	/* interrupt sources */
	22	IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
	23	PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
	24	ADC_ADI0, ADC_ADI1,
f858abbe PM	25
	26	DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7,
	27
	28	MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU,
	29	MTU3_ABCD, MTU4_ABCD, MTU5, POE2_12, MTU3S_ABCD, MTU4S_ABCD, MTU5S,
	30	IIC3,
	31
2eb0303c	32	CMT0, CMT1, BSC, WDT,
f858abbe PM	33
	34	MTU2_TCI3V, MTU2_TCI4V, MTU2S_TCI3V, MTU2S_TCI4V,
	35
2eb0303c	36	POE2_OEI3,
f858abbe PM	37
f858abbe PM	38	SCIF0, SCIF1, SCIF2, SCIF3,
2eb0303c MD	39
2eb0303c MD	40	/* interrupt groups */
f858abbe	41	PINT,
2eb0303c MD	42	};
	43
	44	static struct intc_vect vectors[] __initdata = {
	45	INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
	46	INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
	47	INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
	48	INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
	49	INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
	50	INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
	51	INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
	52	INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
	53	INTC_IRQ(ADC_ADI0, 92), INTC_IRQ(ADC_ADI1, 96),
f858abbe PM	54	INTC_IRQ(DMAC0, 108), INTC_IRQ(DMAC0, 109),
	55	INTC_IRQ(DMAC1, 112), INTC_IRQ(DMAC1, 113),
	56	INTC_IRQ(DMAC2, 116), INTC_IRQ(DMAC2, 117),
	57	INTC_IRQ(DMAC3, 120), INTC_IRQ(DMAC3, 121),
	58	INTC_IRQ(DMAC4, 124), INTC_IRQ(DMAC4, 125),
	59	INTC_IRQ(DMAC5, 128), INTC_IRQ(DMAC5, 129),
	60	INTC_IRQ(DMAC6, 132), INTC_IRQ(DMAC6, 133),
	61	INTC_IRQ(DMAC7, 136), INTC_IRQ(DMAC7, 137),
2eb0303c MD	62	INTC_IRQ(CMT0, 140), INTC_IRQ(CMT1, 144),
2eb0303c MD	63	INTC_IRQ(BSC, 148), INTC_IRQ(WDT, 152),
f858abbe PM	64	INTC_IRQ(MTU0_ABCD, 156), INTC_IRQ(MTU0_ABCD, 157),
	65	INTC_IRQ(MTU0_ABCD, 158), INTC_IRQ(MTU0_ABCD, 159),
	66	INTC_IRQ(MTU0_VEF, 160), INTC_IRQ(MTU0_VEF, 161),
	67	INTC_IRQ(MTU0_VEF, 162),
	68	INTC_IRQ(MTU1_AB, 164), INTC_IRQ(MTU1_AB, 165),
	69	INTC_IRQ(MTU1_VU, 168), INTC_IRQ(MTU1_VU, 169),
	70	INTC_IRQ(MTU2_AB, 172), INTC_IRQ(MTU2_AB, 173),
	71	INTC_IRQ(MTU2_VU, 176), INTC_IRQ(MTU2_VU, 177),
	72	INTC_IRQ(MTU3_ABCD, 180), INTC_IRQ(MTU3_ABCD, 181),
	73	INTC_IRQ(MTU3_ABCD, 182), INTC_IRQ(MTU3_ABCD, 183),
2eb0303c	74	INTC_IRQ(MTU2_TCI3V, 184),
f858abbe PM	75	INTC_IRQ(MTU4_ABCD, 188), INTC_IRQ(MTU4_ABCD, 189),
f858abbe PM	76	INTC_IRQ(MTU4_ABCD, 190), INTC_IRQ(MTU4_ABCD, 191),
2eb0303c	77	INTC_IRQ(MTU2_TCI4V, 192),
f858abbe PM	78	INTC_IRQ(MTU5, 196), INTC_IRQ(MTU5, 197),
	79	INTC_IRQ(MTU5, 198),
	80	INTC_IRQ(POE2_12, 200), INTC_IRQ(POE2_12, 201),
	81	INTC_IRQ(MTU3S_ABCD, 204), INTC_IRQ(MTU3S_ABCD, 205),
	82	INTC_IRQ(MTU3S_ABCD, 206), INTC_IRQ(MTU3S_ABCD, 207),
2eb0303c	83	INTC_IRQ(MTU2S_TCI3V, 208),
f858abbe PM	84	INTC_IRQ(MTU4S_ABCD, 212), INTC_IRQ(MTU4S_ABCD, 213),
f858abbe PM	85	INTC_IRQ(MTU4S_ABCD, 214), INTC_IRQ(MTU4S_ABCD, 215),
2eb0303c	86	INTC_IRQ(MTU2S_TCI4V, 216),
f858abbe PM	87	INTC_IRQ(MTU5S, 220), INTC_IRQ(MTU5S, 221),
f858abbe PM	88	INTC_IRQ(MTU5S, 222),
2eb0303c	89	INTC_IRQ(POE2_OEI3, 224),
f858abbe PM	90	INTC_IRQ(IIC3, 228), INTC_IRQ(IIC3, 229),
	91	INTC_IRQ(IIC3, 230), INTC_IRQ(IIC3, 231),
	92	INTC_IRQ(IIC3, 232),
	93	INTC_IRQ(SCIF0, 240), INTC_IRQ(SCIF0, 241),
	94	INTC_IRQ(SCIF0, 242), INTC_IRQ(SCIF0, 243),
	95	INTC_IRQ(SCIF1, 244), INTC_IRQ(SCIF1, 245),
	96	INTC_IRQ(SCIF1, 246), INTC_IRQ(SCIF1, 247),
	97	INTC_IRQ(SCIF2, 248), INTC_IRQ(SCIF2, 249),
	98	INTC_IRQ(SCIF2, 250), INTC_IRQ(SCIF2, 251),
	99	INTC_IRQ(SCIF3, 252), INTC_IRQ(SCIF3, 253),
	100	INTC_IRQ(SCIF3, 254), INTC_IRQ(SCIF3, 255),
2eb0303c MD	101	};
	102
	103	static struct intc_group groups[] __initdata = {
	104	INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
	105	PINT4, PINT5, PINT6, PINT7),
2eb0303c MD	106	};
	107
	108	static struct intc_prio_reg prio_registers[] __initdata = {
	109	{ 0xfffe0818, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
	110	{ 0xfffe081a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
	111	{ 0xfffe0820, 0, 16, 4, /* IPR05 */ { PINT, 0, ADC_ADI0, ADC_ADI1 } },
	112	{ 0xfffe0c00, 0, 16, 4, /* IPR06 */ { DMAC0, DMAC1, DMAC2, DMAC3 } },
	113	{ 0xfffe0c02, 0, 16, 4, /* IPR07 */ { DMAC4, DMAC5, DMAC6, DMAC7 } },
	114	{ 0xfffe0c04, 0, 16, 4, /* IPR08 */ { CMT0, CMT1, BSC, WDT } },
	115	{ 0xfffe0c06, 0, 16, 4, /* IPR09 */ { MTU0_ABCD, MTU0_VEF,
	116	MTU1_AB, MTU1_VU } },
	117	{ 0xfffe0c08, 0, 16, 4, /* IPR10 */ { MTU2_AB, MTU2_VU,
	118	MTU3_ABCD, MTU2_TCI3V } },
	119	{ 0xfffe0c0a, 0, 16, 4, /* IPR11 */ { MTU4_ABCD, MTU2_TCI4V,
	120	MTU5, POE2_12 } },
	121	{ 0xfffe0c0c, 0, 16, 4, /* IPR12 */ { MTU3S_ABCD, MTU2S_TCI3V,
	122	MTU4S_ABCD, MTU2S_TCI4V } },
	123	{ 0xfffe0c0e, 0, 16, 4, /* IPR13 */ { MTU5S, POE2_OEI3, IIC3, 0 } },
	124	{ 0xfffe0c10, 0, 16, 4, /* IPR14 */ { SCIF0, SCIF1, SCIF2, SCIF3 } },
	125	};
	126
	127	static struct intc_mask_reg mask_registers[] __initdata = {
	128	{ 0xfffe0808, 0, 16, /* PINTER */
	129	{ 0, 0, 0, 0, 0, 0, 0, 0,
	130	PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
	131	};
	132
	133	static DECLARE_INTC_DESC(intc_desc, "sh7206", vectors, groups,
7f3edee8	134	mask_registers, prio_registers, NULL);
2eb0303c	135
be091d20 MD	136	static struct plat_sci_port scif0_platform_data = {
	137	.mapbase = 0xfffe8000,
	138	.flags = UPF_BOOT_AUTOCONF,
	139	.type = PORT_SCIF,
	140	.irqs = { 240, 240, 240, 240 },
9d4436a6 YS	141	};
9d4436a6 YS	142
be091d20	143	static struct platform_device scif0_device = {
9d4436a6	144	.name = "sh-sci",
be091d20 MD	145	.id = 0,
	146	.dev = {
	147	.platform_data = &scif0_platform_data,
	148	},
	149	};
	150
	151	static struct plat_sci_port scif1_platform_data = {
	152	.mapbase = 0xfffe8800,
	153	.flags = UPF_BOOT_AUTOCONF,
	154	.type = PORT_SCIF,
	155	.irqs = { 244, 244, 244, 244 },
	156	};
	157
	158	static struct platform_device scif1_device = {
	159	.name = "sh-sci",
	160	.id = 1,
	161	.dev = {
	162	.platform_data = &scif1_platform_data,
	163	},
	164	};
	165
	166	static struct plat_sci_port scif2_platform_data = {
	167	.mapbase = 0xfffe9000,
	168	.flags = UPF_BOOT_AUTOCONF,
	169	.type = PORT_SCIF,
	170	.irqs = { 248, 248, 248, 248 },
	171	};
	172
	173	static struct platform_device scif2_device = {
	174	.name = "sh-sci",
	175	.id = 2,
	176	.dev = {
	177	.platform_data = &scif2_platform_data,
	178	},
	179	};
	180
	181	static struct plat_sci_port scif3_platform_data = {
	182	.mapbase = 0xfffe9800,
	183	.flags = UPF_BOOT_AUTOCONF,
	184	.type = PORT_SCIF,
	185	.irqs = { 252, 252, 252, 252 },
	186	};
	187
	188	static struct platform_device scif3_device = {
	189	.name = "sh-sci",
	190	.id = 3,
9d4436a6	191	.dev = {
be091d20	192	.platform_data = &scif3_platform_data,
9d4436a6 YS	193	},
	194	};
	195
46a12f74	196	static struct sh_timer_config cmt0_platform_data = {
698aa99d MD	197	.channel_offset = 0x02,
698aa99d MD	198	.timer_bit = 0,
698aa99d MD	199	.clockevent_rating = 125,
	200	.clocksource_rating = 0, /* disabled due to code generation issues */
	201	};
	202
	203	static struct resource cmt0_resources[] = {
	204	[0] = {
698aa99d MD	205	.start = 0xfffec002,
	206	.end = 0xfffec007,
	207	.flags = IORESOURCE_MEM,
	208	},
	209	[1] = {
	210	.start = 140,
	211	.flags = IORESOURCE_IRQ,
	212	},
	213	};
	214
	215	static struct platform_device cmt0_device = {
	216	.name = "sh_cmt",
	217	.id = 0,
	218	.dev = {
	219	.platform_data = &cmt0_platform_data,
	220	},
	221	.resource = cmt0_resources,
	222	.num_resources = ARRAY_SIZE(cmt0_resources),
	223	};
	224
46a12f74	225	static struct sh_timer_config cmt1_platform_data = {
698aa99d MD	226	.channel_offset = 0x08,
698aa99d MD	227	.timer_bit = 1,
698aa99d MD	228	.clockevent_rating = 125,
	229	.clocksource_rating = 0, /* disabled due to code generation issues */
	230	};
	231
	232	static struct resource cmt1_resources[] = {
	233	[0] = {
698aa99d MD	234	.start = 0xfffec008,
	235	.end = 0xfffec00d,
	236	.flags = IORESOURCE_MEM,
	237	},
	238	[1] = {
	239	.start = 144,
	240	.flags = IORESOURCE_IRQ,
	241	},
	242	};
	243
	244	static struct platform_device cmt1_device = {
	245	.name = "sh_cmt",
	246	.id = 1,
	247	.dev = {
	248	.platform_data = &cmt1_platform_data,
	249	},
	250	.resource = cmt1_resources,
	251	.num_resources = ARRAY_SIZE(cmt1_resources),
	252	};
	253
46a12f74	254	static struct sh_timer_config mtu2_0_platform_data = {
da107c6e MD	255	.channel_offset = -0x80,
da107c6e MD	256	.timer_bit = 0,
da107c6e MD	257	.clockevent_rating = 200,
	258	};
	259
	260	static struct resource mtu2_0_resources[] = {
	261	[0] = {
da107c6e MD	262	.start = 0xfffe4300,
	263	.end = 0xfffe4326,
	264	.flags = IORESOURCE_MEM,
	265	},
	266	[1] = {
	267	.start = 156,
	268	.flags = IORESOURCE_IRQ,
	269	},
	270	};
	271
	272	static struct platform_device mtu2_0_device = {
	273	.name = "sh_mtu2",
	274	.id = 0,
	275	.dev = {
	276	.platform_data = &mtu2_0_platform_data,
	277	},
	278	.resource = mtu2_0_resources,
	279	.num_resources = ARRAY_SIZE(mtu2_0_resources),
	280	};
	281
46a12f74	282	static struct sh_timer_config mtu2_1_platform_data = {
da107c6e MD	283	.channel_offset = -0x100,
da107c6e MD	284	.timer_bit = 1,
da107c6e MD	285	.clockevent_rating = 200,
	286	};
	287
	288	static struct resource mtu2_1_resources[] = {
	289	[0] = {
da107c6e MD	290	.start = 0xfffe4380,
	291	.end = 0xfffe4390,
	292	.flags = IORESOURCE_MEM,
	293	},
	294	[1] = {
	295	.start = 164,
	296	.flags = IORESOURCE_IRQ,
	297	},
	298	};
	299
	300	static struct platform_device mtu2_1_device = {
	301	.name = "sh_mtu2",
	302	.id = 1,
	303	.dev = {
	304	.platform_data = &mtu2_1_platform_data,
	305	},
	306	.resource = mtu2_1_resources,
	307	.num_resources = ARRAY_SIZE(mtu2_1_resources),
	308	};
	309
46a12f74	310	static struct sh_timer_config mtu2_2_platform_data = {
da107c6e MD	311	.channel_offset = 0x80,
da107c6e MD	312	.timer_bit = 2,
da107c6e MD	313	.clockevent_rating = 200,
	314	};
	315
	316	static struct resource mtu2_2_resources[] = {
	317	[0] = {
da107c6e MD	318	.start = 0xfffe4000,
	319	.end = 0xfffe400a,
	320	.flags = IORESOURCE_MEM,
	321	},
	322	[1] = {
	323	.start = 180,
	324	.flags = IORESOURCE_IRQ,
	325	},
	326	};
	327
	328	static struct platform_device mtu2_2_device = {
	329	.name = "sh_mtu2",
	330	.id = 2,
	331	.dev = {
	332	.platform_data = &mtu2_2_platform_data,
	333	},
	334	.resource = mtu2_2_resources,
	335	.num_resources = ARRAY_SIZE(mtu2_2_resources),
	336	};
	337
9d4436a6	338	static struct platform_device *sh7206_devices[] __initdata = {
be091d20 MD	339	&scif0_device,
	340	&scif1_device,
	341	&scif2_device,
	342	&scif3_device,
698aa99d MD	343	&cmt0_device,
698aa99d MD	344	&cmt1_device,
da107c6e MD	345	&mtu2_0_device,
	346	&mtu2_1_device,
	347	&mtu2_2_device,
9d4436a6 YS	348	};
	349
	350	static int __init sh7206_devices_setup(void)
	351	{
	352	return platform_add_devices(sh7206_devices,
	353	ARRAY_SIZE(sh7206_devices));
	354	}
ba9a6337	355	arch_initcall(sh7206_devices_setup);
780a1568	356
90015c89	357	void __init plat_irq_setup(void)
780a1568	358	{
2eb0303c	359	register_intc_controller(&intc_desc);
780a1568	360	}
698aa99d MD	361
698aa99d MD	362	static struct platform_device *sh7206_early_devices[] __initdata = {
be091d20 MD	363	&scif0_device,
	364	&scif1_device,
	365	&scif2_device,
	366	&scif3_device,
698aa99d MD	367	&cmt0_device,
698aa99d MD	368	&cmt1_device,
da107c6e MD	369	&mtu2_0_device,
	370	&mtu2_1_device,
	371	&mtu2_2_device,
698aa99d MD	372	};
698aa99d MD	373
da107c6e	374	#define STBCR3 0xfffe0408
698aa99d MD	375	#define STBCR4 0xfffe040c
	376
	377	void __init plat_early_device_setup(void)
	378	{
	379	/* enable CMT clock */
	380	__raw_writeb(__raw_readb(STBCR4) & ~0x04, STBCR4);
	381
da107c6e MD	382	/* enable MTU2 clock */
	383	__raw_writeb(__raw_readb(STBCR3) & ~0x20, STBCR3);
	384
698aa99d MD	385	early_platform_add_devices(sh7206_early_devices,
	386	ARRAY_SIZE(sh7206_early_devices));
	387	}