[linux-2.6-block.git] / arch / powerpc / sysdev / xics / xics-common.c

/*
 * Copyright 2011 IBM Corporation.
 *
 *  This program is free software; you can redistribute it and/or
 *  modify it under the terms of the GNU General Public License
 *  as published by the Free Software Foundation; either version
 *  2 of the License, or (at your option) any later version.
 *
 */
#include <linux/types.h>
#include <linux/threads.h>
#include <linux/kernel.h>
#include <linux/irq.h>
#include <linux/debugfs.h>
#include <linux/smp.h>
#include <linux/interrupt.h>
#include <linux/seq_file.h>
#include <linux/init.h>
#include <linux/cpu.h>
#include <linux/of.h>
#include <linux/slab.h>
#include <linux/spinlock.h>

#include <asm/prom.h>
#include <asm/io.h>
#include <asm/smp.h>
#include <asm/machdep.h>
#include <asm/irq.h>
#include <asm/errno.h>
#include <asm/rtas.h>
#include <asm/xics.h>
#include <asm/firmware.h>

/* Globals common to all ICP/ICS implementations */
const struct icp_ops	*icp_ops;

unsigned int xics_default_server		= 0xff;
unsigned int xics_default_distrib_server	= 0;
unsigned int xics_interrupt_server_size		= 8;

DEFINE_PER_CPU(struct xics_cppr, xics_cppr);

struct irq_domain *xics_host;

static LIST_HEAD(ics_list);

void xics_update_irq_servers(void)
{
	int i, j;
	struct device_node *np;
	u32 ilen;
	const __be32 *ireg;
	u32 hcpuid;

	/* Find the server numbers for the boot cpu. */
	np = of_get_cpu_node(boot_cpuid, NULL);
	BUG_ON(!np);

	hcpuid = get_hard_smp_processor_id(boot_cpuid);
	xics_default_server = xics_default_distrib_server = hcpuid;

	pr_devel("xics: xics_default_server = 0x%x\n", xics_default_server);

	ireg = of_get_property(np, "ibm,ppc-interrupt-gserver#s", &ilen);
	if (!ireg) {
		of_node_put(np);
		return;
	}

	i = ilen / sizeof(int);

	/* Global interrupt distribution server is specified in the last
	 * entry of "ibm,ppc-interrupt-gserver#s" property. Get the last
	 * entry fom this property for current boot cpu id and use it as
	 * default distribution server
	 */
	for (j = 0; j < i; j += 2) {
		if (be32_to_cpu(ireg[j]) == hcpuid) {
			xics_default_distrib_server = be32_to_cpu(ireg[j+1]);
			break;
		}
	}
	pr_devel("xics: xics_default_distrib_server = 0x%x\n",
		 xics_default_distrib_server);
	of_node_put(np);
}

/* GIQ stuff, currently only supported on RTAS setups, will have
 * to be sorted properly for bare metal
 */
void xics_set_cpu_giq(unsigned int gserver, unsigned int join)
{
#ifdef CONFIG_PPC_RTAS
	int index;
	int status;

	if (!rtas_indicator_present(GLOBAL_INTERRUPT_QUEUE, NULL))
		return;

	index = (1UL << xics_interrupt_server_size) - 1 - gserver;

	status = rtas_set_indicator_fast(GLOBAL_INTERRUPT_QUEUE, index, join);

	WARN(status < 0, "set-indicator(%d, %d, %u) returned %d\n",
	     GLOBAL_INTERRUPT_QUEUE, index, join, status);
#endif
}

void xics_setup_cpu(void)
{
	icp_ops->set_priority(LOWEST_PRIORITY);

	xics_set_cpu_giq(xics_default_distrib_server, 1);
}

void xics_mask_unknown_vec(unsigned int vec)
{
	struct ics *ics;

	pr_err("Interrupt 0x%x (real) is invalid, disabling it.\n", vec);

	list_for_each_entry(ics, &ics_list, link)
		ics->mask_unknown(ics, vec);
}


#ifdef CONFIG_SMP

static void xics_request_ipi(void)
{
	unsigned int ipi;

	ipi = irq_create_mapping(xics_host, XICS_IPI);
	BUG_ON(ipi == NO_IRQ);

	/*
	 * IPIs are marked IRQF_PERCPU. The handler was set in map.
	 */
	BUG_ON(request_irq(ipi, icp_ops->ipi_action,
			   IRQF_PERCPU | IRQF_NO_THREAD, "IPI", NULL));
}

void __init xics_smp_probe(void)
{
	/* Setup cause_ipi callback  based on which ICP is used */
	smp_ops->cause_ipi = icp_ops->cause_ipi;

	/* Register all the IPIs */
	xics_request_ipi();
}

#endif /* CONFIG_SMP */

void xics_teardown_cpu(void)
{
	struct xics_cppr *os_cppr = this_cpu_ptr(&xics_cppr);

	/*
	 * we have to reset the cppr index to 0 because we're
	 * not going to return from the IPI
	 */
	os_cppr->index = 0;
	icp_ops->set_priority(0);
	icp_ops->teardown_cpu();
}

void xics_kexec_teardown_cpu(int secondary)
{
	xics_teardown_cpu();

	icp_ops->flush_ipi();

	/*
	 * Some machines need to have at least one cpu in the GIQ,
	 * so leave the master cpu in the group.
	 */
	if (secondary)
		xics_set_cpu_giq(xics_default_distrib_server, 0);
}


#ifdef CONFIG_HOTPLUG_CPU

/* Interrupts are disabled. */
void xics_migrate_irqs_away(void)
{
	int cpu = smp_processor_id(), hw_cpu = hard_smp_processor_id();
	unsigned int irq, virq;
	struct irq_desc *desc;

	/* If we used to be the default server, move to the new "boot_cpuid" */
	if (hw_cpu == xics_default_server)
		xics_update_irq_servers();

	/* Reject any interrupt that was queued to us... */
	icp_ops->set_priority(0);

	/* Remove ourselves from the global interrupt queue */
	xics_set_cpu_giq(xics_default_distrib_server, 0);

	/* Allow IPIs again... */
	icp_ops->set_priority(DEFAULT_PRIORITY);

	for_each_irq_desc(virq, desc) {
		struct irq_chip *chip;
		long server;
		unsigned long flags;
		struct ics *ics;

		/* We can't set affinity on ISA interrupts */
		if (virq < NUM_ISA_INTERRUPTS)
			continue;
		/* We only need to migrate enabled IRQS */
		if (!desc->action)
			continue;
		if (desc->irq_data.domain != xics_host)
			continue;
		irq = desc->irq_data.hwirq;
		/* We need to get IPIs still. */
		if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS)
			continue;
		chip = irq_desc_get_chip(desc);
		if (!chip || !chip->irq_set_affinity)
			continue;

		raw_spin_lock_irqsave(&desc->lock, flags);

		/* Locate interrupt server */
		server = -1;
		ics = irq_desc_get_chip_data(desc);
		if (ics)
			server = ics->get_server(ics, irq);
		if (server < 0) {
			printk(KERN_ERR "%s: Can't find server for irq %d\n",
			       __func__, irq);
			goto unlock;
		}

		/* We only support delivery to all cpus or to one cpu.
		 * The irq has to be migrated only in the single cpu
		 * case.
		 */
		if (server != hw_cpu)
			goto unlock;

		/* This is expected during cpu offline. */
		if (cpu_online(cpu))
			pr_warning("IRQ %u affinity broken off cpu %u\n",
			       virq, cpu);

		/* Reset affinity to all cpus */
		raw_spin_unlock_irqrestore(&desc->lock, flags);
		irq_set_affinity(virq, cpu_all_mask);
		continue;
unlock:
		raw_spin_unlock_irqrestore(&desc->lock, flags);
	}
}
#endif /* CONFIG_HOTPLUG_CPU */

#ifdef CONFIG_SMP
/*
 * For the moment we only implement delivery to all cpus or one cpu.
 *
 * If the requested affinity is cpu_all_mask, we set global affinity.
 * If not we set it to the first cpu in the mask, even if multiple cpus
 * are set. This is so things like irqbalance (which set core and package
 * wide affinities) do the right thing.
 *
 * We need to fix this to implement support for the links
 */
int xics_get_irq_server(unsigned int virq, const struct cpumask *cpumask,
			unsigned int strict_check)
{

	if (!distribute_irqs)
		return xics_default_server;

	if (!cpumask_subset(cpu_possible_mask, cpumask)) {
		int server = cpumask_first_and(cpu_online_mask, cpumask);

		if (server < nr_cpu_ids)
			return get_hard_smp_processor_id(server);

		if (strict_check)
			return -1;
	}

	/*
	 * Workaround issue with some versions of JS20 firmware that
	 * deliver interrupts to cpus which haven't been started. This
	 * happens when using the maxcpus= boot option.
	 */
	if (cpumask_equal(cpu_online_mask, cpu_present_mask))
		return xics_default_distrib_server;

	return xics_default_server;
}
#endif /* CONFIG_SMP */

static int xics_host_match(struct irq_domain *h, struct device_node *node,
			   enum irq_domain_bus_token bus_token)
{
	struct ics *ics;

	list_for_each_entry(ics, &ics_list, link)
		if (ics->host_match(ics, node))
			return 1;

	return 0;
}

/* Dummies */
static void xics_ipi_unmask(struct irq_data *d) { }
static void xics_ipi_mask(struct irq_data *d) { }

static struct irq_chip xics_ipi_chip = {
	.name = "XICS",
	.irq_eoi = NULL, /* Patched at init time */
	.irq_mask = xics_ipi_mask,
	.irq_unmask = xics_ipi_unmask,
};

static int xics_host_map(struct irq_domain *h, unsigned int virq,
			 irq_hw_number_t hw)
{
	struct ics *ics;

	pr_devel("xics: map virq %d, hwirq 0x%lx\n", virq, hw);

	/*
	 * Mark interrupts as edge sensitive by default so that resend
	 * actually works. The device-tree parsing will turn the LSIs
	 * back to level.
	 */
	irq_clear_status_flags(virq, IRQ_LEVEL);

	/* Don't call into ICS for IPIs */
	if (hw == XICS_IPI) {
		irq_set_chip_and_handler(virq, &xics_ipi_chip,
					 handle_percpu_irq);
		return 0;
	}

	/* Let the ICS setup the chip data */
	list_for_each_entry(ics, &ics_list, link)
		if (ics->map(ics, virq) == 0)
			return 0;

	return -EINVAL;
}

static int xics_host_xlate(struct irq_domain *h, struct device_node *ct,
			   const u32 *intspec, unsigned int intsize,
			   irq_hw_number_t *out_hwirq, unsigned int *out_flags)

{
	*out_hwirq = intspec[0];

	/*
	 * If intsize is at least 2, we look for the type in the second cell,
	 * we assume the LSB indicates a level interrupt.
	 */
	if (intsize > 1) {
		if (intspec[1] & 1)
			*out_flags = IRQ_TYPE_LEVEL_LOW;
		else
			*out_flags = IRQ_TYPE_EDGE_RISING;
	} else
		*out_flags = IRQ_TYPE_LEVEL_LOW;

	return 0;
}

int xics_set_irq_type(struct irq_data *d, unsigned int flow_type)
{
	/*
	 * We only support these. This has really no effect other than setting
	 * the corresponding descriptor bits mind you but those will in turn
	 * affect the resend function when re-enabling an edge interrupt.
	 *
	 * Set set the default to edge as explained in map().
	 */
	if (flow_type == IRQ_TYPE_DEFAULT || flow_type == IRQ_TYPE_NONE)
		flow_type = IRQ_TYPE_EDGE_RISING;

	if (flow_type != IRQ_TYPE_EDGE_RISING &&
	    flow_type != IRQ_TYPE_LEVEL_LOW)
		return -EINVAL;

	irqd_set_trigger_type(d, flow_type);

	return IRQ_SET_MASK_OK_NOCOPY;
}

int xics_retrigger(struct irq_data *data)
{
	/*
	 * We need to push a dummy CPPR when retriggering, since the subsequent
	 * EOI will try to pop it. Passing 0 works, as the function hard codes
	 * the priority value anyway.
	 */
	xics_push_cppr(0);

	/* Tell the core to do a soft retrigger */
	return 0;
}

static const struct irq_domain_ops xics_host_ops = {
	.match = xics_host_match,
	.map = xics_host_map,
	.xlate = xics_host_xlate,
};

static void __init xics_init_host(void)
{
	xics_host = irq_domain_add_tree(NULL, &xics_host_ops, NULL);
	BUG_ON(xics_host == NULL);
	irq_set_default_host(xics_host);
}

void __init xics_register_ics(struct ics *ics)
{
	list_add(&ics->link, &ics_list);
}

static void __init xics_get_server_size(void)
{
	struct device_node *np;
	const __be32 *isize;

	/* We fetch the interrupt server size from the first ICS node
	 * we find if any
	 */
	np = of_find_compatible_node(NULL, NULL, "ibm,ppc-xics");
	if (!np)
		return;
	isize = of_get_property(np, "ibm,interrupt-server#-size", NULL);
	if (!isize)
		return;
	xics_interrupt_server_size = be32_to_cpu(*isize);
	of_node_put(np);
}

void __init xics_init(void)
{
	int rc = -1;

	/* Fist locate ICP */
	if (firmware_has_feature(FW_FEATURE_LPAR))
		rc = icp_hv_init();
	if (rc < 0) {
		rc = icp_native_init();
		if (rc == -ENODEV)
		    rc = icp_opal_init();
	}
	if (rc < 0) {
		pr_warning("XICS: Cannot find a Presentation Controller !\n");
		return;
	}

	/* Copy get_irq callback over to ppc_md */
	ppc_md.get_irq = icp_ops->get_irq;

	/* Patch up IPI chip EOI */
	xics_ipi_chip.irq_eoi = icp_ops->eoi;

	/* Now locate ICS */
	rc = ics_rtas_init();
	if (rc < 0)
		rc = ics_opal_init();
	if (rc < 0)
		pr_warning("XICS: Cannot find a Source Controller !\n");

	/* Initialize common bits */
	xics_get_server_size();
	xics_update_irq_servers();
	xics_init_host();
	xics_setup_cpu();
}
Commit	Line	Data
0b05ac6e BH	1	/*
	2	* Copyright 2011 IBM Corporation.
	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License
	6	* as published by the Free Software Foundation; either version
	7	* 2 of the License, or (at your option) any later version.
	8	*
	9	*/
	10	#include <linux/types.h>
	11	#include <linux/threads.h>
	12	#include <linux/kernel.h>
	13	#include <linux/irq.h>
	14	#include <linux/debugfs.h>
	15	#include <linux/smp.h>
	16	#include <linux/interrupt.h>
	17	#include <linux/seq_file.h>
	18	#include <linux/init.h>
	19	#include <linux/cpu.h>
	20	#include <linux/of.h>
	21	#include <linux/slab.h>
	22	#include <linux/spinlock.h>
	23
	24	#include <asm/prom.h>
	25	#include <asm/io.h>
	26	#include <asm/smp.h>
	27	#include <asm/machdep.h>
	28	#include <asm/irq.h>
	29	#include <asm/errno.h>
	30	#include <asm/rtas.h>
	31	#include <asm/xics.h>
	32	#include <asm/firmware.h>
	33
	34	/* Globals common to all ICP/ICS implementations */
	35	const struct icp_ops *icp_ops;
	36
	37	unsigned int xics_default_server = 0xff;
	38	unsigned int xics_default_distrib_server = 0;
	39	unsigned int xics_interrupt_server_size = 8;
	40
	41	DEFINE_PER_CPU(struct xics_cppr, xics_cppr);
	42
bae1d8f1	43	struct irq_domain *xics_host;
0b05ac6e BH	44
	45	static LIST_HEAD(ics_list);
	46
	47	void xics_update_irq_servers(void)
	48	{
	49	int i, j;
	50	struct device_node *np;
	51	u32 ilen;
d213dd53	52	const __be32 *ireg;
0b05ac6e BH	53	u32 hcpuid;
	54
	55	/* Find the server numbers for the boot cpu. */
	56	np = of_get_cpu_node(boot_cpuid, NULL);
	57	BUG_ON(!np);
	58
	59	hcpuid = get_hard_smp_processor_id(boot_cpuid);
f6e17f9b BH	60	xics_default_server = xics_default_distrib_server = hcpuid;
	61
	62	pr_devel("xics: xics_default_server = 0x%x\n", xics_default_server);
0b05ac6e BH	63
	64	ireg = of_get_property(np, "ibm,ppc-interrupt-gserver#s", &ilen);
	65	if (!ireg) {
	66	of_node_put(np);
	67	return;
	68	}
	69
	70	i = ilen / sizeof(int);
	71
	72	/* Global interrupt distribution server is specified in the last
	73	* entry of "ibm,ppc-interrupt-gserver#s" property. Get the last
	74	* entry fom this property for current boot cpu id and use it as
	75	* default distribution server
	76	*/
	77	for (j = 0; j < i; j += 2) {
d213dd53 AB	78	if (be32_to_cpu(ireg[j]) == hcpuid) {
d213dd53 AB	79	xics_default_distrib_server = be32_to_cpu(ireg[j+1]);
f6e17f9b	80	break;
0b05ac6e BH	81	}
0b05ac6e BH	82	}
f6e17f9b BH	83	pr_devel("xics: xics_default_distrib_server = 0x%x\n",
f6e17f9b BH	84	xics_default_distrib_server);
0b05ac6e BH	85	of_node_put(np);
	86	}
	87
	88	/* GIQ stuff, currently only supported on RTAS setups, will have
	89	* to be sorted properly for bare metal
	90	*/
	91	void xics_set_cpu_giq(unsigned int gserver, unsigned int join)
	92	{
	93	#ifdef CONFIG_PPC_RTAS
	94	int index;
	95	int status;
	96
	97	if (!rtas_indicator_present(GLOBAL_INTERRUPT_QUEUE, NULL))
	98	return;
	99
	100	index = (1UL << xics_interrupt_server_size) - 1 - gserver;
	101
	102	status = rtas_set_indicator_fast(GLOBAL_INTERRUPT_QUEUE, index, join);
	103
	104	WARN(status < 0, "set-indicator(%d, %d, %u) returned %d\n",
	105	GLOBAL_INTERRUPT_QUEUE, index, join, status);
	106	#endif
	107	}
	108
	109	void xics_setup_cpu(void)
	110	{
	111	icp_ops->set_priority(LOWEST_PRIORITY);
	112
	113	xics_set_cpu_giq(xics_default_distrib_server, 1);
	114	}
	115
	116	void xics_mask_unknown_vec(unsigned int vec)
	117	{
	118	struct ics *ics;
	119
f6e17f9b	120	pr_err("Interrupt 0x%x (real) is invalid, disabling it.\n", vec);
0b05ac6e BH	121
	122	list_for_each_entry(ics, &ics_list, link)
	123	ics->mask_unknown(ics, vec);
	124	}
	125
	126
	127	#ifdef CONFIG_SMP
	128
0b05ac6e BH	129	static void xics_request_ipi(void)
	130	{
	131	unsigned int ipi;
	132
	133	ipi = irq_create_mapping(xics_host, XICS_IPI);
	134	BUG_ON(ipi == NO_IRQ);
	135
	136	/*
a3a9f3b4	137	* IPIs are marked IRQF_PERCPU. The handler was set in map.
0b05ac6e	138	*/
0b05ac6e	139	BUG_ON(request_irq(ipi, icp_ops->ipi_action,
3b5e16d7	140	IRQF_PERCPU \| IRQF_NO_THREAD, "IPI", NULL));
0b05ac6e BH	141	}
0b05ac6e BH	142
a7f4ee1f	143	void __init xics_smp_probe(void)
0b05ac6e	144	{
23d72bfd MM	145	/* Setup cause_ipi callback based on which ICP is used */
23d72bfd MM	146	smp_ops->cause_ipi = icp_ops->cause_ipi;
0b05ac6e BH	147
	148	/* Register all the IPIs */
	149	xics_request_ipi();
0b05ac6e BH	150	}
	151
	152	#endif /* CONFIG_SMP */
	153
	154	void xics_teardown_cpu(void)
	155	{
69111bac	156	struct xics_cppr *os_cppr = this_cpu_ptr(&xics_cppr);
0b05ac6e BH	157
	158	/*
	159	* we have to reset the cppr index to 0 because we're
	160	* not going to return from the IPI
	161	*/
	162	os_cppr->index = 0;
	163	icp_ops->set_priority(0);
	164	icp_ops->teardown_cpu();
	165	}
	166
	167	void xics_kexec_teardown_cpu(int secondary)
	168	{
	169	xics_teardown_cpu();
	170
	171	icp_ops->flush_ipi();
	172
	173	/*
	174	* Some machines need to have at least one cpu in the GIQ,
	175	* so leave the master cpu in the group.
	176	*/
	177	if (secondary)
	178	xics_set_cpu_giq(xics_default_distrib_server, 0);
	179	}
	180
	181
	182	#ifdef CONFIG_HOTPLUG_CPU
	183
	184	/* Interrupts are disabled. */
	185	void xics_migrate_irqs_away(void)
	186	{
	187	int cpu = smp_processor_id(), hw_cpu = hard_smp_processor_id();
	188	unsigned int irq, virq;
4013369f	189	struct irq_desc *desc;
0b05ac6e BH	190
	191	/* If we used to be the default server, move to the new "boot_cpuid" */
	192	if (hw_cpu == xics_default_server)
	193	xics_update_irq_servers();
	194
	195	/* Reject any interrupt that was queued to us... */
	196	icp_ops->set_priority(0);
	197
	198	/* Remove ourselves from the global interrupt queue */
	199	xics_set_cpu_giq(xics_default_distrib_server, 0);
	200
	201	/* Allow IPIs again... */
	202	icp_ops->set_priority(DEFAULT_PRIORITY);
	203
4013369f	204	for_each_irq_desc(virq, desc) {
0b05ac6e BH	205	struct irq_chip *chip;
	206	long server;
	207	unsigned long flags;
	208	struct ics *ics;
	209
	210	/* We can't set affinity on ISA interrupts */
	211	if (virq < NUM_ISA_INTERRUPTS)
	212	continue;
0b05ac6e	213	/* We only need to migrate enabled IRQS */
4013369f	214	if (!desc->action)
0b05ac6e	215	continue;
6d9285b0 GL	216	if (desc->irq_data.domain != xics_host)
	217	continue;
	218	irq = desc->irq_data.hwirq;
	219	/* We need to get IPIs still. */
	220	if (irq == XICS_IPI \|\| irq == XICS_IRQ_SPURIOUS)
	221	continue;
0b05ac6e BH	222	chip = irq_desc_get_chip(desc);
	223	if (!chip \|\| !chip->irq_set_affinity)
	224	continue;
	225
	226	raw_spin_lock_irqsave(&desc->lock, flags);
	227
	228	/* Locate interrupt server */
	229	server = -1;
c1231a78	230	ics = irq_desc_get_chip_data(desc);
0b05ac6e BH	231	if (ics)
	232	server = ics->get_server(ics, irq);
	233	if (server < 0) {
	234	printk(KERN_ERR "%s: Can't find server for irq %d\n",
	235	__func__, irq);
	236	goto unlock;
	237	}
	238
	239	/* We only support delivery to all cpus or to one cpu.
	240	* The irq has to be migrated only in the single cpu
	241	* case.
	242	*/
	243	if (server != hw_cpu)
	244	goto unlock;
	245
	246	/* This is expected during cpu offline. */
	247	if (cpu_online(cpu))
	248	pr_warning("IRQ %u affinity broken off cpu %u\n",
	249	virq, cpu);
	250
	251	/* Reset affinity to all cpus */
	252	raw_spin_unlock_irqrestore(&desc->lock, flags);
	253	irq_set_affinity(virq, cpu_all_mask);
	254	continue;
	255	unlock:
	256	raw_spin_unlock_irqrestore(&desc->lock, flags);
	257	}
	258	}
	259	#endif /* CONFIG_HOTPLUG_CPU */
	260
	261	#ifdef CONFIG_SMP
	262	/*
	263	* For the moment we only implement delivery to all cpus or one cpu.
	264	*
	265	* If the requested affinity is cpu_all_mask, we set global affinity.
	266	* If not we set it to the first cpu in the mask, even if multiple cpus
	267	* are set. This is so things like irqbalance (which set core and package
	268	* wide affinities) do the right thing.
f6e17f9b BH	269	*
f6e17f9b BH	270	* We need to fix this to implement support for the links
0b05ac6e BH	271	*/
	272	int xics_get_irq_server(unsigned int virq, const struct cpumask *cpumask,
	273	unsigned int strict_check)
	274	{
	275
	276	if (!distribute_irqs)
	277	return xics_default_server;
	278
	279	if (!cpumask_subset(cpu_possible_mask, cpumask)) {
	280	int server = cpumask_first_and(cpu_online_mask, cpumask);
	281
	282	if (server < nr_cpu_ids)
	283	return get_hard_smp_processor_id(server);
	284
	285	if (strict_check)
	286	return -1;
	287	}
	288
	289	/*
	290	* Workaround issue with some versions of JS20 firmware that
	291	* deliver interrupts to cpus which haven't been started. This
	292	* happens when using the maxcpus= boot option.
	293	*/
	294	if (cpumask_equal(cpu_online_mask, cpu_present_mask))
	295	return xics_default_distrib_server;
	296
	297	return xics_default_server;
	298	}
	299	#endif /* CONFIG_SMP */
	300
ad3aedfb MZ	301	static int xics_host_match(struct irq_domain h, struct device_node node,
ad3aedfb MZ	302	enum irq_domain_bus_token bus_token)
0b05ac6e	303	{
5ca12376 ME	304	struct ics *ics;
	305
	306	list_for_each_entry(ics, &ics_list, link)
	307	if (ics->host_match(ics, node))
	308	return 1;
	309
	310	return 0;
0b05ac6e BH	311	}
	312
	313	/* Dummies */
	314	static void xics_ipi_unmask(struct irq_data *d) { }
	315	static void xics_ipi_mask(struct irq_data *d) { }
	316
	317	static struct irq_chip xics_ipi_chip = {
	318	.name = "XICS",
	319	.irq_eoi = NULL, /* Patched at init time */
	320	.irq_mask = xics_ipi_mask,
	321	.irq_unmask = xics_ipi_unmask,
	322	};
	323
bae1d8f1	324	static int xics_host_map(struct irq_domain *h, unsigned int virq,
0b05ac6e BH	325	irq_hw_number_t hw)
	326	{
	327	struct ics *ics;
	328
	329	pr_devel("xics: map virq %d, hwirq 0x%lx\n", virq, hw);
	330
880a3d6a BH	331	/*
	332	* Mark interrupts as edge sensitive by default so that resend
	333	* actually works. The device-tree parsing will turn the LSIs
	334	* back to level.
	335	*/
	336	irq_clear_status_flags(virq, IRQ_LEVEL);
0b05ac6e BH	337
	338	/* Don't call into ICS for IPIs */
	339	if (hw == XICS_IPI) {
	340	irq_set_chip_and_handler(virq, &xics_ipi_chip,
e085255e	341	handle_percpu_irq);
0b05ac6e BH	342	return 0;
	343	}
	344
	345	/* Let the ICS setup the chip data */
	346	list_for_each_entry(ics, &ics_list, link)
	347	if (ics->map(ics, virq) == 0)
e085255e MM	348	return 0;
	349
	350	return -EINVAL;
0b05ac6e BH	351	}
0b05ac6e BH	352
bae1d8f1	353	static int xics_host_xlate(struct irq_domain h, struct device_node ct,
0b05ac6e BH	354	const u32 *intspec, unsigned int intsize,
	355	irq_hw_number_t out_hwirq, unsigned int out_flags)
	356
	357	{
0b05ac6e	358	*out_hwirq = intspec[0];
0b05ac6e	359
880a3d6a BH	360	/*
	361	* If intsize is at least 2, we look for the type in the second cell,
	362	* we assume the LSB indicates a level interrupt.
	363	*/
	364	if (intsize > 1) {
	365	if (intspec[1] & 1)
	366	*out_flags = IRQ_TYPE_LEVEL_LOW;
	367	else
	368	*out_flags = IRQ_TYPE_EDGE_RISING;
	369	} else
	370	*out_flags = IRQ_TYPE_LEVEL_LOW;
	371
	372	return 0;
	373	}
	374
	375	int xics_set_irq_type(struct irq_data *d, unsigned int flow_type)
	376	{
	377	/*
	378	* We only support these. This has really no effect other than setting
	379	* the corresponding descriptor bits mind you but those will in turn
	380	* affect the resend function when re-enabling an edge interrupt.
	381	*
	382	* Set set the default to edge as explained in map().
	383	*/
	384	if (flow_type == IRQ_TYPE_DEFAULT \|\| flow_type == IRQ_TYPE_NONE)
	385	flow_type = IRQ_TYPE_EDGE_RISING;
	386
	387	if (flow_type != IRQ_TYPE_EDGE_RISING &&
	388	flow_type != IRQ_TYPE_LEVEL_LOW)
	389	return -EINVAL;
	390
	391	irqd_set_trigger_type(d, flow_type);
	392
	393	return IRQ_SET_MASK_OK_NOCOPY;
	394	}
	395
	396	int xics_retrigger(struct irq_data *data)
	397	{
	398	/*
	399	* We need to push a dummy CPPR when retriggering, since the subsequent
	400	* EOI will try to pop it. Passing 0 works, as the function hard codes
	401	* the priority value anyway.
	402	*/
	403	xics_push_cppr(0);
	404
	405	/* Tell the core to do a soft retrigger */
0b05ac6e BH	406	return 0;
	407	}
	408
202648a6	409	static const struct irq_domain_ops xics_host_ops = {
0b05ac6e BH	410	.match = xics_host_match,
	411	.map = xics_host_map,
	412	.xlate = xics_host_xlate,
	413	};
	414
	415	static void __init xics_init_host(void)
	416	{
a8db8cf0	417	xics_host = irq_domain_add_tree(NULL, &xics_host_ops, NULL);
0b05ac6e BH	418	BUG_ON(xics_host == NULL);
	419	irq_set_default_host(xics_host);
	420	}
	421
	422	void __init xics_register_ics(struct ics *ics)
	423	{
	424	list_add(&ics->link, &ics_list);
	425	}
	426
	427	static void __init xics_get_server_size(void)
	428	{
	429	struct device_node *np;
d213dd53	430	const __be32 *isize;
0b05ac6e BH	431
	432	/* We fetch the interrupt server size from the first ICS node
	433	* we find if any
	434	*/
	435	np = of_find_compatible_node(NULL, NULL, "ibm,ppc-xics");
	436	if (!np)
	437	return;
	438	isize = of_get_property(np, "ibm,interrupt-server#-size", NULL);
	439	if (!isize)
	440	return;
d213dd53	441	xics_interrupt_server_size = be32_to_cpu(*isize);
0b05ac6e BH	442	of_node_put(np);
	443	}
	444
	445	void __init xics_init(void)
	446	{
	447	int rc = -1;
	448
	449	/* Fist locate ICP */
0b05ac6e BH	450	if (firmware_has_feature(FW_FEATURE_LPAR))
0b05ac6e BH	451	rc = icp_hv_init();
d7436188	452	if (rc < 0) {
0b05ac6e	453	rc = icp_native_init();
d7436188 BH	454	if (rc == -ENODEV)
	455	rc = icp_opal_init();
	456	}
0b05ac6e BH	457	if (rc < 0) {
	458	pr_warning("XICS: Cannot find a Presentation Controller !\n");
	459	return;
	460	}
	461
	462	/* Copy get_irq callback over to ppc_md */
	463	ppc_md.get_irq = icp_ops->get_irq;
	464
	465	/* Patch up IPI chip EOI */
	466	xics_ipi_chip.irq_eoi = icp_ops->eoi;
	467
	468	/* Now locate ICS */
0b05ac6e	469	rc = ics_rtas_init();
5c7c1e94 BH	470	if (rc < 0)
5c7c1e94 BH	471	rc = ics_opal_init();
0b05ac6e BH	472	if (rc < 0)
	473	pr_warning("XICS: Cannot find a Source Controller !\n");
	474
	475	/* Initialize common bits */
	476	xics_get_server_size();
	477	xics_update_irq_servers();
	478	xics_init_host();
	479	xics_setup_cpu();
	480	}