Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * PowerPC64 port by Mike Corrigan and Dave Engebretsen | |
3 | * {mikejc|engebret}@us.ibm.com | |
4 | * | |
5 | * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com> | |
6 | * | |
7 | * SMP scalability work: | |
8 | * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM | |
9 | * | |
10 | * Module name: htab.c | |
11 | * | |
12 | * Description: | |
13 | * PowerPC Hashed Page Table functions | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or | |
16 | * modify it under the terms of the GNU General Public License | |
17 | * as published by the Free Software Foundation; either version | |
18 | * 2 of the License, or (at your option) any later version. | |
19 | */ | |
20 | ||
21 | #undef DEBUG | |
3c726f8d | 22 | #undef DEBUG_LOW |
1da177e4 | 23 | |
1da177e4 LT |
24 | #include <linux/spinlock.h> |
25 | #include <linux/errno.h> | |
26 | #include <linux/sched.h> | |
27 | #include <linux/proc_fs.h> | |
28 | #include <linux/stat.h> | |
29 | #include <linux/sysctl.h> | |
66b15db6 | 30 | #include <linux/export.h> |
1da177e4 LT |
31 | #include <linux/ctype.h> |
32 | #include <linux/cache.h> | |
33 | #include <linux/init.h> | |
34 | #include <linux/signal.h> | |
95f72d1e | 35 | #include <linux/memblock.h> |
ba12eede | 36 | #include <linux/context_tracking.h> |
1da177e4 | 37 | |
1da177e4 LT |
38 | #include <asm/processor.h> |
39 | #include <asm/pgtable.h> | |
40 | #include <asm/mmu.h> | |
41 | #include <asm/mmu_context.h> | |
42 | #include <asm/page.h> | |
43 | #include <asm/types.h> | |
1da177e4 LT |
44 | #include <asm/uaccess.h> |
45 | #include <asm/machdep.h> | |
d9b2b2a2 | 46 | #include <asm/prom.h> |
1da177e4 LT |
47 | #include <asm/tlbflush.h> |
48 | #include <asm/io.h> | |
49 | #include <asm/eeh.h> | |
50 | #include <asm/tlb.h> | |
51 | #include <asm/cacheflush.h> | |
52 | #include <asm/cputable.h> | |
1da177e4 | 53 | #include <asm/sections.h> |
be3ebfe8 | 54 | #include <asm/copro.h> |
aa39be09 | 55 | #include <asm/udbg.h> |
b68a70c4 | 56 | #include <asm/code-patching.h> |
3ccc00a7 | 57 | #include <asm/fadump.h> |
f5339277 | 58 | #include <asm/firmware.h> |
bc2a9408 | 59 | #include <asm/tm.h> |
cfcb3d80 | 60 | #include <asm/trace.h> |
1da177e4 LT |
61 | |
62 | #ifdef DEBUG | |
63 | #define DBG(fmt...) udbg_printf(fmt) | |
64 | #else | |
65 | #define DBG(fmt...) | |
66 | #endif | |
67 | ||
3c726f8d BH |
68 | #ifdef DEBUG_LOW |
69 | #define DBG_LOW(fmt...) udbg_printf(fmt) | |
70 | #else | |
71 | #define DBG_LOW(fmt...) | |
72 | #endif | |
73 | ||
74 | #define KB (1024) | |
75 | #define MB (1024*KB) | |
658013e9 | 76 | #define GB (1024L*MB) |
3c726f8d | 77 | |
1da177e4 LT |
78 | /* |
79 | * Note: pte --> Linux PTE | |
80 | * HPTE --> PowerPC Hashed Page Table Entry | |
81 | * | |
82 | * Execution context: | |
83 | * htab_initialize is called with the MMU off (of course), but | |
84 | * the kernel has been copied down to zero so it can directly | |
85 | * reference global data. At this point it is very difficult | |
86 | * to print debug info. | |
87 | * | |
88 | */ | |
89 | ||
90 | #ifdef CONFIG_U3_DART | |
91 | extern unsigned long dart_tablebase; | |
92 | #endif /* CONFIG_U3_DART */ | |
93 | ||
799d6046 PM |
94 | static unsigned long _SDR1; |
95 | struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT]; | |
e1802b06 | 96 | EXPORT_SYMBOL_GPL(mmu_psize_defs); |
799d6046 | 97 | |
8e561e7e | 98 | struct hash_pte *htab_address; |
337a7128 | 99 | unsigned long htab_size_bytes; |
96e28449 | 100 | unsigned long htab_hash_mask; |
4ab79aa8 | 101 | EXPORT_SYMBOL_GPL(htab_hash_mask); |
3c726f8d | 102 | int mmu_linear_psize = MMU_PAGE_4K; |
8ca7a82f | 103 | EXPORT_SYMBOL_GPL(mmu_linear_psize); |
3c726f8d | 104 | int mmu_virtual_psize = MMU_PAGE_4K; |
bf72aeba | 105 | int mmu_vmalloc_psize = MMU_PAGE_4K; |
cec08e7a BH |
106 | #ifdef CONFIG_SPARSEMEM_VMEMMAP |
107 | int mmu_vmemmap_psize = MMU_PAGE_4K; | |
108 | #endif | |
bf72aeba | 109 | int mmu_io_psize = MMU_PAGE_4K; |
1189be65 | 110 | int mmu_kernel_ssize = MMU_SEGSIZE_256M; |
8ca7a82f | 111 | EXPORT_SYMBOL_GPL(mmu_kernel_ssize); |
1189be65 | 112 | int mmu_highuser_ssize = MMU_SEGSIZE_256M; |
584f8b71 | 113 | u16 mmu_slb_size = 64; |
4ab79aa8 | 114 | EXPORT_SYMBOL_GPL(mmu_slb_size); |
bf72aeba PM |
115 | #ifdef CONFIG_PPC_64K_PAGES |
116 | int mmu_ci_restrictions; | |
117 | #endif | |
370a908d BH |
118 | #ifdef CONFIG_DEBUG_PAGEALLOC |
119 | static u8 *linear_map_hash_slots; | |
120 | static unsigned long linear_map_hash_count; | |
ed166692 | 121 | static DEFINE_SPINLOCK(linear_map_hash_lock); |
370a908d | 122 | #endif /* CONFIG_DEBUG_PAGEALLOC */ |
1da177e4 | 123 | |
3c726f8d BH |
124 | /* There are definitions of page sizes arrays to be used when none |
125 | * is provided by the firmware. | |
126 | */ | |
1da177e4 | 127 | |
3c726f8d BH |
128 | /* Pre-POWER4 CPUs (4k pages only) |
129 | */ | |
09de9ff8 | 130 | static struct mmu_psize_def mmu_psize_defaults_old[] = { |
3c726f8d BH |
131 | [MMU_PAGE_4K] = { |
132 | .shift = 12, | |
133 | .sllp = 0, | |
b1022fbd | 134 | .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1}, |
3c726f8d BH |
135 | .avpnm = 0, |
136 | .tlbiel = 0, | |
137 | }, | |
138 | }; | |
139 | ||
140 | /* POWER4, GPUL, POWER5 | |
141 | * | |
142 | * Support for 16Mb large pages | |
143 | */ | |
09de9ff8 | 144 | static struct mmu_psize_def mmu_psize_defaults_gp[] = { |
3c726f8d BH |
145 | [MMU_PAGE_4K] = { |
146 | .shift = 12, | |
147 | .sllp = 0, | |
b1022fbd | 148 | .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1}, |
3c726f8d BH |
149 | .avpnm = 0, |
150 | .tlbiel = 1, | |
151 | }, | |
152 | [MMU_PAGE_16M] = { | |
153 | .shift = 24, | |
154 | .sllp = SLB_VSID_L, | |
b1022fbd AK |
155 | .penc = {[0 ... MMU_PAGE_16M - 1] = -1, [MMU_PAGE_16M] = 0, |
156 | [MMU_PAGE_16M + 1 ... MMU_PAGE_COUNT - 1] = -1 }, | |
3c726f8d BH |
157 | .avpnm = 0x1UL, |
158 | .tlbiel = 0, | |
159 | }, | |
160 | }; | |
161 | ||
dc47c0c1 AK |
162 | /* |
163 | * 'R' and 'C' update notes: | |
164 | * - Under pHyp or KVM, the updatepp path will not set C, thus it *will* | |
165 | * create writeable HPTEs without C set, because the hcall H_PROTECT | |
166 | * that we use in that case will not update C | |
167 | * - The above is however not a problem, because we also don't do that | |
168 | * fancy "no flush" variant of eviction and we use H_REMOVE which will | |
169 | * do the right thing and thus we don't have the race I described earlier | |
170 | * | |
171 | * - Under bare metal, we do have the race, so we need R and C set | |
172 | * - We make sure R is always set and never lost | |
173 | * - C is _PAGE_DIRTY, and *should* always be set for a writeable mapping | |
174 | */ | |
c6a3c495 | 175 | unsigned long htab_convert_pte_flags(unsigned long pteflags) |
bc033b63 | 176 | { |
c6a3c495 | 177 | unsigned long rflags = 0; |
bc033b63 BH |
178 | |
179 | /* _PAGE_EXEC -> NOEXEC */ | |
180 | if ((pteflags & _PAGE_EXEC) == 0) | |
181 | rflags |= HPTE_R_N; | |
c6a3c495 | 182 | /* |
e58e87ad | 183 | * PPP bits: |
1ec3f937 | 184 | * Linux uses slb key 0 for kernel and 1 for user. |
e58e87ad AK |
185 | * kernel RW areas are mapped with PPP=0b000 |
186 | * User area is mapped with PPP=0b010 for read/write | |
187 | * or PPP=0b011 for read-only (including writeable but clean pages). | |
bc033b63 | 188 | */ |
e58e87ad AK |
189 | if (pteflags & _PAGE_PRIVILEGED) { |
190 | /* | |
191 | * Kernel read only mapped with ppp bits 0b110 | |
192 | */ | |
193 | if (!(pteflags & _PAGE_WRITE)) | |
194 | rflags |= (HPTE_R_PP0 | 0x2); | |
195 | } else { | |
c7d54842 AK |
196 | if (pteflags & _PAGE_RWX) |
197 | rflags |= 0x2; | |
198 | if (!((pteflags & _PAGE_WRITE) && (pteflags & _PAGE_DIRTY))) | |
c6a3c495 AK |
199 | rflags |= 0x1; |
200 | } | |
c8c06f5a | 201 | /* |
dc47c0c1 AK |
202 | * We can't allow hardware to update hpte bits. Hence always |
203 | * set 'R' bit and set 'C' if it is a write fault | |
c8c06f5a | 204 | */ |
e568006b | 205 | rflags |= HPTE_R_R; |
dc47c0c1 AK |
206 | |
207 | if (pteflags & _PAGE_DIRTY) | |
208 | rflags |= HPTE_R_C; | |
40e8550a AK |
209 | /* |
210 | * Add in WIG bits | |
211 | */ | |
30bda41a AK |
212 | |
213 | if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_TOLERANT) | |
40e8550a | 214 | rflags |= HPTE_R_I; |
e568006b | 215 | else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_NON_IDEMPOTENT) |
30bda41a | 216 | rflags |= (HPTE_R_I | HPTE_R_G); |
e568006b AK |
217 | else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_SAO) |
218 | rflags |= (HPTE_R_W | HPTE_R_I | HPTE_R_M); | |
219 | else | |
220 | /* | |
221 | * Add memory coherence if cache inhibited is not set | |
222 | */ | |
223 | rflags |= HPTE_R_M; | |
40e8550a AK |
224 | |
225 | return rflags; | |
bc033b63 | 226 | } |
3c726f8d BH |
227 | |
228 | int htab_bolt_mapping(unsigned long vstart, unsigned long vend, | |
bc033b63 | 229 | unsigned long pstart, unsigned long prot, |
1189be65 | 230 | int psize, int ssize) |
1da177e4 | 231 | { |
3c726f8d BH |
232 | unsigned long vaddr, paddr; |
233 | unsigned int step, shift; | |
3c726f8d | 234 | int ret = 0; |
1da177e4 | 235 | |
3c726f8d BH |
236 | shift = mmu_psize_defs[psize].shift; |
237 | step = 1 << shift; | |
1da177e4 | 238 | |
bc033b63 BH |
239 | prot = htab_convert_pte_flags(prot); |
240 | ||
241 | DBG("htab_bolt_mapping(%lx..%lx -> %lx (%lx,%d,%d)\n", | |
242 | vstart, vend, pstart, prot, psize, ssize); | |
243 | ||
3c726f8d BH |
244 | for (vaddr = vstart, paddr = pstart; vaddr < vend; |
245 | vaddr += step, paddr += step) { | |
370a908d | 246 | unsigned long hash, hpteg; |
1189be65 | 247 | unsigned long vsid = get_kernel_vsid(vaddr, ssize); |
5524a27d | 248 | unsigned long vpn = hpt_vpn(vaddr, vsid, ssize); |
9e88ba4e PM |
249 | unsigned long tprot = prot; |
250 | ||
c60ac569 AK |
251 | /* |
252 | * If we hit a bad address return error. | |
253 | */ | |
254 | if (!vsid) | |
255 | return -1; | |
9e88ba4e | 256 | /* Make kernel text executable */ |
549e8152 | 257 | if (overlaps_kernel_text(vaddr, vaddr + step)) |
9e88ba4e | 258 | tprot &= ~HPTE_R_N; |
1da177e4 | 259 | |
b18db0b8 AG |
260 | /* Make kvm guest trampolines executable */ |
261 | if (overlaps_kvm_tmp(vaddr, vaddr + step)) | |
262 | tprot &= ~HPTE_R_N; | |
263 | ||
429d2e83 MS |
264 | /* |
265 | * If relocatable, check if it overlaps interrupt vectors that | |
266 | * are copied down to real 0. For relocatable kernel | |
267 | * (e.g. kdump case) we copy interrupt vectors down to real | |
268 | * address 0. Mark that region as executable. This is | |
269 | * because on p8 system with relocation on exception feature | |
270 | * enabled, exceptions are raised with MMU (IR=DR=1) ON. Hence | |
271 | * in order to execute the interrupt handlers in virtual | |
272 | * mode the vector region need to be marked as executable. | |
273 | */ | |
274 | if ((PHYSICAL_START > MEMORY_START) && | |
275 | overlaps_interrupt_vector_text(vaddr, vaddr + step)) | |
276 | tprot &= ~HPTE_R_N; | |
277 | ||
5524a27d | 278 | hash = hpt_hash(vpn, shift, ssize); |
1da177e4 LT |
279 | hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP); |
280 | ||
c30a4df3 | 281 | BUG_ON(!ppc_md.hpte_insert); |
5524a27d | 282 | ret = ppc_md.hpte_insert(hpteg, vpn, paddr, tprot, |
b1022fbd | 283 | HPTE_V_BOLTED, psize, psize, ssize); |
c30a4df3 | 284 | |
3c726f8d BH |
285 | if (ret < 0) |
286 | break; | |
e7df0d88 | 287 | |
370a908d | 288 | #ifdef CONFIG_DEBUG_PAGEALLOC |
e7df0d88 JK |
289 | if (debug_pagealloc_enabled() && |
290 | (paddr >> PAGE_SHIFT) < linear_map_hash_count) | |
370a908d BH |
291 | linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80; |
292 | #endif /* CONFIG_DEBUG_PAGEALLOC */ | |
3c726f8d BH |
293 | } |
294 | return ret < 0 ? ret : 0; | |
295 | } | |
1da177e4 | 296 | |
ed5694a8 | 297 | int htab_remove_mapping(unsigned long vstart, unsigned long vend, |
f8c8803b BP |
298 | int psize, int ssize) |
299 | { | |
300 | unsigned long vaddr; | |
301 | unsigned int step, shift; | |
27828f98 DG |
302 | int rc; |
303 | int ret = 0; | |
f8c8803b BP |
304 | |
305 | shift = mmu_psize_defs[psize].shift; | |
306 | step = 1 << shift; | |
307 | ||
abd0a0e7 DG |
308 | if (!ppc_md.hpte_removebolted) |
309 | return -ENODEV; | |
f8c8803b | 310 | |
27828f98 DG |
311 | for (vaddr = vstart; vaddr < vend; vaddr += step) { |
312 | rc = ppc_md.hpte_removebolted(vaddr, psize, ssize); | |
313 | if (rc == -ENOENT) { | |
314 | ret = -ENOENT; | |
315 | continue; | |
316 | } | |
317 | if (rc < 0) | |
318 | return rc; | |
319 | } | |
52db9b44 | 320 | |
27828f98 | 321 | return ret; |
f8c8803b BP |
322 | } |
323 | ||
1189be65 PM |
324 | static int __init htab_dt_scan_seg_sizes(unsigned long node, |
325 | const char *uname, int depth, | |
326 | void *data) | |
327 | { | |
9d0c4dfe RH |
328 | const char *type = of_get_flat_dt_prop(node, "device_type", NULL); |
329 | const __be32 *prop; | |
330 | int size = 0; | |
1189be65 PM |
331 | |
332 | /* We are scanning "cpu" nodes only */ | |
333 | if (type == NULL || strcmp(type, "cpu") != 0) | |
334 | return 0; | |
335 | ||
12f04f2b | 336 | prop = of_get_flat_dt_prop(node, "ibm,processor-segment-sizes", &size); |
1189be65 PM |
337 | if (prop == NULL) |
338 | return 0; | |
339 | for (; size >= 4; size -= 4, ++prop) { | |
12f04f2b | 340 | if (be32_to_cpu(prop[0]) == 40) { |
1189be65 | 341 | DBG("1T segment support detected\n"); |
44ae3ab3 | 342 | cur_cpu_spec->mmu_features |= MMU_FTR_1T_SEGMENT; |
f5534004 | 343 | return 1; |
1189be65 | 344 | } |
1189be65 | 345 | } |
44ae3ab3 | 346 | cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B; |
1189be65 PM |
347 | return 0; |
348 | } | |
349 | ||
350 | static void __init htab_init_seg_sizes(void) | |
351 | { | |
352 | of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL); | |
353 | } | |
354 | ||
b1022fbd AK |
355 | static int __init get_idx_from_shift(unsigned int shift) |
356 | { | |
357 | int idx = -1; | |
358 | ||
359 | switch (shift) { | |
360 | case 0xc: | |
361 | idx = MMU_PAGE_4K; | |
362 | break; | |
363 | case 0x10: | |
364 | idx = MMU_PAGE_64K; | |
365 | break; | |
366 | case 0x14: | |
367 | idx = MMU_PAGE_1M; | |
368 | break; | |
369 | case 0x18: | |
370 | idx = MMU_PAGE_16M; | |
371 | break; | |
372 | case 0x22: | |
373 | idx = MMU_PAGE_16G; | |
374 | break; | |
375 | } | |
376 | return idx; | |
377 | } | |
378 | ||
3c726f8d BH |
379 | static int __init htab_dt_scan_page_sizes(unsigned long node, |
380 | const char *uname, int depth, | |
381 | void *data) | |
382 | { | |
9d0c4dfe RH |
383 | const char *type = of_get_flat_dt_prop(node, "device_type", NULL); |
384 | const __be32 *prop; | |
385 | int size = 0; | |
3c726f8d BH |
386 | |
387 | /* We are scanning "cpu" nodes only */ | |
388 | if (type == NULL || strcmp(type, "cpu") != 0) | |
389 | return 0; | |
390 | ||
12f04f2b | 391 | prop = of_get_flat_dt_prop(node, "ibm,segment-page-sizes", &size); |
9e34992a ME |
392 | if (!prop) |
393 | return 0; | |
394 | ||
395 | pr_info("Page sizes from device-tree:\n"); | |
396 | size /= 4; | |
397 | cur_cpu_spec->mmu_features &= ~(MMU_FTR_16M_PAGE); | |
398 | while(size > 0) { | |
399 | unsigned int base_shift = be32_to_cpu(prop[0]); | |
400 | unsigned int slbenc = be32_to_cpu(prop[1]); | |
401 | unsigned int lpnum = be32_to_cpu(prop[2]); | |
402 | struct mmu_psize_def *def; | |
403 | int idx, base_idx; | |
404 | ||
405 | size -= 3; prop += 3; | |
406 | base_idx = get_idx_from_shift(base_shift); | |
407 | if (base_idx < 0) { | |
408 | /* skip the pte encoding also */ | |
409 | prop += lpnum * 2; size -= lpnum * 2; | |
410 | continue; | |
411 | } | |
412 | def = &mmu_psize_defs[base_idx]; | |
413 | if (base_idx == MMU_PAGE_16M) | |
414 | cur_cpu_spec->mmu_features |= MMU_FTR_16M_PAGE; | |
415 | ||
416 | def->shift = base_shift; | |
417 | if (base_shift <= 23) | |
418 | def->avpnm = 0; | |
419 | else | |
420 | def->avpnm = (1 << (base_shift - 23)) - 1; | |
421 | def->sllp = slbenc; | |
422 | /* | |
423 | * We don't know for sure what's up with tlbiel, so | |
424 | * for now we only set it for 4K and 64K pages | |
425 | */ | |
426 | if (base_idx == MMU_PAGE_4K || base_idx == MMU_PAGE_64K) | |
427 | def->tlbiel = 1; | |
428 | else | |
429 | def->tlbiel = 0; | |
430 | ||
431 | while (size > 0 && lpnum) { | |
432 | unsigned int shift = be32_to_cpu(prop[0]); | |
433 | int penc = be32_to_cpu(prop[1]); | |
434 | ||
435 | prop += 2; size -= 2; | |
436 | lpnum--; | |
437 | ||
438 | idx = get_idx_from_shift(shift); | |
439 | if (idx < 0) | |
b1022fbd | 440 | continue; |
9e34992a ME |
441 | |
442 | if (penc == -1) | |
443 | pr_err("Invalid penc for base_shift=%d " | |
444 | "shift=%d\n", base_shift, shift); | |
445 | ||
446 | def->penc[idx] = penc; | |
447 | pr_info("base_shift=%d: shift=%d, sllp=0x%04lx," | |
448 | " avpnm=0x%08lx, tlbiel=%d, penc=%d\n", | |
449 | base_shift, shift, def->sllp, | |
450 | def->avpnm, def->tlbiel, def->penc[idx]); | |
1da177e4 | 451 | } |
3c726f8d | 452 | } |
9e34992a ME |
453 | |
454 | return 1; | |
3c726f8d BH |
455 | } |
456 | ||
e16a9c09 | 457 | #ifdef CONFIG_HUGETLB_PAGE |
658013e9 JT |
458 | /* Scan for 16G memory blocks that have been set aside for huge pages |
459 | * and reserve those blocks for 16G huge pages. | |
460 | */ | |
461 | static int __init htab_dt_scan_hugepage_blocks(unsigned long node, | |
462 | const char *uname, int depth, | |
463 | void *data) { | |
9d0c4dfe RH |
464 | const char *type = of_get_flat_dt_prop(node, "device_type", NULL); |
465 | const __be64 *addr_prop; | |
466 | const __be32 *page_count_prop; | |
658013e9 JT |
467 | unsigned int expected_pages; |
468 | long unsigned int phys_addr; | |
469 | long unsigned int block_size; | |
470 | ||
471 | /* We are scanning "memory" nodes only */ | |
472 | if (type == NULL || strcmp(type, "memory") != 0) | |
473 | return 0; | |
474 | ||
475 | /* This property is the log base 2 of the number of virtual pages that | |
476 | * will represent this memory block. */ | |
477 | page_count_prop = of_get_flat_dt_prop(node, "ibm,expected#pages", NULL); | |
478 | if (page_count_prop == NULL) | |
479 | return 0; | |
12f04f2b | 480 | expected_pages = (1 << be32_to_cpu(page_count_prop[0])); |
658013e9 JT |
481 | addr_prop = of_get_flat_dt_prop(node, "reg", NULL); |
482 | if (addr_prop == NULL) | |
483 | return 0; | |
12f04f2b AB |
484 | phys_addr = be64_to_cpu(addr_prop[0]); |
485 | block_size = be64_to_cpu(addr_prop[1]); | |
658013e9 JT |
486 | if (block_size != (16 * GB)) |
487 | return 0; | |
488 | printk(KERN_INFO "Huge page(16GB) memory: " | |
489 | "addr = 0x%lX size = 0x%lX pages = %d\n", | |
490 | phys_addr, block_size, expected_pages); | |
95f72d1e YL |
491 | if (phys_addr + (16 * GB) <= memblock_end_of_DRAM()) { |
492 | memblock_reserve(phys_addr, block_size * expected_pages); | |
4792adba JT |
493 | add_gpage(phys_addr, block_size, expected_pages); |
494 | } | |
658013e9 JT |
495 | return 0; |
496 | } | |
e16a9c09 | 497 | #endif /* CONFIG_HUGETLB_PAGE */ |
658013e9 | 498 | |
b1022fbd AK |
499 | static void mmu_psize_set_default_penc(void) |
500 | { | |
501 | int bpsize, apsize; | |
502 | for (bpsize = 0; bpsize < MMU_PAGE_COUNT; bpsize++) | |
503 | for (apsize = 0; apsize < MMU_PAGE_COUNT; apsize++) | |
504 | mmu_psize_defs[bpsize].penc[apsize] = -1; | |
505 | } | |
506 | ||
9048e648 AG |
507 | #ifdef CONFIG_PPC_64K_PAGES |
508 | ||
509 | static bool might_have_hea(void) | |
510 | { | |
511 | /* | |
512 | * The HEA ethernet adapter requires awareness of the | |
513 | * GX bus. Without that awareness we can easily assume | |
514 | * we will never see an HEA ethernet device. | |
515 | */ | |
516 | #ifdef CONFIG_IBMEBUS | |
517 | return !cpu_has_feature(CPU_FTR_ARCH_207S); | |
518 | #else | |
519 | return false; | |
520 | #endif | |
521 | } | |
522 | ||
523 | #endif /* #ifdef CONFIG_PPC_64K_PAGES */ | |
524 | ||
3c726f8d BH |
525 | static void __init htab_init_page_sizes(void) |
526 | { | |
527 | int rc; | |
528 | ||
b1022fbd AK |
529 | /* se the invalid penc to -1 */ |
530 | mmu_psize_set_default_penc(); | |
531 | ||
3c726f8d BH |
532 | /* Default to 4K pages only */ |
533 | memcpy(mmu_psize_defs, mmu_psize_defaults_old, | |
534 | sizeof(mmu_psize_defaults_old)); | |
535 | ||
536 | /* | |
537 | * Try to find the available page sizes in the device-tree | |
538 | */ | |
539 | rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL); | |
540 | if (rc != 0) /* Found */ | |
541 | goto found; | |
542 | ||
543 | /* | |
544 | * Not in the device-tree, let's fallback on known size | |
545 | * list for 16M capable GP & GR | |
546 | */ | |
44ae3ab3 | 547 | if (mmu_has_feature(MMU_FTR_16M_PAGE)) |
3c726f8d BH |
548 | memcpy(mmu_psize_defs, mmu_psize_defaults_gp, |
549 | sizeof(mmu_psize_defaults_gp)); | |
e7df0d88 JK |
550 | found: |
551 | if (!debug_pagealloc_enabled()) { | |
552 | /* | |
553 | * Pick a size for the linear mapping. Currently, we only | |
554 | * support 16M, 1M and 4K which is the default | |
555 | */ | |
556 | if (mmu_psize_defs[MMU_PAGE_16M].shift) | |
557 | mmu_linear_psize = MMU_PAGE_16M; | |
558 | else if (mmu_psize_defs[MMU_PAGE_1M].shift) | |
559 | mmu_linear_psize = MMU_PAGE_1M; | |
560 | } | |
3c726f8d | 561 | |
bf72aeba | 562 | #ifdef CONFIG_PPC_64K_PAGES |
3c726f8d BH |
563 | /* |
564 | * Pick a size for the ordinary pages. Default is 4K, we support | |
bf72aeba PM |
565 | * 64K for user mappings and vmalloc if supported by the processor. |
566 | * We only use 64k for ioremap if the processor | |
567 | * (and firmware) support cache-inhibited large pages. | |
568 | * If not, we use 4k and set mmu_ci_restrictions so that | |
569 | * hash_page knows to switch processes that use cache-inhibited | |
570 | * mappings to 4k pages. | |
3c726f8d | 571 | */ |
bf72aeba | 572 | if (mmu_psize_defs[MMU_PAGE_64K].shift) { |
3c726f8d | 573 | mmu_virtual_psize = MMU_PAGE_64K; |
bf72aeba | 574 | mmu_vmalloc_psize = MMU_PAGE_64K; |
370a908d BH |
575 | if (mmu_linear_psize == MMU_PAGE_4K) |
576 | mmu_linear_psize = MMU_PAGE_64K; | |
44ae3ab3 | 577 | if (mmu_has_feature(MMU_FTR_CI_LARGE_PAGE)) { |
cfe666b1 | 578 | /* |
9048e648 AG |
579 | * When running on pSeries using 64k pages for ioremap |
580 | * would stop us accessing the HEA ethernet. So if we | |
581 | * have the chance of ever seeing one, stay at 4k. | |
cfe666b1 | 582 | */ |
9048e648 | 583 | if (!might_have_hea() || !machine_is(pseries)) |
cfe666b1 PM |
584 | mmu_io_psize = MMU_PAGE_64K; |
585 | } else | |
bf72aeba PM |
586 | mmu_ci_restrictions = 1; |
587 | } | |
370a908d | 588 | #endif /* CONFIG_PPC_64K_PAGES */ |
3c726f8d | 589 | |
cec08e7a BH |
590 | #ifdef CONFIG_SPARSEMEM_VMEMMAP |
591 | /* We try to use 16M pages for vmemmap if that is supported | |
592 | * and we have at least 1G of RAM at boot | |
593 | */ | |
594 | if (mmu_psize_defs[MMU_PAGE_16M].shift && | |
95f72d1e | 595 | memblock_phys_mem_size() >= 0x40000000) |
cec08e7a BH |
596 | mmu_vmemmap_psize = MMU_PAGE_16M; |
597 | else if (mmu_psize_defs[MMU_PAGE_64K].shift) | |
598 | mmu_vmemmap_psize = MMU_PAGE_64K; | |
599 | else | |
600 | mmu_vmemmap_psize = MMU_PAGE_4K; | |
601 | #endif /* CONFIG_SPARSEMEM_VMEMMAP */ | |
602 | ||
bf72aeba | 603 | printk(KERN_DEBUG "Page orders: linear mapping = %d, " |
cec08e7a BH |
604 | "virtual = %d, io = %d" |
605 | #ifdef CONFIG_SPARSEMEM_VMEMMAP | |
606 | ", vmemmap = %d" | |
607 | #endif | |
608 | "\n", | |
3c726f8d | 609 | mmu_psize_defs[mmu_linear_psize].shift, |
bf72aeba | 610 | mmu_psize_defs[mmu_virtual_psize].shift, |
cec08e7a BH |
611 | mmu_psize_defs[mmu_io_psize].shift |
612 | #ifdef CONFIG_SPARSEMEM_VMEMMAP | |
613 | ,mmu_psize_defs[mmu_vmemmap_psize].shift | |
614 | #endif | |
615 | ); | |
3c726f8d BH |
616 | |
617 | #ifdef CONFIG_HUGETLB_PAGE | |
658013e9 JT |
618 | /* Reserve 16G huge page memory sections for huge pages */ |
619 | of_scan_flat_dt(htab_dt_scan_hugepage_blocks, NULL); | |
3c726f8d BH |
620 | #endif /* CONFIG_HUGETLB_PAGE */ |
621 | } | |
622 | ||
623 | static int __init htab_dt_scan_pftsize(unsigned long node, | |
624 | const char *uname, int depth, | |
625 | void *data) | |
626 | { | |
9d0c4dfe RH |
627 | const char *type = of_get_flat_dt_prop(node, "device_type", NULL); |
628 | const __be32 *prop; | |
3c726f8d BH |
629 | |
630 | /* We are scanning "cpu" nodes only */ | |
631 | if (type == NULL || strcmp(type, "cpu") != 0) | |
632 | return 0; | |
633 | ||
12f04f2b | 634 | prop = of_get_flat_dt_prop(node, "ibm,pft-size", NULL); |
3c726f8d BH |
635 | if (prop != NULL) { |
636 | /* pft_size[0] is the NUMA CEC cookie */ | |
12f04f2b | 637 | ppc64_pft_size = be32_to_cpu(prop[1]); |
3c726f8d | 638 | return 1; |
1da177e4 | 639 | } |
3c726f8d | 640 | return 0; |
1da177e4 LT |
641 | } |
642 | ||
5c3c7ede | 643 | unsigned htab_shift_for_mem_size(unsigned long mem_size) |
3eac8c69 | 644 | { |
5c3c7ede DG |
645 | unsigned memshift = __ilog2(mem_size); |
646 | unsigned pshift = mmu_psize_defs[mmu_virtual_psize].shift; | |
647 | unsigned pteg_shift; | |
648 | ||
649 | /* round mem_size up to next power of 2 */ | |
650 | if ((1UL << memshift) < mem_size) | |
651 | memshift += 1; | |
3eac8c69 | 652 | |
5c3c7ede DG |
653 | /* aim for 2 pages / pteg */ |
654 | pteg_shift = memshift - (pshift + 1); | |
3eac8c69 | 655 | |
5c3c7ede DG |
656 | /* |
657 | * 2^11 PTEGS of 128 bytes each, ie. 2^18 bytes is the minimum htab | |
658 | * size permitted by the architecture. | |
659 | */ | |
660 | return max(pteg_shift + 7, 18U); | |
661 | } | |
662 | ||
663 | static unsigned long __init htab_get_table_size(void) | |
664 | { | |
3c726f8d | 665 | /* If hash size isn't already provided by the platform, we try to |
943ffb58 | 666 | * retrieve it from the device-tree. If it's not there neither, we |
3c726f8d | 667 | * calculate it now based on the total RAM size |
3eac8c69 | 668 | */ |
3c726f8d BH |
669 | if (ppc64_pft_size == 0) |
670 | of_scan_flat_dt(htab_dt_scan_pftsize, NULL); | |
3eac8c69 PM |
671 | if (ppc64_pft_size) |
672 | return 1UL << ppc64_pft_size; | |
673 | ||
5c3c7ede | 674 | return 1UL << htab_shift_for_mem_size(memblock_phys_mem_size()); |
3eac8c69 PM |
675 | } |
676 | ||
54b79248 | 677 | #ifdef CONFIG_MEMORY_HOTPLUG |
a1194097 | 678 | int create_section_mapping(unsigned long start, unsigned long end) |
54b79248 | 679 | { |
1dace6c6 DG |
680 | int rc = htab_bolt_mapping(start, end, __pa(start), |
681 | pgprot_val(PAGE_KERNEL), mmu_linear_psize, | |
682 | mmu_kernel_ssize); | |
683 | ||
684 | if (rc < 0) { | |
685 | int rc2 = htab_remove_mapping(start, end, mmu_linear_psize, | |
686 | mmu_kernel_ssize); | |
687 | BUG_ON(rc2 && (rc2 != -ENOENT)); | |
688 | } | |
689 | return rc; | |
54b79248 | 690 | } |
f8c8803b | 691 | |
52db9b44 | 692 | int remove_section_mapping(unsigned long start, unsigned long end) |
f8c8803b | 693 | { |
abd0a0e7 DG |
694 | int rc = htab_remove_mapping(start, end, mmu_linear_psize, |
695 | mmu_kernel_ssize); | |
696 | WARN_ON(rc < 0); | |
697 | return rc; | |
f8c8803b | 698 | } |
54b79248 MK |
699 | #endif /* CONFIG_MEMORY_HOTPLUG */ |
700 | ||
50de596d AK |
701 | static void __init hash_init_partition_table(phys_addr_t hash_table, |
702 | unsigned long pteg_count) | |
703 | { | |
704 | unsigned long ps_field; | |
705 | unsigned long htab_size; | |
706 | unsigned long patb_size = 1UL << PATB_SIZE_SHIFT; | |
707 | ||
708 | /* | |
709 | * slb llp encoding for the page size used in VPM real mode. | |
710 | * We can ignore that for lpid 0 | |
711 | */ | |
712 | ps_field = 0; | |
713 | htab_size = __ilog2(pteg_count) - 11; | |
714 | ||
715 | BUILD_BUG_ON_MSG((PATB_SIZE_SHIFT > 24), "Partition table size too large."); | |
716 | partition_tb = __va(memblock_alloc_base(patb_size, patb_size, | |
717 | MEMBLOCK_ALLOC_ANYWHERE)); | |
718 | ||
719 | /* Initialize the Partition Table with no entries */ | |
720 | memset((void *)partition_tb, 0, patb_size); | |
721 | partition_tb->patb0 = cpu_to_be64(ps_field | hash_table | htab_size); | |
722 | /* | |
723 | * FIXME!! This should be done via update_partition table | |
724 | * For now UPRT is 0 for us. | |
725 | */ | |
726 | partition_tb->patb1 = 0; | |
727 | DBG("Partition table %p\n", partition_tb); | |
728 | /* | |
729 | * update partition table control register, | |
730 | * 64 K size. | |
731 | */ | |
732 | mtspr(SPRN_PTCR, __pa(partition_tb) | (PATB_SIZE_SHIFT - 12)); | |
733 | ||
734 | } | |
735 | ||
757c74d2 | 736 | static void __init htab_initialize(void) |
1da177e4 | 737 | { |
337a7128 | 738 | unsigned long table; |
1da177e4 | 739 | unsigned long pteg_count; |
9e88ba4e | 740 | unsigned long prot; |
41d824bf | 741 | unsigned long base = 0, size = 0, limit; |
28be7072 | 742 | struct memblock_region *reg; |
3c726f8d | 743 | |
1da177e4 LT |
744 | DBG(" -> htab_initialize()\n"); |
745 | ||
1189be65 PM |
746 | /* Initialize segment sizes */ |
747 | htab_init_seg_sizes(); | |
748 | ||
3c726f8d BH |
749 | /* Initialize page sizes */ |
750 | htab_init_page_sizes(); | |
751 | ||
44ae3ab3 | 752 | if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) { |
1189be65 PM |
753 | mmu_kernel_ssize = MMU_SEGSIZE_1T; |
754 | mmu_highuser_ssize = MMU_SEGSIZE_1T; | |
755 | printk(KERN_INFO "Using 1TB segments\n"); | |
756 | } | |
757 | ||
1da177e4 LT |
758 | /* |
759 | * Calculate the required size of the htab. We want the number of | |
760 | * PTEGs to equal one half the number of real pages. | |
761 | */ | |
3c726f8d | 762 | htab_size_bytes = htab_get_table_size(); |
1da177e4 LT |
763 | pteg_count = htab_size_bytes >> 7; |
764 | ||
1da177e4 LT |
765 | htab_hash_mask = pteg_count - 1; |
766 | ||
57cfb814 | 767 | if (firmware_has_feature(FW_FEATURE_LPAR)) { |
1da177e4 LT |
768 | /* Using a hypervisor which owns the htab */ |
769 | htab_address = NULL; | |
770 | _SDR1 = 0; | |
3ccc00a7 MS |
771 | #ifdef CONFIG_FA_DUMP |
772 | /* | |
773 | * If firmware assisted dump is active firmware preserves | |
774 | * the contents of htab along with entire partition memory. | |
775 | * Clear the htab if firmware assisted dump is active so | |
776 | * that we dont end up using old mappings. | |
777 | */ | |
778 | if (is_fadump_active() && ppc_md.hpte_clear_all) | |
779 | ppc_md.hpte_clear_all(); | |
780 | #endif | |
1da177e4 LT |
781 | } else { |
782 | /* Find storage for the HPT. Must be contiguous in | |
41d824bf | 783 | * the absolute address space. On cell we want it to be |
31bf1119 | 784 | * in the first 2 Gig so we can use it for IOMMU hacks. |
1da177e4 | 785 | */ |
41d824bf | 786 | if (machine_is(cell)) |
31bf1119 | 787 | limit = 0x80000000; |
41d824bf | 788 | else |
27f574c2 | 789 | limit = MEMBLOCK_ALLOC_ANYWHERE; |
41d824bf | 790 | |
95f72d1e | 791 | table = memblock_alloc_base(htab_size_bytes, htab_size_bytes, limit); |
1da177e4 LT |
792 | |
793 | DBG("Hash table allocated at %lx, size: %lx\n", table, | |
794 | htab_size_bytes); | |
795 | ||
70267a7f | 796 | htab_address = __va(table); |
1da177e4 LT |
797 | |
798 | /* htab absolute addr + encoded htabsize */ | |
799 | _SDR1 = table + __ilog2(pteg_count) - 11; | |
800 | ||
801 | /* Initialize the HPT with no entries */ | |
802 | memset((void *)table, 0, htab_size_bytes); | |
799d6046 | 803 | |
50de596d AK |
804 | if (!cpu_has_feature(CPU_FTR_ARCH_300)) |
805 | /* Set SDR1 */ | |
806 | mtspr(SPRN_SDR1, _SDR1); | |
807 | else | |
808 | hash_init_partition_table(table, pteg_count); | |
1da177e4 LT |
809 | } |
810 | ||
f5ea64dc | 811 | prot = pgprot_val(PAGE_KERNEL); |
1da177e4 | 812 | |
370a908d | 813 | #ifdef CONFIG_DEBUG_PAGEALLOC |
e7df0d88 JK |
814 | if (debug_pagealloc_enabled()) { |
815 | linear_map_hash_count = memblock_end_of_DRAM() >> PAGE_SHIFT; | |
816 | linear_map_hash_slots = __va(memblock_alloc_base( | |
817 | linear_map_hash_count, 1, ppc64_rma_size)); | |
818 | memset(linear_map_hash_slots, 0, linear_map_hash_count); | |
819 | } | |
370a908d BH |
820 | #endif /* CONFIG_DEBUG_PAGEALLOC */ |
821 | ||
1da177e4 LT |
822 | /* On U3 based machines, we need to reserve the DART area and |
823 | * _NOT_ map it to avoid cache paradoxes as it's remapped non | |
824 | * cacheable later on | |
825 | */ | |
1da177e4 LT |
826 | |
827 | /* create bolted the linear mapping in the hash table */ | |
28be7072 BH |
828 | for_each_memblock(memory, reg) { |
829 | base = (unsigned long)__va(reg->base); | |
830 | size = reg->size; | |
1da177e4 | 831 | |
5c339919 | 832 | DBG("creating mapping for region: %lx..%lx (prot: %lx)\n", |
9e88ba4e | 833 | base, size, prot); |
1da177e4 LT |
834 | |
835 | #ifdef CONFIG_U3_DART | |
836 | /* Do not map the DART space. Fortunately, it will be aligned | |
95f72d1e | 837 | * in such a way that it will not cross two memblock regions and |
3c726f8d BH |
838 | * will fit within a single 16Mb page. |
839 | * The DART space is assumed to be a full 16Mb region even if | |
840 | * we only use 2Mb of that space. We will use more of it later | |
841 | * for AGP GART. We have to use a full 16Mb large page. | |
1da177e4 LT |
842 | */ |
843 | DBG("DART base: %lx\n", dart_tablebase); | |
844 | ||
845 | if (dart_tablebase != 0 && dart_tablebase >= base | |
846 | && dart_tablebase < (base + size)) { | |
caf80e57 | 847 | unsigned long dart_table_end = dart_tablebase + 16 * MB; |
1da177e4 | 848 | if (base != dart_tablebase) |
3c726f8d | 849 | BUG_ON(htab_bolt_mapping(base, dart_tablebase, |
9e88ba4e | 850 | __pa(base), prot, |
1189be65 PM |
851 | mmu_linear_psize, |
852 | mmu_kernel_ssize)); | |
caf80e57 | 853 | if ((base + size) > dart_table_end) |
3c726f8d | 854 | BUG_ON(htab_bolt_mapping(dart_tablebase+16*MB, |
caf80e57 ME |
855 | base + size, |
856 | __pa(dart_table_end), | |
9e88ba4e | 857 | prot, |
1189be65 PM |
858 | mmu_linear_psize, |
859 | mmu_kernel_ssize)); | |
1da177e4 LT |
860 | continue; |
861 | } | |
862 | #endif /* CONFIG_U3_DART */ | |
caf80e57 | 863 | BUG_ON(htab_bolt_mapping(base, base + size, __pa(base), |
9e88ba4e | 864 | prot, mmu_linear_psize, mmu_kernel_ssize)); |
e63075a3 BH |
865 | } |
866 | memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE); | |
1da177e4 LT |
867 | |
868 | /* | |
869 | * If we have a memory_limit and we've allocated TCEs then we need to | |
870 | * explicitly map the TCE area at the top of RAM. We also cope with the | |
871 | * case that the TCEs start below memory_limit. | |
872 | * tce_alloc_start/end are 16MB aligned so the mapping should work | |
873 | * for either 4K or 16MB pages. | |
874 | */ | |
875 | if (tce_alloc_start) { | |
b5666f70 ME |
876 | tce_alloc_start = (unsigned long)__va(tce_alloc_start); |
877 | tce_alloc_end = (unsigned long)__va(tce_alloc_end); | |
1da177e4 LT |
878 | |
879 | if (base + size >= tce_alloc_start) | |
880 | tce_alloc_start = base + size + 1; | |
881 | ||
caf80e57 | 882 | BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end, |
bc033b63 | 883 | __pa(tce_alloc_start), prot, |
1189be65 | 884 | mmu_linear_psize, mmu_kernel_ssize)); |
1da177e4 LT |
885 | } |
886 | ||
7d0daae4 | 887 | |
1da177e4 LT |
888 | DBG(" <- htab_initialize()\n"); |
889 | } | |
890 | #undef KB | |
891 | #undef MB | |
1da177e4 | 892 | |
756d08d1 | 893 | void __init hash__early_init_mmu(void) |
799d6046 | 894 | { |
dd1842a2 AK |
895 | /* |
896 | * initialize page table size | |
897 | */ | |
5ed7ecd0 AK |
898 | __pte_frag_nr = H_PTE_FRAG_NR; |
899 | __pte_frag_size_shift = H_PTE_FRAG_SIZE_SHIFT; | |
900 | ||
dd1842a2 AK |
901 | __pte_index_size = H_PTE_INDEX_SIZE; |
902 | __pmd_index_size = H_PMD_INDEX_SIZE; | |
903 | __pud_index_size = H_PUD_INDEX_SIZE; | |
904 | __pgd_index_size = H_PGD_INDEX_SIZE; | |
905 | __pmd_cache_index = H_PMD_CACHE_INDEX; | |
906 | __pte_table_size = H_PTE_TABLE_SIZE; | |
907 | __pmd_table_size = H_PMD_TABLE_SIZE; | |
908 | __pud_table_size = H_PUD_TABLE_SIZE; | |
909 | __pgd_table_size = H_PGD_TABLE_SIZE; | |
a2f41eb9 AK |
910 | /* |
911 | * 4k use hugepd format, so for hash set then to | |
912 | * zero | |
913 | */ | |
914 | __pmd_val_bits = 0; | |
915 | __pud_val_bits = 0; | |
916 | __pgd_val_bits = 0; | |
d6a9996e AK |
917 | |
918 | __kernel_virt_start = H_KERN_VIRT_START; | |
919 | __kernel_virt_size = H_KERN_VIRT_SIZE; | |
920 | __vmalloc_start = H_VMALLOC_START; | |
921 | __vmalloc_end = H_VMALLOC_END; | |
922 | vmemmap = (struct page *)H_VMEMMAP_BASE; | |
923 | ioremap_bot = IOREMAP_BASE; | |
924 | ||
bfa37087 DS |
925 | #ifdef CONFIG_PCI |
926 | pci_io_base = ISA_IO_BASE; | |
927 | #endif | |
928 | ||
757c74d2 | 929 | /* Initialize the MMU Hash table and create the linear mapping |
376af594 ME |
930 | * of memory. Has to be done before SLB initialization as this is |
931 | * currently where the page size encoding is obtained. | |
757c74d2 BH |
932 | */ |
933 | htab_initialize(); | |
934 | ||
376af594 | 935 | /* Initialize SLB management */ |
13b3d13b | 936 | slb_initialize(); |
757c74d2 BH |
937 | } |
938 | ||
939 | #ifdef CONFIG_SMP | |
756d08d1 | 940 | void hash__early_init_mmu_secondary(void) |
757c74d2 BH |
941 | { |
942 | /* Initialize hash table for that CPU */ | |
b5dcc609 AK |
943 | if (!firmware_has_feature(FW_FEATURE_LPAR)) { |
944 | if (!cpu_has_feature(CPU_FTR_ARCH_300)) | |
945 | mtspr(SPRN_SDR1, _SDR1); | |
946 | else | |
947 | mtspr(SPRN_PTCR, | |
948 | __pa(partition_tb) | (PATB_SIZE_SHIFT - 12)); | |
949 | } | |
376af594 | 950 | /* Initialize SLB */ |
13b3d13b | 951 | slb_initialize(); |
799d6046 | 952 | } |
757c74d2 | 953 | #endif /* CONFIG_SMP */ |
799d6046 | 954 | |
1da177e4 LT |
955 | /* |
956 | * Called by asm hashtable.S for doing lazy icache flush | |
957 | */ | |
958 | unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap) | |
959 | { | |
960 | struct page *page; | |
961 | ||
76c8e25b BH |
962 | if (!pfn_valid(pte_pfn(pte))) |
963 | return pp; | |
964 | ||
1da177e4 LT |
965 | page = pte_page(pte); |
966 | ||
967 | /* page is dirty */ | |
968 | if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) { | |
969 | if (trap == 0x400) { | |
0895ecda | 970 | flush_dcache_icache_page(page); |
1da177e4 LT |
971 | set_bit(PG_arch_1, &page->flags); |
972 | } else | |
3c726f8d | 973 | pp |= HPTE_R_N; |
1da177e4 LT |
974 | } |
975 | return pp; | |
976 | } | |
977 | ||
3a8247cc | 978 | #ifdef CONFIG_PPC_MM_SLICES |
e51df2c1 | 979 | static unsigned int get_paca_psize(unsigned long addr) |
3a8247cc | 980 | { |
7aa0727f AK |
981 | u64 lpsizes; |
982 | unsigned char *hpsizes; | |
983 | unsigned long index, mask_index; | |
3a8247cc PM |
984 | |
985 | if (addr < SLICE_LOW_TOP) { | |
2fc251a8 | 986 | lpsizes = get_paca()->mm_ctx_low_slices_psize; |
3a8247cc | 987 | index = GET_LOW_SLICE_INDEX(addr); |
7aa0727f | 988 | return (lpsizes >> (index * 4)) & 0xF; |
3a8247cc | 989 | } |
2fc251a8 | 990 | hpsizes = get_paca()->mm_ctx_high_slices_psize; |
7aa0727f AK |
991 | index = GET_HIGH_SLICE_INDEX(addr); |
992 | mask_index = index & 0x1; | |
993 | return (hpsizes[index >> 1] >> (mask_index * 4)) & 0xF; | |
3a8247cc PM |
994 | } |
995 | ||
996 | #else | |
997 | unsigned int get_paca_psize(unsigned long addr) | |
998 | { | |
c33e54fa | 999 | return get_paca()->mm_ctx_user_psize; |
3a8247cc PM |
1000 | } |
1001 | #endif | |
1002 | ||
721151d0 PM |
1003 | /* |
1004 | * Demote a segment to using 4k pages. | |
1005 | * For now this makes the whole process use 4k pages. | |
1006 | */ | |
721151d0 | 1007 | #ifdef CONFIG_PPC_64K_PAGES |
fa28237c | 1008 | void demote_segment_4k(struct mm_struct *mm, unsigned long addr) |
16f1c746 | 1009 | { |
3a8247cc | 1010 | if (get_slice_psize(mm, addr) == MMU_PAGE_4K) |
721151d0 | 1011 | return; |
3a8247cc | 1012 | slice_set_range_psize(mm, addr, 1, MMU_PAGE_4K); |
be3ebfe8 | 1013 | copro_flush_all_slbs(mm); |
a1dca346 | 1014 | if ((get_paca_psize(addr) != MMU_PAGE_4K) && (current->mm == mm)) { |
c395465d MN |
1015 | |
1016 | copy_mm_to_paca(&mm->context); | |
fa28237c PM |
1017 | slb_flush_and_rebolt(); |
1018 | } | |
721151d0 | 1019 | } |
16f1c746 | 1020 | #endif /* CONFIG_PPC_64K_PAGES */ |
721151d0 | 1021 | |
fa28237c PM |
1022 | #ifdef CONFIG_PPC_SUBPAGE_PROT |
1023 | /* | |
1024 | * This looks up a 2-bit protection code for a 4k subpage of a 64k page. | |
1025 | * Userspace sets the subpage permissions using the subpage_prot system call. | |
1026 | * | |
1027 | * Result is 0: full permissions, _PAGE_RW: read-only, | |
73a1441a | 1028 | * _PAGE_RWX: no access. |
fa28237c | 1029 | */ |
d28513bc | 1030 | static int subpage_protection(struct mm_struct *mm, unsigned long ea) |
fa28237c | 1031 | { |
d28513bc | 1032 | struct subpage_prot_table *spt = &mm->context.spt; |
fa28237c PM |
1033 | u32 spp = 0; |
1034 | u32 **sbpm, *sbpp; | |
1035 | ||
1036 | if (ea >= spt->maxaddr) | |
1037 | return 0; | |
b0d436c7 | 1038 | if (ea < 0x100000000UL) { |
fa28237c PM |
1039 | /* addresses below 4GB use spt->low_prot */ |
1040 | sbpm = spt->low_prot; | |
1041 | } else { | |
1042 | sbpm = spt->protptrs[ea >> SBP_L3_SHIFT]; | |
1043 | if (!sbpm) | |
1044 | return 0; | |
1045 | } | |
1046 | sbpp = sbpm[(ea >> SBP_L2_SHIFT) & (SBP_L2_COUNT - 1)]; | |
1047 | if (!sbpp) | |
1048 | return 0; | |
1049 | spp = sbpp[(ea >> PAGE_SHIFT) & (SBP_L1_COUNT - 1)]; | |
1050 | ||
1051 | /* extract 2-bit bitfield for this 4k subpage */ | |
1052 | spp >>= 30 - 2 * ((ea >> 12) & 0xf); | |
1053 | ||
73a1441a AK |
1054 | /* |
1055 | * 0 -> full premission | |
1056 | * 1 -> Read only | |
1057 | * 2 -> no access. | |
1058 | * We return the flag that need to be cleared. | |
1059 | */ | |
1060 | spp = ((spp & 2) ? _PAGE_RWX : 0) | ((spp & 1) ? _PAGE_WRITE : 0); | |
fa28237c PM |
1061 | return spp; |
1062 | } | |
1063 | ||
1064 | #else /* CONFIG_PPC_SUBPAGE_PROT */ | |
d28513bc | 1065 | static inline int subpage_protection(struct mm_struct *mm, unsigned long ea) |
fa28237c PM |
1066 | { |
1067 | return 0; | |
1068 | } | |
1069 | #endif | |
1070 | ||
4b8692c0 BH |
1071 | void hash_failure_debug(unsigned long ea, unsigned long access, |
1072 | unsigned long vsid, unsigned long trap, | |
d8139ebf | 1073 | int ssize, int psize, int lpsize, unsigned long pte) |
4b8692c0 BH |
1074 | { |
1075 | if (!printk_ratelimit()) | |
1076 | return; | |
1077 | pr_info("mm: Hashing failure ! EA=0x%lx access=0x%lx current=%s\n", | |
1078 | ea, access, current->comm); | |
d8139ebf AK |
1079 | pr_info(" trap=0x%lx vsid=0x%lx ssize=%d base psize=%d psize %d pte=0x%lx\n", |
1080 | trap, vsid, ssize, psize, lpsize, pte); | |
4b8692c0 BH |
1081 | } |
1082 | ||
09567e7f ME |
1083 | static void check_paca_psize(unsigned long ea, struct mm_struct *mm, |
1084 | int psize, bool user_region) | |
1085 | { | |
1086 | if (user_region) { | |
1087 | if (psize != get_paca_psize(ea)) { | |
c395465d | 1088 | copy_mm_to_paca(&mm->context); |
09567e7f ME |
1089 | slb_flush_and_rebolt(); |
1090 | } | |
1091 | } else if (get_paca()->vmalloc_sllp != | |
1092 | mmu_psize_defs[mmu_vmalloc_psize].sllp) { | |
1093 | get_paca()->vmalloc_sllp = | |
1094 | mmu_psize_defs[mmu_vmalloc_psize].sllp; | |
1095 | slb_vmalloc_update(); | |
1096 | } | |
1097 | } | |
1098 | ||
1da177e4 LT |
1099 | /* Result code is: |
1100 | * 0 - handled | |
1101 | * 1 - normal page fault | |
1102 | * -1 - critical hash insertion error | |
fa28237c | 1103 | * -2 - access not permitted by subpage protection mechanism |
1da177e4 | 1104 | */ |
aefa5688 AK |
1105 | int hash_page_mm(struct mm_struct *mm, unsigned long ea, |
1106 | unsigned long access, unsigned long trap, | |
1107 | unsigned long flags) | |
1da177e4 | 1108 | { |
891121e6 | 1109 | bool is_thp; |
ba12eede | 1110 | enum ctx_state prev_state = exception_enter(); |
a1128f8f | 1111 | pgd_t *pgdir; |
1da177e4 | 1112 | unsigned long vsid; |
1da177e4 | 1113 | pte_t *ptep; |
a4fe3ce7 | 1114 | unsigned hugeshift; |
56aa4129 | 1115 | const struct cpumask *tmp; |
aefa5688 | 1116 | int rc, user_region = 0; |
1189be65 | 1117 | int psize, ssize; |
1da177e4 | 1118 | |
3c726f8d BH |
1119 | DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n", |
1120 | ea, access, trap); | |
cfcb3d80 | 1121 | trace_hash_fault(ea, access, trap); |
1f8d419e | 1122 | |
3c726f8d | 1123 | /* Get region & vsid */ |
1da177e4 LT |
1124 | switch (REGION_ID(ea)) { |
1125 | case USER_REGION_ID: | |
1126 | user_region = 1; | |
3c726f8d BH |
1127 | if (! mm) { |
1128 | DBG_LOW(" user region with no mm !\n"); | |
ba12eede LZ |
1129 | rc = 1; |
1130 | goto bail; | |
3c726f8d | 1131 | } |
16c2d476 | 1132 | psize = get_slice_psize(mm, ea); |
1189be65 PM |
1133 | ssize = user_segment_size(ea); |
1134 | vsid = get_vsid(mm->context.id, ea, ssize); | |
1da177e4 | 1135 | break; |
1da177e4 | 1136 | case VMALLOC_REGION_ID: |
1189be65 | 1137 | vsid = get_kernel_vsid(ea, mmu_kernel_ssize); |
bf72aeba PM |
1138 | if (ea < VMALLOC_END) |
1139 | psize = mmu_vmalloc_psize; | |
1140 | else | |
1141 | psize = mmu_io_psize; | |
1189be65 | 1142 | ssize = mmu_kernel_ssize; |
1da177e4 | 1143 | break; |
1da177e4 LT |
1144 | default: |
1145 | /* Not a valid range | |
1146 | * Send the problem up to do_page_fault | |
1147 | */ | |
ba12eede LZ |
1148 | rc = 1; |
1149 | goto bail; | |
1da177e4 | 1150 | } |
3c726f8d | 1151 | DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid); |
1da177e4 | 1152 | |
c60ac569 AK |
1153 | /* Bad address. */ |
1154 | if (!vsid) { | |
1155 | DBG_LOW("Bad address!\n"); | |
ba12eede LZ |
1156 | rc = 1; |
1157 | goto bail; | |
c60ac569 | 1158 | } |
3c726f8d | 1159 | /* Get pgdir */ |
1da177e4 | 1160 | pgdir = mm->pgd; |
ba12eede LZ |
1161 | if (pgdir == NULL) { |
1162 | rc = 1; | |
1163 | goto bail; | |
1164 | } | |
1da177e4 | 1165 | |
3c726f8d | 1166 | /* Check CPU locality */ |
56aa4129 RR |
1167 | tmp = cpumask_of(smp_processor_id()); |
1168 | if (user_region && cpumask_equal(mm_cpumask(mm), tmp)) | |
aefa5688 | 1169 | flags |= HPTE_LOCAL_UPDATE; |
1da177e4 | 1170 | |
16c2d476 | 1171 | #ifndef CONFIG_PPC_64K_PAGES |
a4fe3ce7 DG |
1172 | /* If we use 4K pages and our psize is not 4K, then we might |
1173 | * be hitting a special driver mapping, and need to align the | |
1174 | * address before we fetch the PTE. | |
1175 | * | |
1176 | * It could also be a hugepage mapping, in which case this is | |
1177 | * not necessary, but it's not harmful, either. | |
16c2d476 BH |
1178 | */ |
1179 | if (psize != MMU_PAGE_4K) | |
1180 | ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1); | |
1181 | #endif /* CONFIG_PPC_64K_PAGES */ | |
1182 | ||
3c726f8d | 1183 | /* Get PTE and page size from page tables */ |
891121e6 | 1184 | ptep = __find_linux_pte_or_hugepte(pgdir, ea, &is_thp, &hugeshift); |
3c726f8d BH |
1185 | if (ptep == NULL || !pte_present(*ptep)) { |
1186 | DBG_LOW(" no PTE !\n"); | |
ba12eede LZ |
1187 | rc = 1; |
1188 | goto bail; | |
3c726f8d BH |
1189 | } |
1190 | ||
ca91e6c0 BH |
1191 | /* Add _PAGE_PRESENT to the required access perm */ |
1192 | access |= _PAGE_PRESENT; | |
1193 | ||
1194 | /* Pre-check access permissions (will be re-checked atomically | |
1195 | * in __hash_page_XX but this pre-check is a fast path | |
1196 | */ | |
ac29c640 | 1197 | if (!check_pte_access(access, pte_val(*ptep))) { |
ca91e6c0 | 1198 | DBG_LOW(" no access !\n"); |
ba12eede LZ |
1199 | rc = 1; |
1200 | goto bail; | |
ca91e6c0 BH |
1201 | } |
1202 | ||
ba12eede | 1203 | if (hugeshift) { |
891121e6 | 1204 | if (is_thp) |
6d492ecc | 1205 | rc = __hash_page_thp(ea, access, vsid, (pmd_t *)ptep, |
aefa5688 | 1206 | trap, flags, ssize, psize); |
6d492ecc AK |
1207 | #ifdef CONFIG_HUGETLB_PAGE |
1208 | else | |
1209 | rc = __hash_page_huge(ea, access, vsid, ptep, trap, | |
aefa5688 | 1210 | flags, ssize, hugeshift, psize); |
6d492ecc AK |
1211 | #else |
1212 | else { | |
1213 | /* | |
1214 | * if we have hugeshift, and is not transhuge with | |
1215 | * hugetlb disabled, something is really wrong. | |
1216 | */ | |
1217 | rc = 1; | |
1218 | WARN_ON(1); | |
1219 | } | |
1220 | #endif | |
a1dca346 IM |
1221 | if (current->mm == mm) |
1222 | check_paca_psize(ea, mm, psize, user_region); | |
09567e7f | 1223 | |
ba12eede LZ |
1224 | goto bail; |
1225 | } | |
a4fe3ce7 | 1226 | |
3c726f8d BH |
1227 | #ifndef CONFIG_PPC_64K_PAGES |
1228 | DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep)); | |
1229 | #else | |
1230 | DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep), | |
1231 | pte_val(*(ptep + PTRS_PER_PTE))); | |
1232 | #endif | |
3c726f8d | 1233 | /* Do actual hashing */ |
16c2d476 | 1234 | #ifdef CONFIG_PPC_64K_PAGES |
945537df AK |
1235 | /* If H_PAGE_4K_PFN is set, make sure this is a 4k segment */ |
1236 | if ((pte_val(*ptep) & H_PAGE_4K_PFN) && psize == MMU_PAGE_64K) { | |
721151d0 PM |
1237 | demote_segment_4k(mm, ea); |
1238 | psize = MMU_PAGE_4K; | |
1239 | } | |
1240 | ||
16f1c746 BH |
1241 | /* If this PTE is non-cacheable and we have restrictions on |
1242 | * using non cacheable large pages, then we switch to 4k | |
1243 | */ | |
30bda41a | 1244 | if (mmu_ci_restrictions && psize == MMU_PAGE_64K && pte_ci(*ptep)) { |
16f1c746 BH |
1245 | if (user_region) { |
1246 | demote_segment_4k(mm, ea); | |
1247 | psize = MMU_PAGE_4K; | |
1248 | } else if (ea < VMALLOC_END) { | |
1249 | /* | |
1250 | * some driver did a non-cacheable mapping | |
1251 | * in vmalloc space, so switch vmalloc | |
1252 | * to 4k pages | |
1253 | */ | |
1254 | printk(KERN_ALERT "Reducing vmalloc segment " | |
1255 | "to 4kB pages because of " | |
1256 | "non-cacheable mapping\n"); | |
1257 | psize = mmu_vmalloc_psize = MMU_PAGE_4K; | |
be3ebfe8 | 1258 | copro_flush_all_slbs(mm); |
bf72aeba | 1259 | } |
16f1c746 | 1260 | } |
09567e7f | 1261 | |
0863d7f2 AK |
1262 | #endif /* CONFIG_PPC_64K_PAGES */ |
1263 | ||
a1dca346 IM |
1264 | if (current->mm == mm) |
1265 | check_paca_psize(ea, mm, psize, user_region); | |
16f1c746 | 1266 | |
73b341ef | 1267 | #ifdef CONFIG_PPC_64K_PAGES |
bf72aeba | 1268 | if (psize == MMU_PAGE_64K) |
aefa5688 AK |
1269 | rc = __hash_page_64K(ea, access, vsid, ptep, trap, |
1270 | flags, ssize); | |
3c726f8d | 1271 | else |
73b341ef | 1272 | #endif /* CONFIG_PPC_64K_PAGES */ |
fa28237c | 1273 | { |
a1128f8f | 1274 | int spp = subpage_protection(mm, ea); |
fa28237c PM |
1275 | if (access & spp) |
1276 | rc = -2; | |
1277 | else | |
1278 | rc = __hash_page_4K(ea, access, vsid, ptep, trap, | |
aefa5688 | 1279 | flags, ssize, spp); |
fa28237c | 1280 | } |
3c726f8d | 1281 | |
4b8692c0 BH |
1282 | /* Dump some info in case of hash insertion failure, they should |
1283 | * never happen so it is really useful to know if/when they do | |
1284 | */ | |
1285 | if (rc == -1) | |
1286 | hash_failure_debug(ea, access, vsid, trap, ssize, psize, | |
d8139ebf | 1287 | psize, pte_val(*ptep)); |
3c726f8d BH |
1288 | #ifndef CONFIG_PPC_64K_PAGES |
1289 | DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep)); | |
1290 | #else | |
1291 | DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep), | |
1292 | pte_val(*(ptep + PTRS_PER_PTE))); | |
1293 | #endif | |
1294 | DBG_LOW(" -> rc=%d\n", rc); | |
ba12eede LZ |
1295 | |
1296 | bail: | |
1297 | exception_exit(prev_state); | |
3c726f8d | 1298 | return rc; |
1da177e4 | 1299 | } |
a1dca346 IM |
1300 | EXPORT_SYMBOL_GPL(hash_page_mm); |
1301 | ||
aefa5688 AK |
1302 | int hash_page(unsigned long ea, unsigned long access, unsigned long trap, |
1303 | unsigned long dsisr) | |
a1dca346 | 1304 | { |
aefa5688 | 1305 | unsigned long flags = 0; |
a1dca346 IM |
1306 | struct mm_struct *mm = current->mm; |
1307 | ||
1308 | if (REGION_ID(ea) == VMALLOC_REGION_ID) | |
1309 | mm = &init_mm; | |
1310 | ||
aefa5688 AK |
1311 | if (dsisr & DSISR_NOHPTE) |
1312 | flags |= HPTE_NOHPTE_UPDATE; | |
1313 | ||
1314 | return hash_page_mm(mm, ea, access, trap, flags); | |
a1dca346 | 1315 | } |
67207b96 | 1316 | EXPORT_SYMBOL_GPL(hash_page); |
1da177e4 | 1317 | |
106713a1 AK |
1318 | int __hash_page(unsigned long ea, unsigned long msr, unsigned long trap, |
1319 | unsigned long dsisr) | |
1320 | { | |
c7d54842 | 1321 | unsigned long access = _PAGE_PRESENT | _PAGE_READ; |
106713a1 AK |
1322 | unsigned long flags = 0; |
1323 | struct mm_struct *mm = current->mm; | |
1324 | ||
1325 | if (REGION_ID(ea) == VMALLOC_REGION_ID) | |
1326 | mm = &init_mm; | |
1327 | ||
1328 | if (dsisr & DSISR_NOHPTE) | |
1329 | flags |= HPTE_NOHPTE_UPDATE; | |
1330 | ||
1331 | if (dsisr & DSISR_ISSTORE) | |
c7d54842 | 1332 | access |= _PAGE_WRITE; |
106713a1 | 1333 | /* |
ac29c640 AK |
1334 | * We set _PAGE_PRIVILEGED only when |
1335 | * kernel mode access kernel space. | |
1336 | * | |
1337 | * _PAGE_PRIVILEGED is NOT set | |
1338 | * 1) when kernel mode access user space | |
1339 | * 2) user space access kernel space. | |
106713a1 | 1340 | */ |
ac29c640 | 1341 | access |= _PAGE_PRIVILEGED; |
106713a1 | 1342 | if ((msr & MSR_PR) || (REGION_ID(ea) == USER_REGION_ID)) |
ac29c640 | 1343 | access &= ~_PAGE_PRIVILEGED; |
106713a1 AK |
1344 | |
1345 | if (trap == 0x400) | |
1346 | access |= _PAGE_EXEC; | |
1347 | ||
1348 | return hash_page_mm(mm, ea, access, trap, flags); | |
1349 | } | |
1350 | ||
8bbc9b7b ME |
1351 | #ifdef CONFIG_PPC_MM_SLICES |
1352 | static bool should_hash_preload(struct mm_struct *mm, unsigned long ea) | |
1353 | { | |
aac55d75 ME |
1354 | int psize = get_slice_psize(mm, ea); |
1355 | ||
8bbc9b7b | 1356 | /* We only prefault standard pages for now */ |
aac55d75 ME |
1357 | if (unlikely(psize != mm->context.user_psize)) |
1358 | return false; | |
1359 | ||
1360 | /* | |
1361 | * Don't prefault if subpage protection is enabled for the EA. | |
1362 | */ | |
1363 | if (unlikely((psize == MMU_PAGE_4K) && subpage_protection(mm, ea))) | |
8bbc9b7b ME |
1364 | return false; |
1365 | ||
1366 | return true; | |
1367 | } | |
1368 | #else | |
1369 | static bool should_hash_preload(struct mm_struct *mm, unsigned long ea) | |
1370 | { | |
1371 | return true; | |
1372 | } | |
1373 | #endif | |
1374 | ||
3c726f8d BH |
1375 | void hash_preload(struct mm_struct *mm, unsigned long ea, |
1376 | unsigned long access, unsigned long trap) | |
1da177e4 | 1377 | { |
12bc9f6f | 1378 | int hugepage_shift; |
3c726f8d | 1379 | unsigned long vsid; |
0b97fee0 | 1380 | pgd_t *pgdir; |
3c726f8d | 1381 | pte_t *ptep; |
3c726f8d | 1382 | unsigned long flags; |
aefa5688 | 1383 | int rc, ssize, update_flags = 0; |
3c726f8d | 1384 | |
d0f13e3c BH |
1385 | BUG_ON(REGION_ID(ea) != USER_REGION_ID); |
1386 | ||
8bbc9b7b | 1387 | if (!should_hash_preload(mm, ea)) |
3c726f8d BH |
1388 | return; |
1389 | ||
1390 | DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx," | |
1391 | " trap=%lx\n", mm, mm->pgd, ea, access, trap); | |
1da177e4 | 1392 | |
16f1c746 | 1393 | /* Get Linux PTE if available */ |
3c726f8d BH |
1394 | pgdir = mm->pgd; |
1395 | if (pgdir == NULL) | |
1396 | return; | |
0ac52dd7 AK |
1397 | |
1398 | /* Get VSID */ | |
1399 | ssize = user_segment_size(ea); | |
1400 | vsid = get_vsid(mm->context.id, ea, ssize); | |
1401 | if (!vsid) | |
1402 | return; | |
1403 | /* | |
1404 | * Hash doesn't like irqs. Walking linux page table with irq disabled | |
1405 | * saves us from holding multiple locks. | |
1406 | */ | |
1407 | local_irq_save(flags); | |
1408 | ||
12bc9f6f AK |
1409 | /* |
1410 | * THP pages use update_mmu_cache_pmd. We don't do | |
1411 | * hash preload there. Hence can ignore THP here | |
1412 | */ | |
891121e6 | 1413 | ptep = find_linux_pte_or_hugepte(pgdir, ea, NULL, &hugepage_shift); |
3c726f8d | 1414 | if (!ptep) |
0ac52dd7 | 1415 | goto out_exit; |
16f1c746 | 1416 | |
12bc9f6f | 1417 | WARN_ON(hugepage_shift); |
16f1c746 | 1418 | #ifdef CONFIG_PPC_64K_PAGES |
945537df | 1419 | /* If either H_PAGE_4K_PFN or cache inhibited is set (and we are on |
16f1c746 BH |
1420 | * a 64K kernel), then we don't preload, hash_page() will take |
1421 | * care of it once we actually try to access the page. | |
1422 | * That way we don't have to duplicate all of the logic for segment | |
1423 | * page size demotion here | |
1424 | */ | |
945537df | 1425 | if ((pte_val(*ptep) & H_PAGE_4K_PFN) || pte_ci(*ptep)) |
0ac52dd7 | 1426 | goto out_exit; |
16f1c746 BH |
1427 | #endif /* CONFIG_PPC_64K_PAGES */ |
1428 | ||
16c2d476 | 1429 | /* Is that local to this CPU ? */ |
56aa4129 | 1430 | if (cpumask_equal(mm_cpumask(mm), cpumask_of(smp_processor_id()))) |
aefa5688 | 1431 | update_flags |= HPTE_LOCAL_UPDATE; |
16c2d476 BH |
1432 | |
1433 | /* Hash it in */ | |
73b341ef | 1434 | #ifdef CONFIG_PPC_64K_PAGES |
bf72aeba | 1435 | if (mm->context.user_psize == MMU_PAGE_64K) |
aefa5688 AK |
1436 | rc = __hash_page_64K(ea, access, vsid, ptep, trap, |
1437 | update_flags, ssize); | |
1da177e4 | 1438 | else |
73b341ef | 1439 | #endif /* CONFIG_PPC_64K_PAGES */ |
aefa5688 AK |
1440 | rc = __hash_page_4K(ea, access, vsid, ptep, trap, update_flags, |
1441 | ssize, subpage_protection(mm, ea)); | |
4b8692c0 BH |
1442 | |
1443 | /* Dump some info in case of hash insertion failure, they should | |
1444 | * never happen so it is really useful to know if/when they do | |
1445 | */ | |
1446 | if (rc == -1) | |
1447 | hash_failure_debug(ea, access, vsid, trap, ssize, | |
d8139ebf AK |
1448 | mm->context.user_psize, |
1449 | mm->context.user_psize, | |
1450 | pte_val(*ptep)); | |
0ac52dd7 | 1451 | out_exit: |
3c726f8d BH |
1452 | local_irq_restore(flags); |
1453 | } | |
1454 | ||
f6ab0b92 BH |
1455 | /* WARNING: This is called from hash_low_64.S, if you change this prototype, |
1456 | * do not forget to update the assembly call site ! | |
1457 | */ | |
5524a27d | 1458 | void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize, int ssize, |
aefa5688 | 1459 | unsigned long flags) |
3c726f8d BH |
1460 | { |
1461 | unsigned long hash, index, shift, hidx, slot; | |
aefa5688 | 1462 | int local = flags & HPTE_LOCAL_UPDATE; |
3c726f8d | 1463 | |
5524a27d AK |
1464 | DBG_LOW("flush_hash_page(vpn=%016lx)\n", vpn); |
1465 | pte_iterate_hashed_subpages(pte, psize, vpn, index, shift) { | |
1466 | hash = hpt_hash(vpn, shift, ssize); | |
3c726f8d BH |
1467 | hidx = __rpte_to_hidx(pte, index); |
1468 | if (hidx & _PTEIDX_SECONDARY) | |
1469 | hash = ~hash; | |
1470 | slot = (hash & htab_hash_mask) * HPTES_PER_GROUP; | |
1471 | slot += hidx & _PTEIDX_GROUP_IX; | |
5c339919 | 1472 | DBG_LOW(" sub %ld: hash=%lx, hidx=%lx\n", index, slot, hidx); |
db3d8534 AK |
1473 | /* |
1474 | * We use same base page size and actual psize, because we don't | |
1475 | * use these functions for hugepage | |
1476 | */ | |
1477 | ppc_md.hpte_invalidate(slot, vpn, psize, psize, ssize, local); | |
3c726f8d | 1478 | } pte_iterate_hashed_end(); |
bc2a9408 MN |
1479 | |
1480 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
1481 | /* Transactions are not aborted by tlbiel, only tlbie. | |
1482 | * Without, syncing a page back to a block device w/ PIO could pick up | |
1483 | * transactional data (bad!) so we force an abort here. Before the | |
1484 | * sync the page will be made read-only, which will flush_hash_page. | |
1485 | * BIG ISSUE here: if the kernel uses a page from userspace without | |
1486 | * unmapping it first, it may see the speculated version. | |
1487 | */ | |
1488 | if (local && cpu_has_feature(CPU_FTR_TM) && | |
c2fd22df | 1489 | current->thread.regs && |
bc2a9408 MN |
1490 | MSR_TM_ACTIVE(current->thread.regs->msr)) { |
1491 | tm_enable(); | |
1492 | tm_abort(TM_CAUSE_TLBI); | |
1493 | } | |
1494 | #endif | |
1da177e4 LT |
1495 | } |
1496 | ||
f1581bf1 AK |
1497 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
1498 | void flush_hash_hugepage(unsigned long vsid, unsigned long addr, | |
aefa5688 AK |
1499 | pmd_t *pmdp, unsigned int psize, int ssize, |
1500 | unsigned long flags) | |
f1581bf1 AK |
1501 | { |
1502 | int i, max_hpte_count, valid; | |
1503 | unsigned long s_addr; | |
1504 | unsigned char *hpte_slot_array; | |
1505 | unsigned long hidx, shift, vpn, hash, slot; | |
aefa5688 | 1506 | int local = flags & HPTE_LOCAL_UPDATE; |
f1581bf1 AK |
1507 | |
1508 | s_addr = addr & HPAGE_PMD_MASK; | |
1509 | hpte_slot_array = get_hpte_slot_array(pmdp); | |
1510 | /* | |
1511 | * IF we try to do a HUGE PTE update after a withdraw is done. | |
1512 | * we will find the below NULL. This happens when we do | |
1513 | * split_huge_page_pmd | |
1514 | */ | |
1515 | if (!hpte_slot_array) | |
1516 | return; | |
1517 | ||
d557b098 AK |
1518 | if (ppc_md.hugepage_invalidate) { |
1519 | ppc_md.hugepage_invalidate(vsid, s_addr, hpte_slot_array, | |
1520 | psize, ssize, local); | |
1521 | goto tm_abort; | |
1522 | } | |
f1581bf1 AK |
1523 | /* |
1524 | * No bluk hpte removal support, invalidate each entry | |
1525 | */ | |
1526 | shift = mmu_psize_defs[psize].shift; | |
1527 | max_hpte_count = HPAGE_PMD_SIZE >> shift; | |
1528 | for (i = 0; i < max_hpte_count; i++) { | |
1529 | /* | |
1530 | * 8 bits per each hpte entries | |
1531 | * 000| [ secondary group (one bit) | hidx (3 bits) | valid bit] | |
1532 | */ | |
1533 | valid = hpte_valid(hpte_slot_array, i); | |
1534 | if (!valid) | |
1535 | continue; | |
1536 | hidx = hpte_hash_index(hpte_slot_array, i); | |
1537 | ||
1538 | /* get the vpn */ | |
1539 | addr = s_addr + (i * (1ul << shift)); | |
1540 | vpn = hpt_vpn(addr, vsid, ssize); | |
1541 | hash = hpt_hash(vpn, shift, ssize); | |
1542 | if (hidx & _PTEIDX_SECONDARY) | |
1543 | hash = ~hash; | |
1544 | ||
1545 | slot = (hash & htab_hash_mask) * HPTES_PER_GROUP; | |
1546 | slot += hidx & _PTEIDX_GROUP_IX; | |
1547 | ppc_md.hpte_invalidate(slot, vpn, psize, | |
d557b098 AK |
1548 | MMU_PAGE_16M, ssize, local); |
1549 | } | |
1550 | tm_abort: | |
1551 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
1552 | /* Transactions are not aborted by tlbiel, only tlbie. | |
1553 | * Without, syncing a page back to a block device w/ PIO could pick up | |
1554 | * transactional data (bad!) so we force an abort here. Before the | |
1555 | * sync the page will be made read-only, which will flush_hash_page. | |
1556 | * BIG ISSUE here: if the kernel uses a page from userspace without | |
1557 | * unmapping it first, it may see the speculated version. | |
1558 | */ | |
1559 | if (local && cpu_has_feature(CPU_FTR_TM) && | |
1560 | current->thread.regs && | |
1561 | MSR_TM_ACTIVE(current->thread.regs->msr)) { | |
1562 | tm_enable(); | |
1563 | tm_abort(TM_CAUSE_TLBI); | |
f1581bf1 | 1564 | } |
d557b098 | 1565 | #endif |
2e826695 | 1566 | return; |
f1581bf1 AK |
1567 | } |
1568 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ | |
1569 | ||
61b1a942 | 1570 | void flush_hash_range(unsigned long number, int local) |
1da177e4 | 1571 | { |
3c726f8d | 1572 | if (ppc_md.flush_hash_range) |
61b1a942 | 1573 | ppc_md.flush_hash_range(number, local); |
3c726f8d | 1574 | else { |
1da177e4 | 1575 | int i; |
61b1a942 | 1576 | struct ppc64_tlb_batch *batch = |
69111bac | 1577 | this_cpu_ptr(&ppc64_tlb_batch); |
1da177e4 LT |
1578 | |
1579 | for (i = 0; i < number; i++) | |
5524a27d | 1580 | flush_hash_page(batch->vpn[i], batch->pte[i], |
1189be65 | 1581 | batch->psize, batch->ssize, local); |
1da177e4 LT |
1582 | } |
1583 | } | |
1584 | ||
1da177e4 LT |
1585 | /* |
1586 | * low_hash_fault is called when we the low level hash code failed | |
1587 | * to instert a PTE due to an hypervisor error | |
1588 | */ | |
fa28237c | 1589 | void low_hash_fault(struct pt_regs *regs, unsigned long address, int rc) |
1da177e4 | 1590 | { |
ba12eede LZ |
1591 | enum ctx_state prev_state = exception_enter(); |
1592 | ||
1da177e4 | 1593 | if (user_mode(regs)) { |
fa28237c PM |
1594 | #ifdef CONFIG_PPC_SUBPAGE_PROT |
1595 | if (rc == -2) | |
1596 | _exception(SIGSEGV, regs, SEGV_ACCERR, address); | |
1597 | else | |
1598 | #endif | |
1599 | _exception(SIGBUS, regs, BUS_ADRERR, address); | |
1600 | } else | |
1601 | bad_page_fault(regs, address, SIGBUS); | |
ba12eede LZ |
1602 | |
1603 | exception_exit(prev_state); | |
1da177e4 | 1604 | } |
370a908d | 1605 | |
b170bd3d LZ |
1606 | long hpte_insert_repeating(unsigned long hash, unsigned long vpn, |
1607 | unsigned long pa, unsigned long rflags, | |
1608 | unsigned long vflags, int psize, int ssize) | |
1609 | { | |
1610 | unsigned long hpte_group; | |
1611 | long slot; | |
1612 | ||
1613 | repeat: | |
1614 | hpte_group = ((hash & htab_hash_mask) * | |
1615 | HPTES_PER_GROUP) & ~0x7UL; | |
1616 | ||
1617 | /* Insert into the hash table, primary slot */ | |
1618 | slot = ppc_md.hpte_insert(hpte_group, vpn, pa, rflags, vflags, | |
b1022fbd | 1619 | psize, psize, ssize); |
b170bd3d LZ |
1620 | |
1621 | /* Primary is full, try the secondary */ | |
1622 | if (unlikely(slot == -1)) { | |
1623 | hpte_group = ((~hash & htab_hash_mask) * | |
1624 | HPTES_PER_GROUP) & ~0x7UL; | |
1625 | slot = ppc_md.hpte_insert(hpte_group, vpn, pa, rflags, | |
1626 | vflags | HPTE_V_SECONDARY, | |
b1022fbd | 1627 | psize, psize, ssize); |
b170bd3d LZ |
1628 | if (slot == -1) { |
1629 | if (mftb() & 0x1) | |
1630 | hpte_group = ((hash & htab_hash_mask) * | |
1631 | HPTES_PER_GROUP)&~0x7UL; | |
1632 | ||
1633 | ppc_md.hpte_remove(hpte_group); | |
1634 | goto repeat; | |
1635 | } | |
1636 | } | |
1637 | ||
1638 | return slot; | |
1639 | } | |
1640 | ||
370a908d BH |
1641 | #ifdef CONFIG_DEBUG_PAGEALLOC |
1642 | static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi) | |
1643 | { | |
016af59f | 1644 | unsigned long hash; |
1189be65 | 1645 | unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize); |
5524a27d | 1646 | unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize); |
09f3f326 | 1647 | unsigned long mode = htab_convert_pte_flags(pgprot_val(PAGE_KERNEL)); |
016af59f | 1648 | long ret; |
370a908d | 1649 | |
5524a27d | 1650 | hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize); |
370a908d | 1651 | |
c60ac569 AK |
1652 | /* Don't create HPTE entries for bad address */ |
1653 | if (!vsid) | |
1654 | return; | |
016af59f LZ |
1655 | |
1656 | ret = hpte_insert_repeating(hash, vpn, __pa(vaddr), mode, | |
1657 | HPTE_V_BOLTED, | |
1658 | mmu_linear_psize, mmu_kernel_ssize); | |
1659 | ||
370a908d BH |
1660 | BUG_ON (ret < 0); |
1661 | spin_lock(&linear_map_hash_lock); | |
1662 | BUG_ON(linear_map_hash_slots[lmi] & 0x80); | |
1663 | linear_map_hash_slots[lmi] = ret | 0x80; | |
1664 | spin_unlock(&linear_map_hash_lock); | |
1665 | } | |
1666 | ||
1667 | static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi) | |
1668 | { | |
1189be65 PM |
1669 | unsigned long hash, hidx, slot; |
1670 | unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize); | |
5524a27d | 1671 | unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize); |
370a908d | 1672 | |
5524a27d | 1673 | hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize); |
370a908d BH |
1674 | spin_lock(&linear_map_hash_lock); |
1675 | BUG_ON(!(linear_map_hash_slots[lmi] & 0x80)); | |
1676 | hidx = linear_map_hash_slots[lmi] & 0x7f; | |
1677 | linear_map_hash_slots[lmi] = 0; | |
1678 | spin_unlock(&linear_map_hash_lock); | |
1679 | if (hidx & _PTEIDX_SECONDARY) | |
1680 | hash = ~hash; | |
1681 | slot = (hash & htab_hash_mask) * HPTES_PER_GROUP; | |
1682 | slot += hidx & _PTEIDX_GROUP_IX; | |
db3d8534 AK |
1683 | ppc_md.hpte_invalidate(slot, vpn, mmu_linear_psize, mmu_linear_psize, |
1684 | mmu_kernel_ssize, 0); | |
370a908d BH |
1685 | } |
1686 | ||
031bc574 | 1687 | void __kernel_map_pages(struct page *page, int numpages, int enable) |
370a908d BH |
1688 | { |
1689 | unsigned long flags, vaddr, lmi; | |
1690 | int i; | |
1691 | ||
1692 | local_irq_save(flags); | |
1693 | for (i = 0; i < numpages; i++, page++) { | |
1694 | vaddr = (unsigned long)page_address(page); | |
1695 | lmi = __pa(vaddr) >> PAGE_SHIFT; | |
1696 | if (lmi >= linear_map_hash_count) | |
1697 | continue; | |
1698 | if (enable) | |
1699 | kernel_map_linear_page(vaddr, lmi); | |
1700 | else | |
1701 | kernel_unmap_linear_page(vaddr, lmi); | |
1702 | } | |
1703 | local_irq_restore(flags); | |
1704 | } | |
1705 | #endif /* CONFIG_DEBUG_PAGEALLOC */ | |
cd3db0c4 | 1706 | |
756d08d1 | 1707 | void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base, |
cd3db0c4 BH |
1708 | phys_addr_t first_memblock_size) |
1709 | { | |
1710 | /* We don't currently support the first MEMBLOCK not mapping 0 | |
1711 | * physical on those processors | |
1712 | */ | |
1713 | BUG_ON(first_memblock_base != 0); | |
1714 | ||
1715 | /* On LPAR systems, the first entry is our RMA region, | |
1716 | * non-LPAR 64-bit hash MMU systems don't have a limitation | |
1717 | * on real mode access, but using the first entry works well | |
1718 | * enough. We also clamp it to 1G to avoid some funky things | |
1719 | * such as RTAS bugs etc... | |
1720 | */ | |
1721 | ppc64_rma_size = min_t(u64, first_memblock_size, 0x40000000); | |
1722 | ||
1723 | /* Finally limit subsequent allocations */ | |
1724 | memblock_set_current_limit(ppc64_rma_size); | |
1725 | } |