[linux-2.6-block.git] / arch / powerpc / kernel / misc_32.S

/*
 * This file contains miscellaneous low-level functions.
 *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
 *
 * Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
 * and Paul Mackerras.
 *
 * kexec bits:
 * Copyright (C) 2002-2003 Eric Biederman  <ebiederm@xmission.com>
 * GameCube/ppc32 port Copyright (C) 2004 Albert Herranz
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 *
 */

#include <linux/sys.h>
#include <asm/unistd.h>
#include <asm/errno.h>
#include <asm/reg.h>
#include <asm/page.h>
#include <asm/cache.h>
#include <asm/cputable.h>
#include <asm/mmu.h>
#include <asm/ppc_asm.h>
#include <asm/thread_info.h>
#include <asm/asm-offsets.h>
#include <asm/processor.h>
#include <asm/kexec.h>
#include <asm/bug.h>

	.text

#ifdef CONFIG_IRQSTACKS
_GLOBAL(call_do_softirq)
	mflr	r0
	stw	r0,4(r1)
	stwu	r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r3)
	mr	r1,r3
	bl	__do_softirq
	lwz	r1,0(r1)
	lwz	r0,4(r1)
	mtlr	r0
	blr

_GLOBAL(call_handle_irq)
	mflr	r0
	stw	r0,4(r1)
	mtctr	r6
	stwu	r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r5)
	mr	r1,r5
	bctrl
	lwz	r1,0(r1)
	lwz	r0,4(r1)
	mtlr	r0
	blr
#endif /* CONFIG_IRQSTACKS */

/*
 * This returns the high 64 bits of the product of two 64-bit numbers.
 */
_GLOBAL(mulhdu)
	cmpwi	r6,0
	cmpwi	cr1,r3,0
	mr	r10,r4
	mulhwu	r4,r4,r5
	beq	1f
	mulhwu	r0,r10,r6
	mullw	r7,r10,r5
	addc	r7,r0,r7
	addze	r4,r4
1:	beqlr	cr1		/* all done if high part of A is 0 */
	mr	r10,r3
	mullw	r9,r3,r5
	mulhwu	r3,r3,r5
	beq	2f
	mullw	r0,r10,r6
	mulhwu	r8,r10,r6
	addc	r7,r0,r7
	adde	r4,r4,r8
	addze	r3,r3
2:	addc	r4,r4,r9
	addze	r3,r3
	blr

/*
 * sub_reloc_offset(x) returns x - reloc_offset().
 */
_GLOBAL(sub_reloc_offset)
	mflr	r0
	bl	1f
1:	mflr	r5
	lis	r4,1b@ha
	addi	r4,r4,1b@l
	subf	r5,r4,r5
	subf	r3,r5,r3
	mtlr	r0
	blr

/*
 * reloc_got2 runs through the .got2 section adding an offset
 * to each entry.
 */
_GLOBAL(reloc_got2)
	mflr	r11
	lis	r7,__got2_start@ha
	addi	r7,r7,__got2_start@l
	lis	r8,__got2_end@ha
	addi	r8,r8,__got2_end@l
	subf	r8,r7,r8
	srwi.	r8,r8,2
	beqlr
	mtctr	r8
	bl	1f
1:	mflr	r0
	lis	r4,1b@ha
	addi	r4,r4,1b@l
	subf	r0,r4,r0
	add	r7,r0,r7
2:	lwz	r0,0(r7)
	add	r0,r0,r3
	stw	r0,0(r7)
	addi	r7,r7,4
	bdnz	2b
	mtlr	r11
	blr

/*
 * call_setup_cpu - call the setup_cpu function for this cpu
 * r3 = data offset, r24 = cpu number
 *
 * Setup function is called with:
 *   r3 = data offset
 *   r4 = ptr to CPU spec (relocated)
 */
_GLOBAL(call_setup_cpu)
	addis	r4,r3,cur_cpu_spec@ha
	addi	r4,r4,cur_cpu_spec@l
	lwz	r4,0(r4)
	add	r4,r4,r3
	lwz	r5,CPU_SPEC_SETUP(r4)
	cmpwi	0,r5,0
	add	r5,r5,r3
	beqlr
	mtctr	r5
	bctr

#if defined(CONFIG_CPU_FREQ_PMAC) && defined(CONFIG_6xx)

/* This gets called by via-pmu.c to switch the PLL selection
 * on 750fx CPU. This function should really be moved to some
 * other place (as most of the cpufreq code in via-pmu
 */
_GLOBAL(low_choose_750fx_pll)
	/* Clear MSR:EE */
	mfmsr	r7
	rlwinm	r0,r7,0,17,15
	mtmsr	r0

	/* If switching to PLL1, disable HID0:BTIC */
	cmplwi	cr0,r3,0
	beq	1f
	mfspr	r5,SPRN_HID0
	rlwinm	r5,r5,0,27,25
	sync
	mtspr	SPRN_HID0,r5
	isync
	sync

1:
	/* Calc new HID1 value */
	mfspr	r4,SPRN_HID1	/* Build a HID1:PS bit from parameter */
	rlwinm	r5,r3,16,15,15	/* Clear out HID1:PS from value read */
	rlwinm	r4,r4,0,16,14	/* Could have I used rlwimi here ? */
	or	r4,r4,r5
	mtspr	SPRN_HID1,r4

	/* Store new HID1 image */
	rlwinm	r6,r1,0,0,(31-THREAD_SHIFT)
	lwz	r6,TI_CPU(r6)
	slwi	r6,r6,2
	addis	r6,r6,nap_save_hid1@ha
	stw	r4,nap_save_hid1@l(r6)

	/* If switching to PLL0, enable HID0:BTIC */
	cmplwi	cr0,r3,0
	bne	1f
	mfspr	r5,SPRN_HID0
	ori	r5,r5,HID0_BTIC
	sync
	mtspr	SPRN_HID0,r5
	isync
	sync

1:
	/* Return */
	mtmsr	r7
	blr

_GLOBAL(low_choose_7447a_dfs)
	/* Clear MSR:EE */
	mfmsr	r7
	rlwinm	r0,r7,0,17,15
	mtmsr	r0
	
	/* Calc new HID1 value */
	mfspr	r4,SPRN_HID1
	insrwi	r4,r3,1,9	/* insert parameter into bit 9 */
	sync
	mtspr	SPRN_HID1,r4
	sync
	isync

	/* Return */
	mtmsr	r7
	blr

#endif /* CONFIG_CPU_FREQ_PMAC && CONFIG_6xx */

/*
 * complement mask on the msr then "or" some values on.
 *     _nmask_and_or_msr(nmask, value_to_or)
 */
_GLOBAL(_nmask_and_or_msr)
	mfmsr	r0		/* Get current msr */
	andc	r0,r0,r3	/* And off the bits set in r3 (first parm) */
	or	r0,r0,r4	/* Or on the bits in r4 (second parm) */
	SYNC			/* Some chip revs have problems here... */
	mtmsr	r0		/* Update machine state */
	isync
	blr			/* Done */

#ifdef CONFIG_40x

/*
 * Do an IO access in real mode
 */
_GLOBAL(real_readb)
	mfmsr	r7
	ori	r0,r7,MSR_DR
	xori	r0,r0,MSR_DR
	sync
	mtmsr	r0
	sync
	isync
	lbz	r3,0(r3)
	sync
	mtmsr	r7
	sync
	isync
	blr

	/*
 * Do an IO access in real mode
 */
_GLOBAL(real_writeb)
	mfmsr	r7
	ori	r0,r7,MSR_DR
	xori	r0,r0,MSR_DR
	sync
	mtmsr	r0
	sync
	isync
	stb	r3,0(r4)
	sync
	mtmsr	r7
	sync
	isync
	blr

#endif /* CONFIG_40x */


/*
 * Flush instruction cache.
 * This is a no-op on the 601.
 */
_GLOBAL(flush_instruction_cache)
#if defined(CONFIG_8xx)
	isync
	lis	r5, IDC_INVALL@h
	mtspr	SPRN_IC_CST, r5
#elif defined(CONFIG_4xx)
#ifdef CONFIG_403GCX
	li      r3, 512
	mtctr   r3
	lis     r4, KERNELBASE@h
1:	iccci   0, r4
	addi    r4, r4, 16
	bdnz    1b
#else
	lis	r3, KERNELBASE@h
	iccci	0,r3
#endif
#elif CONFIG_FSL_BOOKE
BEGIN_FTR_SECTION
	mfspr   r3,SPRN_L1CSR0
	ori     r3,r3,L1CSR0_CFI|L1CSR0_CLFC
	/* msync; isync recommended here */
	mtspr   SPRN_L1CSR0,r3
	isync
	blr
END_FTR_SECTION_IFSET(CPU_FTR_UNIFIED_ID_CACHE)
	mfspr	r3,SPRN_L1CSR1
	ori	r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR
	mtspr	SPRN_L1CSR1,r3
#else
	mfspr	r3,SPRN_PVR
	rlwinm	r3,r3,16,16,31
	cmpwi	0,r3,1
	beqlr			/* for 601, do nothing */
	/* 603/604 processor - use invalidate-all bit in HID0 */
	mfspr	r3,SPRN_HID0
	ori	r3,r3,HID0_ICFI
	mtspr	SPRN_HID0,r3
#endif /* CONFIG_8xx/4xx */
	isync
	blr

/*
 * Write any modified data cache blocks out to memory
 * and invalidate the corresponding instruction cache blocks.
 * This is a no-op on the 601.
 *
 * flush_icache_range(unsigned long start, unsigned long stop)
 */
_KPROBE(__flush_icache_range)
BEGIN_FTR_SECTION
	blr				/* for 601, do nothing */
END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
	li	r5,L1_CACHE_BYTES-1
	andc	r3,r3,r5
	subf	r4,r3,r4
	add	r4,r4,r5
	srwi.	r4,r4,L1_CACHE_SHIFT
	beqlr
	mtctr	r4
	mr	r6,r3
1:	dcbst	0,r3
	addi	r3,r3,L1_CACHE_BYTES
	bdnz	1b
	sync				/* wait for dcbst's to get to ram */
#ifndef CONFIG_44x
	mtctr	r4
2:	icbi	0,r6
	addi	r6,r6,L1_CACHE_BYTES
	bdnz	2b
#else
	/* Flash invalidate on 44x because we are passed kmapped addresses and
	   this doesn't work for userspace pages due to the virtually tagged
	   icache.  Sigh. */
	iccci	0, r0
#endif
	sync				/* additional sync needed on g4 */
	isync
	blr
/*
 * Write any modified data cache blocks out to memory.
 * Does not invalidate the corresponding cache lines (especially for
 * any corresponding instruction cache).
 *
 * clean_dcache_range(unsigned long start, unsigned long stop)
 */
_GLOBAL(clean_dcache_range)
	li	r5,L1_CACHE_BYTES-1
	andc	r3,r3,r5
	subf	r4,r3,r4
	add	r4,r4,r5
	srwi.	r4,r4,L1_CACHE_SHIFT
	beqlr
	mtctr	r4

1:	dcbst	0,r3
	addi	r3,r3,L1_CACHE_BYTES
	bdnz	1b
	sync				/* wait for dcbst's to get to ram */
	blr

/*
 * Write any modified data cache blocks out to memory and invalidate them.
 * Does not invalidate the corresponding instruction cache blocks.
 *
 * flush_dcache_range(unsigned long start, unsigned long stop)
 */
_GLOBAL(flush_dcache_range)
	li	r5,L1_CACHE_BYTES-1
	andc	r3,r3,r5
	subf	r4,r3,r4
	add	r4,r4,r5
	srwi.	r4,r4,L1_CACHE_SHIFT
	beqlr
	mtctr	r4

1:	dcbf	0,r3
	addi	r3,r3,L1_CACHE_BYTES
	bdnz	1b
	sync				/* wait for dcbst's to get to ram */
	blr

/*
 * Like above, but invalidate the D-cache.  This is used by the 8xx
 * to invalidate the cache so the PPC core doesn't get stale data
 * from the CPM (no cache snooping here :-).
 *
 * invalidate_dcache_range(unsigned long start, unsigned long stop)
 */
_GLOBAL(invalidate_dcache_range)
	li	r5,L1_CACHE_BYTES-1
	andc	r3,r3,r5
	subf	r4,r3,r4
	add	r4,r4,r5
	srwi.	r4,r4,L1_CACHE_SHIFT
	beqlr
	mtctr	r4

1:	dcbi	0,r3
	addi	r3,r3,L1_CACHE_BYTES
	bdnz	1b
	sync				/* wait for dcbi's to get to ram */
	blr

/*
 * Flush a particular page from the data cache to RAM.
 * Note: this is necessary because the instruction cache does *not*
 * snoop from the data cache.
 * This is a no-op on the 601 which has a unified cache.
 *
 *	void __flush_dcache_icache(void *page)
 */
_GLOBAL(__flush_dcache_icache)
BEGIN_FTR_SECTION
	blr
END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
	rlwinm	r3,r3,0,0,31-PAGE_SHIFT		/* Get page base address */
	li	r4,PAGE_SIZE/L1_CACHE_BYTES	/* Number of lines in a page */
	mtctr	r4
	mr	r6,r3
0:	dcbst	0,r3				/* Write line to ram */
	addi	r3,r3,L1_CACHE_BYTES
	bdnz	0b
	sync
#ifndef CONFIG_44x
	/* We don't flush the icache on 44x. Those have a virtual icache
	 * and we don't have access to the virtual address here (it's
	 * not the page vaddr but where it's mapped in user space). The
	 * flushing of the icache on these is handled elsewhere, when
	 * a change in the address space occurs, before returning to
	 * user space
	 */
	mtctr	r4
1:	icbi	0,r6
	addi	r6,r6,L1_CACHE_BYTES
	bdnz	1b
	sync
	isync
#endif /* CONFIG_44x */
	blr

/*
 * Flush a particular page from the data cache to RAM, identified
 * by its physical address.  We turn off the MMU so we can just use
 * the physical address (this may be a highmem page without a kernel
 * mapping).
 *
 *	void __flush_dcache_icache_phys(unsigned long physaddr)
 */
_GLOBAL(__flush_dcache_icache_phys)
BEGIN_FTR_SECTION
	blr					/* for 601, do nothing */
END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
	mfmsr	r10
	rlwinm	r0,r10,0,28,26			/* clear DR */
	mtmsr	r0
	isync
	rlwinm	r3,r3,0,0,31-PAGE_SHIFT		/* Get page base address */
	li	r4,PAGE_SIZE/L1_CACHE_BYTES	/* Number of lines in a page */
	mtctr	r4
	mr	r6,r3
0:	dcbst	0,r3				/* Write line to ram */
	addi	r3,r3,L1_CACHE_BYTES
	bdnz	0b
	sync
	mtctr	r4
1:	icbi	0,r6
	addi	r6,r6,L1_CACHE_BYTES
	bdnz	1b
	sync
	mtmsr	r10				/* restore DR */
	isync
	blr

/*
 * Clear pages using the dcbz instruction, which doesn't cause any
 * memory traffic (except to write out any cache lines which get
 * displaced).  This only works on cacheable memory.
 *
 * void clear_pages(void *page, int order) ;
 */
_GLOBAL(clear_pages)
	li	r0,PAGE_SIZE/L1_CACHE_BYTES
	slw	r0,r0,r4
	mtctr	r0
1:	dcbz	0,r3
	addi	r3,r3,L1_CACHE_BYTES
	bdnz	1b
	blr

/*
 * Copy a whole page.  We use the dcbz instruction on the destination
 * to reduce memory traffic (it eliminates the unnecessary reads of
 * the destination into cache).  This requires that the destination
 * is cacheable.
 */
#define COPY_16_BYTES		\
	lwz	r6,4(r4);	\
	lwz	r7,8(r4);	\
	lwz	r8,12(r4);	\
	lwzu	r9,16(r4);	\
	stw	r6,4(r3);	\
	stw	r7,8(r3);	\
	stw	r8,12(r3);	\
	stwu	r9,16(r3)

_GLOBAL(copy_page)
	addi	r3,r3,-4
	addi	r4,r4,-4

	li	r5,4

#if MAX_COPY_PREFETCH > 1
	li	r0,MAX_COPY_PREFETCH
	li	r11,4
	mtctr	r0
11:	dcbt	r11,r4
	addi	r11,r11,L1_CACHE_BYTES
	bdnz	11b
#else /* MAX_COPY_PREFETCH == 1 */
	dcbt	r5,r4
	li	r11,L1_CACHE_BYTES+4
#endif /* MAX_COPY_PREFETCH */
	li	r0,PAGE_SIZE/L1_CACHE_BYTES - MAX_COPY_PREFETCH
	crclr	4*cr0+eq
2:
	mtctr	r0
1:
	dcbt	r11,r4
	dcbz	r5,r3
	COPY_16_BYTES
#if L1_CACHE_BYTES >= 32
	COPY_16_BYTES
#if L1_CACHE_BYTES >= 64
	COPY_16_BYTES
	COPY_16_BYTES
#if L1_CACHE_BYTES >= 128
	COPY_16_BYTES
	COPY_16_BYTES
	COPY_16_BYTES
	COPY_16_BYTES
#endif
#endif
#endif
	bdnz	1b
	beqlr
	crnot	4*cr0+eq,4*cr0+eq
	li	r0,MAX_COPY_PREFETCH
	li	r11,4
	b	2b

/*
 * void atomic_clear_mask(atomic_t mask, atomic_t *addr)
 * void atomic_set_mask(atomic_t mask, atomic_t *addr);
 */
_GLOBAL(atomic_clear_mask)
10:	lwarx	r5,0,r4
	andc	r5,r5,r3
	PPC405_ERR77(0,r4)
	stwcx.	r5,0,r4
	bne-	10b
	blr
_GLOBAL(atomic_set_mask)
10:	lwarx	r5,0,r4
	or	r5,r5,r3
	PPC405_ERR77(0,r4)
	stwcx.	r5,0,r4
	bne-	10b
	blr

/*
 * Extended precision shifts.
 *
 * Updated to be valid for shift counts from 0 to 63 inclusive.
 * -- Gabriel
 *
 * R3/R4 has 64 bit value
 * R5    has shift count
 * result in R3/R4
 *
 *  ashrdi3: arithmetic right shift (sign propagation)	
 *  lshrdi3: logical right shift
 *  ashldi3: left shift
 */
_GLOBAL(__ashrdi3)
	subfic	r6,r5,32
	srw	r4,r4,r5	# LSW = count > 31 ? 0 : LSW >> count
	addi	r7,r5,32	# could be xori, or addi with -32
	slw	r6,r3,r6	# t1 = count > 31 ? 0 : MSW << (32-count)
	rlwinm	r8,r7,0,32	# t3 = (count < 32) ? 32 : 0
	sraw	r7,r3,r7	# t2 = MSW >> (count-32)
	or	r4,r4,r6	# LSW |= t1
	slw	r7,r7,r8	# t2 = (count < 32) ? 0 : t2
	sraw	r3,r3,r5	# MSW = MSW >> count
	or	r4,r4,r7	# LSW |= t2
	blr

_GLOBAL(__ashldi3)
	subfic	r6,r5,32
	slw	r3,r3,r5	# MSW = count > 31 ? 0 : MSW << count
	addi	r7,r5,32	# could be xori, or addi with -32
	srw	r6,r4,r6	# t1 = count > 31 ? 0 : LSW >> (32-count)
	slw	r7,r4,r7	# t2 = count < 32 ? 0 : LSW << (count-32)
	or	r3,r3,r6	# MSW |= t1
	slw	r4,r4,r5	# LSW = LSW << count
	or	r3,r3,r7	# MSW |= t2
	blr

_GLOBAL(__lshrdi3)
	subfic	r6,r5,32
	srw	r4,r4,r5	# LSW = count > 31 ? 0 : LSW >> count
	addi	r7,r5,32	# could be xori, or addi with -32
	slw	r6,r3,r6	# t1 = count > 31 ? 0 : MSW << (32-count)
	srw	r7,r3,r7	# t2 = count < 32 ? 0 : MSW >> (count-32)
	or	r4,r4,r6	# LSW |= t1
	srw	r3,r3,r5	# MSW = MSW >> count
	or	r4,r4,r7	# LSW |= t2
	blr

/*
 * 64-bit comparison: __ucmpdi2(u64 a, u64 b)
 * Returns 0 if a < b, 1 if a == b, 2 if a > b.
 */
_GLOBAL(__ucmpdi2)
	cmplw	r3,r5
	li	r3,1
	bne	1f
	cmplw	r4,r6
	beqlr
1:	li	r3,0
	bltlr
	li	r3,2
	blr

_GLOBAL(abs)
	srawi	r4,r3,31
	xor	r3,r3,r4
	sub	r3,r3,r4
	blr

/*
 * Create a kernel thread
 *   kernel_thread(fn, arg, flags)
 */
_GLOBAL(kernel_thread)
	stwu	r1,-16(r1)
	stw	r30,8(r1)
	stw	r31,12(r1)
	mr	r30,r3		/* function */
	mr	r31,r4		/* argument */
	ori	r3,r5,CLONE_VM	/* flags */
	oris	r3,r3,CLONE_UNTRACED>>16
	li	r4,0		/* new sp (unused) */
	li	r0,__NR_clone
	sc
	bns+	1f		/* did system call indicate error? */
	neg	r3,r3		/* if so, make return code negative */
1:	cmpwi	0,r3,0		/* parent or child? */
	bne	2f		/* return if parent */
	li	r0,0		/* make top-level stack frame */
	stwu	r0,-16(r1)
	mtlr	r30		/* fn addr in lr */
	mr	r3,r31		/* load arg and call fn */
	PPC440EP_ERR42
	blrl
	li	r0,__NR_exit	/* exit if function returns */
	li	r3,0
	sc
2:	lwz	r30,8(r1)
	lwz	r31,12(r1)
	addi	r1,r1,16
	blr

/*
 * This routine is just here to keep GCC happy - sigh...
 */
_GLOBAL(__main)
	blr

#ifdef CONFIG_KEXEC
	/*
	 * Must be relocatable PIC code callable as a C function.
	 */
	.globl relocate_new_kernel
relocate_new_kernel:
	/* r3 = page_list   */
	/* r4 = reboot_code_buffer */
	/* r5 = start_address      */

	li	r0, 0

	/*
	 * Set Machine Status Register to a known status,
	 * switch the MMU off and jump to 1: in a single step.
	 */

	mr	r8, r0
	ori     r8, r8, MSR_RI|MSR_ME
	mtspr	SPRN_SRR1, r8
	addi	r8, r4, 1f - relocate_new_kernel
	mtspr	SPRN_SRR0, r8
	sync
	rfi

1:
	/* from this point address translation is turned off */
	/* and interrupts are disabled */

	/* set a new stack at the bottom of our page... */
	/* (not really needed now) */
	addi	r1, r4, KEXEC_CONTROL_PAGE_SIZE - 8 /* for LR Save+Back Chain */
	stw	r0, 0(r1)

	/* Do the copies */
	li	r6, 0 /* checksum */
	mr	r0, r3
	b	1f

0:	/* top, read another word for the indirection page */
	lwzu	r0, 4(r3)

1:
	/* is it a destination page? (r8) */
	rlwinm.	r7, r0, 0, 31, 31 /* IND_DESTINATION (1<<0) */
	beq	2f

	rlwinm	r8, r0, 0, 0, 19 /* clear kexec flags, page align */
	b	0b

2:	/* is it an indirection page? (r3) */
	rlwinm.	r7, r0, 0, 30, 30 /* IND_INDIRECTION (1<<1) */
	beq	2f

	rlwinm	r3, r0, 0, 0, 19 /* clear kexec flags, page align */
	subi	r3, r3, 4
	b	0b

2:	/* are we done? */
	rlwinm.	r7, r0, 0, 29, 29 /* IND_DONE (1<<2) */
	beq	2f
	b	3f

2:	/* is it a source page? (r9) */
	rlwinm.	r7, r0, 0, 28, 28 /* IND_SOURCE (1<<3) */
	beq	0b

	rlwinm	r9, r0, 0, 0, 19 /* clear kexec flags, page align */

	li	r7, PAGE_SIZE / 4
	mtctr   r7
	subi    r9, r9, 4
	subi    r8, r8, 4
9:
	lwzu    r0, 4(r9)  /* do the copy */
	xor	r6, r6, r0
	stwu    r0, 4(r8)
	dcbst	0, r8
	sync
	icbi	0, r8
	bdnz    9b

	addi    r9, r9, 4
	addi    r8, r8, 4
	b	0b

3:

	/* To be certain of avoiding problems with self-modifying code
	 * execute a serializing instruction here.
	 */
	isync
	sync

	/* jump to the entry point, usually the setup routine */
	mtlr	r5
	blrl

1:	b	1b

relocate_new_kernel_end:

	.globl relocate_new_kernel_size
relocate_new_kernel_size:
	.long relocate_new_kernel_end - relocate_new_kernel
#endif
Commit	Line	Data
9994a338 PM	1	/*
	2	* This file contains miscellaneous low-level functions.
	3	* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
	4	*
	5	* Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
	6	* and Paul Mackerras.
	7	*
3d1229d6 ME	8	* kexec bits:
	9	* Copyright (C) 2002-2003 Eric Biederman <ebiederm@xmission.com>
	10	* GameCube/ppc32 port Copyright (C) 2004 Albert Herranz
	11	*
9994a338 PM	12	* This program is free software; you can redistribute it and/or
	13	* modify it under the terms of the GNU General Public License
	14	* as published by the Free Software Foundation; either version
	15	* 2 of the License, or (at your option) any later version.
	16	*
	17	*/
	18
9994a338 PM	19	#include <linux/sys.h>
	20	#include <asm/unistd.h>
	21	#include <asm/errno.h>
	22	#include <asm/reg.h>
	23	#include <asm/page.h>
	24	#include <asm/cache.h>
	25	#include <asm/cputable.h>
	26	#include <asm/mmu.h>
	27	#include <asm/ppc_asm.h>
	28	#include <asm/thread_info.h>
	29	#include <asm/asm-offsets.h>
3d1229d6 ME	30	#include <asm/processor.h>
3d1229d6 ME	31	#include <asm/kexec.h>
f048aace	32	#include <asm/bug.h>
9994a338 PM	33
	34	.text
	35
85218827 KG	36	#ifdef CONFIG_IRQSTACKS
	37	_GLOBAL(call_do_softirq)
	38	mflr r0
	39	stw r0,4(r1)
	40	stwu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r3)
	41	mr r1,r3
	42	bl __do_softirq
	43	lwz r1,0(r1)
	44	lwz r0,4(r1)
	45	mtlr r0
	46	blr
	47
	48	_GLOBAL(call_handle_irq)
	49	mflr r0
	50	stw r0,4(r1)
	51	mtctr r6
	52	stwu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r5)
	53	mr r1,r5
	54	bctrl
	55	lwz r1,0(r1)
	56	lwz r0,4(r1)
	57	mtlr r0
	58	blr
	59	#endif /* CONFIG_IRQSTACKS */
	60
f2783c15 PM	61	/*
	62	* This returns the high 64 bits of the product of two 64-bit numbers.
	63	*/
	64	_GLOBAL(mulhdu)
	65	cmpwi r6,0
	66	cmpwi cr1,r3,0
	67	mr r10,r4
	68	mulhwu r4,r4,r5
	69	beq 1f
	70	mulhwu r0,r10,r6
	71	mullw r7,r10,r5
	72	addc r7,r0,r7
	73	addze r4,r4
	74	1: beqlr cr1 /* all done if high part of A is 0 */
	75	mr r10,r3
	76	mullw r9,r3,r5
	77	mulhwu r3,r3,r5
	78	beq 2f
	79	mullw r0,r10,r6
	80	mulhwu r8,r10,r6
	81	addc r7,r0,r7
	82	adde r4,r4,r8
	83	addze r3,r3
	84	2: addc r4,r4,r9
	85	addze r3,r3
	86	blr
	87
9994a338 PM	88	/*
	89	* sub_reloc_offset(x) returns x - reloc_offset().
	90	*/
	91	_GLOBAL(sub_reloc_offset)
	92	mflr r0
	93	bl 1f
	94	1: mflr r5
	95	lis r4,1b@ha
	96	addi r4,r4,1b@l
	97	subf r5,r4,r5
	98	subf r3,r5,r3
	99	mtlr r0
	100	blr
	101
	102	/*
	103	* reloc_got2 runs through the .got2 section adding an offset
	104	* to each entry.
	105	*/
	106	_GLOBAL(reloc_got2)
	107	mflr r11
	108	lis r7,__got2_start@ha
	109	addi r7,r7,__got2_start@l
	110	lis r8,__got2_end@ha
	111	addi r8,r8,__got2_end@l
	112	subf r8,r7,r8
	113	srwi. r8,r8,2
	114	beqlr
	115	mtctr r8
	116	bl 1f
	117	1: mflr r0
	118	lis r4,1b@ha
	119	addi r4,r4,1b@l
	120	subf r0,r4,r0
	121	add r7,r0,r7
	122	2: lwz r0,0(r7)
	123	add r0,r0,r3
	124	stw r0,0(r7)
	125	addi r7,r7,4
	126	bdnz 2b
	127	mtlr r11
	128	blr
	129
9994a338 PM	130	/*
	131	* call_setup_cpu - call the setup_cpu function for this cpu
	132	* r3 = data offset, r24 = cpu number
	133	*
	134	* Setup function is called with:
	135	* r3 = data offset
	136	* r4 = ptr to CPU spec (relocated)
	137	*/
	138	_GLOBAL(call_setup_cpu)
	139	addis r4,r3,cur_cpu_spec@ha
	140	addi r4,r4,cur_cpu_spec@l
	141	lwz r4,0(r4)
	142	add r4,r4,r3
	143	lwz r5,CPU_SPEC_SETUP(r4)
b26f100d	144	cmpwi 0,r5,0
9994a338 PM	145	add r5,r5,r3
	146	beqlr
	147	mtctr r5
	148	bctr
	149
	150	#if defined(CONFIG_CPU_FREQ_PMAC) && defined(CONFIG_6xx)
	151
	152	/* This gets called by via-pmu.c to switch the PLL selection
	153	* on 750fx CPU. This function should really be moved to some
	154	* other place (as most of the cpufreq code in via-pmu
	155	*/
	156	_GLOBAL(low_choose_750fx_pll)
	157	/* Clear MSR:EE */
	158	mfmsr r7
	159	rlwinm r0,r7,0,17,15
	160	mtmsr r0
	161
	162	/* If switching to PLL1, disable HID0:BTIC */
	163	cmplwi cr0,r3,0
	164	beq 1f
	165	mfspr r5,SPRN_HID0
	166	rlwinm r5,r5,0,27,25
	167	sync
	168	mtspr SPRN_HID0,r5
	169	isync
	170	sync
	171
	172	1:
	173	/* Calc new HID1 value */
	174	mfspr r4,SPRN_HID1 /* Build a HID1:PS bit from parameter */
	175	rlwinm r5,r3,16,15,15 /* Clear out HID1:PS from value read */
	176	rlwinm r4,r4,0,16,14 /* Could have I used rlwimi here ? */
	177	or r4,r4,r5
	178	mtspr SPRN_HID1,r4
	179
	180	/* Store new HID1 image */
f608600e	181	rlwinm r6,r1,0,0,(31-THREAD_SHIFT)
9994a338 PM	182	lwz r6,TI_CPU(r6)
	183	slwi r6,r6,2
	184	addis r6,r6,nap_save_hid1@ha
	185	stw r4,nap_save_hid1@l(r6)
	186
	187	/* If switching to PLL0, enable HID0:BTIC */
	188	cmplwi cr0,r3,0
	189	bne 1f
	190	mfspr r5,SPRN_HID0
	191	ori r5,r5,HID0_BTIC
	192	sync
	193	mtspr SPRN_HID0,r5
	194	isync
	195	sync
	196
	197	1:
	198	/* Return */
	199	mtmsr r7
	200	blr
	201
	202	_GLOBAL(low_choose_7447a_dfs)
	203	/* Clear MSR:EE */
	204	mfmsr r7
	205	rlwinm r0,r7,0,17,15
	206	mtmsr r0
	207
	208	/* Calc new HID1 value */
	209	mfspr r4,SPRN_HID1
	210	insrwi r4,r3,1,9 /* insert parameter into bit 9 */
	211	sync
	212	mtspr SPRN_HID1,r4
	213	sync
	214	isync
	215
	216	/* Return */
	217	mtmsr r7
	218	blr
	219
	220	#endif /* CONFIG_CPU_FREQ_PMAC && CONFIG_6xx */
	221
	222	/*
	223	* complement mask on the msr then "or" some values on.
	224	* _nmask_and_or_msr(nmask, value_to_or)
	225	*/
	226	_GLOBAL(_nmask_and_or_msr)
	227	mfmsr r0 /* Get current msr */
	228	andc r0,r0,r3 /* And off the bits set in r3 (first parm) */
	229	or r0,r0,r4 /* Or on the bits in r4 (second parm) */
	230	SYNC /* Some chip revs have problems here... */
	231	mtmsr r0 /* Update machine state */
	232	isync
	233	blr /* Done */
	234
9dae8afd BH	235	#ifdef CONFIG_40x
	236
	237	/*
	238	* Do an IO access in real mode
	239	*/
	240	_GLOBAL(real_readb)
	241	mfmsr r7
	242	ori r0,r7,MSR_DR
	243	xori r0,r0,MSR_DR
	244	sync
	245	mtmsr r0
	246	sync
	247	isync
	248	lbz r3,0(r3)
	249	sync
	250	mtmsr r7
	251	sync
	252	isync
	253	blr
	254
	255	/*
	256	* Do an IO access in real mode
	257	*/
	258	_GLOBAL(real_writeb)
	259	mfmsr r7
	260	ori r0,r7,MSR_DR
	261	xori r0,r0,MSR_DR
	262	sync
	263	mtmsr r0
	264	sync
	265	isync
	266	stb r3,0(r4)
	267	sync
	268	mtmsr r7
	269	sync
	270	isync
	271	blr
	272
	273	#endif /* CONFIG_40x */
9994a338	274
0ba3418b	275
9994a338 PM	276	/*
	277	* Flush instruction cache.
	278	* This is a no-op on the 601.
	279	*/
	280	_GLOBAL(flush_instruction_cache)
	281	#if defined(CONFIG_8xx)
	282	isync
	283	lis r5, IDC_INVALL@h
	284	mtspr SPRN_IC_CST, r5
	285	#elif defined(CONFIG_4xx)
	286	#ifdef CONFIG_403GCX
	287	li r3, 512
	288	mtctr r3
	289	lis r4, KERNELBASE@h
	290	1: iccci 0, r4
	291	addi r4, r4, 16
	292	bdnz 1b
	293	#else
	294	lis r3, KERNELBASE@h
	295	iccci 0,r3
	296	#endif
	297	#elif CONFIG_FSL_BOOKE
	298	BEGIN_FTR_SECTION
	299	mfspr r3,SPRN_L1CSR0
	300	ori r3,r3,L1CSR0_CFI\|L1CSR0_CLFC
	301	/* msync; isync recommended here */
	302	mtspr SPRN_L1CSR0,r3
	303	isync
	304	blr
4508dc21	305	END_FTR_SECTION_IFSET(CPU_FTR_UNIFIED_ID_CACHE)
9994a338 PM	306	mfspr r3,SPRN_L1CSR1
	307	ori r3,r3,L1CSR1_ICFI\|L1CSR1_ICLFR
	308	mtspr SPRN_L1CSR1,r3
	309	#else
	310	mfspr r3,SPRN_PVR
	311	rlwinm r3,r3,16,16,31
	312	cmpwi 0,r3,1
	313	beqlr /* for 601, do nothing */
	314	/* 603/604 processor - use invalidate-all bit in HID0 */
	315	mfspr r3,SPRN_HID0
	316	ori r3,r3,HID0_ICFI
	317	mtspr SPRN_HID0,r3
	318	#endif /* CONFIG_8xx/4xx */
	319	isync
	320	blr
	321
	322	/*
	323	* Write any modified data cache blocks out to memory
	324	* and invalidate the corresponding instruction cache blocks.
	325	* This is a no-op on the 601.
	326	*
	327	* flush_icache_range(unsigned long start, unsigned long stop)
	328	*/
b76e59d1	329	_KPROBE(__flush_icache_range)
9994a338 PM	330	BEGIN_FTR_SECTION
9994a338 PM	331	blr /* for 601, do nothing */
4508dc21	332	END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
7dffb720	333	li r5,L1_CACHE_BYTES-1
9994a338 PM	334	andc r3,r3,r5
	335	subf r4,r3,r4
	336	add r4,r4,r5
7dffb720	337	srwi. r4,r4,L1_CACHE_SHIFT
9994a338 PM	338	beqlr
	339	mtctr r4
	340	mr r6,r3
	341	1: dcbst 0,r3
7dffb720	342	addi r3,r3,L1_CACHE_BYTES
9994a338 PM	343	bdnz 1b
9994a338 PM	344	sync /* wait for dcbst's to get to ram */
14d75752	345	#ifndef CONFIG_44x
9994a338 PM	346	mtctr r4
9994a338 PM	347	2: icbi 0,r6
7dffb720	348	addi r6,r6,L1_CACHE_BYTES
9994a338	349	bdnz 2b
14d75752 JB	350	#else
	351	/* Flash invalidate on 44x because we are passed kmapped addresses and
	352	this doesn't work for userspace pages due to the virtually tagged
	353	icache. Sigh. */
	354	iccci 0, r0
	355	#endif
9994a338 PM	356	sync /* additional sync needed on g4 */
	357	isync
	358	blr
	359	/*
	360	* Write any modified data cache blocks out to memory.
	361	* Does not invalidate the corresponding cache lines (especially for
	362	* any corresponding instruction cache).
	363	*
	364	* clean_dcache_range(unsigned long start, unsigned long stop)
	365	*/
	366	_GLOBAL(clean_dcache_range)
7dffb720	367	li r5,L1_CACHE_BYTES-1
9994a338 PM	368	andc r3,r3,r5
	369	subf r4,r3,r4
	370	add r4,r4,r5
7dffb720	371	srwi. r4,r4,L1_CACHE_SHIFT
9994a338 PM	372	beqlr
	373	mtctr r4
	374
	375	1: dcbst 0,r3
7dffb720	376	addi r3,r3,L1_CACHE_BYTES
9994a338 PM	377	bdnz 1b
	378	sync /* wait for dcbst's to get to ram */
	379	blr
	380
	381	/*
	382	* Write any modified data cache blocks out to memory and invalidate them.
	383	* Does not invalidate the corresponding instruction cache blocks.
	384	*
	385	* flush_dcache_range(unsigned long start, unsigned long stop)
	386	*/
	387	_GLOBAL(flush_dcache_range)
7dffb720	388	li r5,L1_CACHE_BYTES-1
9994a338 PM	389	andc r3,r3,r5
	390	subf r4,r3,r4
	391	add r4,r4,r5
7dffb720	392	srwi. r4,r4,L1_CACHE_SHIFT
9994a338 PM	393	beqlr
	394	mtctr r4
	395
	396	1: dcbf 0,r3
7dffb720	397	addi r3,r3,L1_CACHE_BYTES
9994a338 PM	398	bdnz 1b
	399	sync /* wait for dcbst's to get to ram */
	400	blr
	401
	402	/*
	403	* Like above, but invalidate the D-cache. This is used by the 8xx
	404	* to invalidate the cache so the PPC core doesn't get stale data
	405	* from the CPM (no cache snooping here :-).
	406	*
	407	* invalidate_dcache_range(unsigned long start, unsigned long stop)
	408	*/
	409	_GLOBAL(invalidate_dcache_range)
7dffb720	410	li r5,L1_CACHE_BYTES-1
9994a338 PM	411	andc r3,r3,r5
	412	subf r4,r3,r4
	413	add r4,r4,r5
7dffb720	414	srwi. r4,r4,L1_CACHE_SHIFT
9994a338 PM	415	beqlr
	416	mtctr r4
	417
	418	1: dcbi 0,r3
7dffb720	419	addi r3,r3,L1_CACHE_BYTES
9994a338 PM	420	bdnz 1b
	421	sync /* wait for dcbi's to get to ram */
	422	blr
	423
9994a338 PM	424	/*
	425	* Flush a particular page from the data cache to RAM.
	426	* Note: this is necessary because the instruction cache does not
	427	* snoop from the data cache.
	428	* This is a no-op on the 601 which has a unified cache.
	429	*
	430	* void __flush_dcache_icache(void *page)
	431	*/
	432	_GLOBAL(__flush_dcache_icache)
	433	BEGIN_FTR_SECTION
4508dc21 DG	434	blr
4508dc21 DG	435	END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
ca9153a3 IY	436	rlwinm r3,r3,0,0,31-PAGE_SHIFT /* Get page base address */
ca9153a3 IY	437	li r4,PAGE_SIZE/L1_CACHE_BYTES /* Number of lines in a page */
9994a338 PM	438	mtctr r4
	439	mr r6,r3
	440	0: dcbst 0,r3 /* Write line to ram */
7dffb720	441	addi r3,r3,L1_CACHE_BYTES
9994a338 PM	442	bdnz 0b
9994a338 PM	443	sync
b98ac05d BH	444	#ifndef CONFIG_44x
	445	/* We don't flush the icache on 44x. Those have a virtual icache
	446	* and we don't have access to the virtual address here (it's
	447	* not the page vaddr but where it's mapped in user space). The
	448	* flushing of the icache on these is handled elsewhere, when
	449	* a change in the address space occurs, before returning to
	450	* user space
	451	*/
9994a338 PM	452	mtctr r4
9994a338 PM	453	1: icbi 0,r6
7dffb720	454	addi r6,r6,L1_CACHE_BYTES
9994a338 PM	455	bdnz 1b
	456	sync
	457	isync
b98ac05d	458	#endif /* CONFIG_44x */
9994a338 PM	459	blr
	460
	461	/*
	462	* Flush a particular page from the data cache to RAM, identified
	463	* by its physical address. We turn off the MMU so we can just use
	464	* the physical address (this may be a highmem page without a kernel
	465	* mapping).
	466	*
	467	* void __flush_dcache_icache_phys(unsigned long physaddr)
	468	*/
	469	_GLOBAL(__flush_dcache_icache_phys)
	470	BEGIN_FTR_SECTION
	471	blr /* for 601, do nothing */
4508dc21	472	END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
9994a338 PM	473	mfmsr r10
	474	rlwinm r0,r10,0,28,26 /* clear DR */
	475	mtmsr r0
	476	isync
ca9153a3 IY	477	rlwinm r3,r3,0,0,31-PAGE_SHIFT /* Get page base address */
ca9153a3 IY	478	li r4,PAGE_SIZE/L1_CACHE_BYTES /* Number of lines in a page */
9994a338 PM	479	mtctr r4
	480	mr r6,r3
	481	0: dcbst 0,r3 /* Write line to ram */
7dffb720	482	addi r3,r3,L1_CACHE_BYTES
9994a338 PM	483	bdnz 0b
	484	sync
	485	mtctr r4
	486	1: icbi 0,r6
7dffb720	487	addi r6,r6,L1_CACHE_BYTES
9994a338 PM	488	bdnz 1b
	489	sync
	490	mtmsr r10 /* restore DR */
	491	isync
	492	blr
	493
	494	/*
	495	* Clear pages using the dcbz instruction, which doesn't cause any
	496	* memory traffic (except to write out any cache lines which get
	497	* displaced). This only works on cacheable memory.
	498	*
	499	* void clear_pages(void *page, int order) ;
	500	*/
	501	_GLOBAL(clear_pages)
ca9153a3	502	li r0,PAGE_SIZE/L1_CACHE_BYTES
9994a338 PM	503	slw r0,r0,r4
9994a338 PM	504	mtctr r0
9994a338	505	1: dcbz 0,r3
7dffb720	506	addi r3,r3,L1_CACHE_BYTES
9994a338 PM	507	bdnz 1b
	508	blr
	509
	510	/*
	511	* Copy a whole page. We use the dcbz instruction on the destination
	512	* to reduce memory traffic (it eliminates the unnecessary reads of
	513	* the destination into cache). This requires that the destination
	514	* is cacheable.
	515	*/
	516	#define COPY_16_BYTES \
	517	lwz r6,4(r4); \
	518	lwz r7,8(r4); \
	519	lwz r8,12(r4); \
	520	lwzu r9,16(r4); \
	521	stw r6,4(r3); \
	522	stw r7,8(r3); \
	523	stw r8,12(r3); \
	524	stwu r9,16(r3)
	525
	526	_GLOBAL(copy_page)
	527	addi r3,r3,-4
	528	addi r4,r4,-4
	529
9994a338 PM	530	li r5,4
	531
	532	#if MAX_COPY_PREFETCH > 1
	533	li r0,MAX_COPY_PREFETCH
	534	li r11,4
	535	mtctr r0
	536	11: dcbt r11,r4
7dffb720	537	addi r11,r11,L1_CACHE_BYTES
9994a338 PM	538	bdnz 11b
	539	#else /* MAX_COPY_PREFETCH == 1 */
	540	dcbt r5,r4
7dffb720	541	li r11,L1_CACHE_BYTES+4
9994a338	542	#endif /* MAX_COPY_PREFETCH */
ca9153a3	543	li r0,PAGE_SIZE/L1_CACHE_BYTES - MAX_COPY_PREFETCH
9994a338 PM	544	crclr 4*cr0+eq
	545	2:
	546	mtctr r0
	547	1:
	548	dcbt r11,r4
	549	dcbz r5,r3
	550	COPY_16_BYTES
7dffb720	551	#if L1_CACHE_BYTES >= 32
9994a338	552	COPY_16_BYTES
7dffb720	553	#if L1_CACHE_BYTES >= 64
9994a338 PM	554	COPY_16_BYTES
9994a338 PM	555	COPY_16_BYTES
7dffb720	556	#if L1_CACHE_BYTES >= 128
9994a338 PM	557	COPY_16_BYTES
	558	COPY_16_BYTES
	559	COPY_16_BYTES
	560	COPY_16_BYTES
	561	#endif
	562	#endif
	563	#endif
	564	bdnz 1b
	565	beqlr
	566	crnot 4cr0+eq,4cr0+eq
	567	li r0,MAX_COPY_PREFETCH
	568	li r11,4
	569	b 2b
9994a338 PM	570
	571	/*
	572	* void atomic_clear_mask(atomic_t mask, atomic_t *addr)
	573	* void atomic_set_mask(atomic_t mask, atomic_t *addr);
	574	*/
	575	_GLOBAL(atomic_clear_mask)
	576	10: lwarx r5,0,r4
	577	andc r5,r5,r3
	578	PPC405_ERR77(0,r4)
	579	stwcx. r5,0,r4
	580	bne- 10b
	581	blr
	582	_GLOBAL(atomic_set_mask)
	583	10: lwarx r5,0,r4
	584	or r5,r5,r3
	585	PPC405_ERR77(0,r4)
	586	stwcx. r5,0,r4
	587	bne- 10b
	588	blr
	589
9994a338 PM	590	/*
	591	* Extended precision shifts.
	592	*
	593	* Updated to be valid for shift counts from 0 to 63 inclusive.
	594	* -- Gabriel
	595	*
	596	* R3/R4 has 64 bit value
	597	* R5 has shift count
	598	* result in R3/R4
	599	*
	600	* ashrdi3: arithmetic right shift (sign propagation)
	601	* lshrdi3: logical right shift
	602	* ashldi3: left shift
	603	*/
	604	_GLOBAL(__ashrdi3)
	605	subfic r6,r5,32
	606	srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
	607	addi r7,r5,32 # could be xori, or addi with -32
	608	slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
	609	rlwinm r8,r7,0,32 # t3 = (count < 32) ? 32 : 0
	610	sraw r7,r3,r7 # t2 = MSW >> (count-32)
	611	or r4,r4,r6 # LSW \|= t1
	612	slw r7,r7,r8 # t2 = (count < 32) ? 0 : t2
	613	sraw r3,r3,r5 # MSW = MSW >> count
	614	or r4,r4,r7 # LSW \|= t2
	615	blr
	616
	617	_GLOBAL(__ashldi3)
	618	subfic r6,r5,32
	619	slw r3,r3,r5 # MSW = count > 31 ? 0 : MSW << count
	620	addi r7,r5,32 # could be xori, or addi with -32
	621	srw r6,r4,r6 # t1 = count > 31 ? 0 : LSW >> (32-count)
	622	slw r7,r4,r7 # t2 = count < 32 ? 0 : LSW << (count-32)
	623	or r3,r3,r6 # MSW \|= t1
	624	slw r4,r4,r5 # LSW = LSW << count
	625	or r3,r3,r7 # MSW \|= t2
	626	blr
	627
	628	_GLOBAL(__lshrdi3)
	629	subfic r6,r5,32
	630	srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
	631	addi r7,r5,32 # could be xori, or addi with -32
	632	slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
	633	srw r7,r3,r7 # t2 = count < 32 ? 0 : MSW >> (count-32)
	634	or r4,r4,r6 # LSW \|= t1
	635	srw r3,r3,r5 # MSW = MSW >> count
	636	or r4,r4,r7 # LSW \|= t2
	637	blr
	638
95ff54f5 PM	639	/*
	640	* 64-bit comparison: __ucmpdi2(u64 a, u64 b)
	641	* Returns 0 if a < b, 1 if a == b, 2 if a > b.
	642	*/
	643	_GLOBAL(__ucmpdi2)
	644	cmplw r3,r5
	645	li r3,1
	646	bne 1f
	647	cmplw r4,r6
	648	beqlr
	649	1: li r3,0
	650	bltlr
	651	li r3,2
	652	blr
	653
9994a338 PM	654	_GLOBAL(abs)
	655	srawi r4,r3,31
	656	xor r3,r3,r4
	657	sub r3,r3,r4
	658	blr
	659
9994a338 PM	660	/*
	661	* Create a kernel thread
	662	* kernel_thread(fn, arg, flags)
	663	*/
	664	_GLOBAL(kernel_thread)
	665	stwu r1,-16(r1)
	666	stw r30,8(r1)
	667	stw r31,12(r1)
	668	mr r30,r3 /* function */
	669	mr r31,r4 /* argument */
	670	ori r3,r5,CLONE_VM /* flags */
	671	oris r3,r3,CLONE_UNTRACED>>16
	672	li r4,0 /* new sp (unused) */
	673	li r0,__NR_clone
	674	sc
41c2e949 JP	675	bns+ 1f /* did system call indicate error? */
	676	neg r3,r3 /* if so, make return code negative */
	677	1: cmpwi 0,r3,0 /* parent or child? */
	678	bne 2f /* return if parent */
9994a338 PM	679	li r0,0 /* make top-level stack frame */
	680	stwu r0,-16(r1)
	681	mtlr r30 /* fn addr in lr */
	682	mr r3,r31 /* load arg and call fn */
	683	PPC440EP_ERR42
	684	blrl
	685	li r0,__NR_exit /* exit if function returns */
	686	li r3,0
	687	sc
41c2e949	688	2: lwz r30,8(r1)
9994a338 PM	689	lwz r31,12(r1)
	690	addi r1,r1,16
	691	blr
	692
9994a338 PM	693	/*
	694	* This routine is just here to keep GCC happy - sigh...
	695	*/
	696	_GLOBAL(__main)
	697	blr
3d1229d6 ME	698
	699	#ifdef CONFIG_KEXEC
	700	/*
	701	* Must be relocatable PIC code callable as a C function.
	702	*/
	703	.globl relocate_new_kernel
	704	relocate_new_kernel:
	705	/* r3 = page_list */
	706	/* r4 = reboot_code_buffer */
	707	/* r5 = start_address */
	708
	709	li r0, 0
	710
	711	/*
	712	* Set Machine Status Register to a known status,
	713	* switch the MMU off and jump to 1: in a single step.
	714	*/
	715
	716	mr r8, r0
	717	ori r8, r8, MSR_RI\|MSR_ME
	718	mtspr SPRN_SRR1, r8
	719	addi r8, r4, 1f - relocate_new_kernel
	720	mtspr SPRN_SRR0, r8
	721	sync
	722	rfi
	723
	724	1:
	725	/* from this point address translation is turned off */
	726	/* and interrupts are disabled */
	727
	728	/* set a new stack at the bottom of our page... */
	729	/* (not really needed now) */
d9178f4c	730	addi r1, r4, KEXEC_CONTROL_PAGE_SIZE - 8 /* for LR Save+Back Chain */
3d1229d6 ME	731	stw r0, 0(r1)
	732
	733	/* Do the copies */
	734	li r6, 0 /* checksum */
	735	mr r0, r3
	736	b 1f
	737
	738	0: /* top, read another word for the indirection page */
	739	lwzu r0, 4(r3)
	740
	741	1:
	742	/* is it a destination page? (r8) */
	743	rlwinm. r7, r0, 0, 31, 31 /* IND_DESTINATION (1<<0) */
	744	beq 2f
	745
	746	rlwinm r8, r0, 0, 0, 19 /* clear kexec flags, page align */
	747	b 0b
	748
	749	2: /* is it an indirection page? (r3) */
	750	rlwinm. r7, r0, 0, 30, 30 /* IND_INDIRECTION (1<<1) */
	751	beq 2f
	752
	753	rlwinm r3, r0, 0, 0, 19 /* clear kexec flags, page align */
	754	subi r3, r3, 4
	755	b 0b
	756
	757	2: /* are we done? */
	758	rlwinm. r7, r0, 0, 29, 29 /* IND_DONE (1<<2) */
	759	beq 2f
	760	b 3f
	761
	762	2: /* is it a source page? (r9) */
	763	rlwinm. r7, r0, 0, 28, 28 /* IND_SOURCE (1<<3) */
	764	beq 0b
	765
	766	rlwinm r9, r0, 0, 0, 19 /* clear kexec flags, page align */
	767
	768	li r7, PAGE_SIZE / 4
	769	mtctr r7
	770	subi r9, r9, 4
	771	subi r8, r8, 4
	772	9:
	773	lwzu r0, 4(r9) /* do the copy */
	774	xor r6, r6, r0
	775	stwu r0, 4(r8)
	776	dcbst 0, r8
	777	sync
	778	icbi 0, r8
	779	bdnz 9b
	780
	781	addi r9, r9, 4
	782	addi r8, r8, 4
	783	b 0b
	784
	785	3:
	786
	787	/* To be certain of avoiding problems with self-modifying code
	788	* execute a serializing instruction here.
	789	*/
	790	isync
	791	sync
	792
	793	/* jump to the entry point, usually the setup routine */
	794	mtlr r5
795	blrl
796
797	1: b 1b
798
799	relocate_new_kernel_end:
800
801	.globl relocate_new_kernel_size
802	relocate_new_kernel_size:
803	.long relocate_new_kernel_end - relocate_new_kernel
804	#endif