Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle | |
7 | * Copyright (C) 2000 Silicon Graphics, Inc. | |
8 | * Modified for further R[236]000 support by Paul M. Antoine, 1996. | |
9 | * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com | |
a3692020 | 10 | * Copyright (C) 2000, 07 MIPS Technologies, Inc. |
4194318c | 11 | * Copyright (C) 2003, 2004 Maciej W. Rozycki |
1da177e4 LT |
12 | */ |
13 | #ifndef _ASM_MIPSREGS_H | |
14 | #define _ASM_MIPSREGS_H | |
15 | ||
1da177e4 | 16 | #include <linux/linkage.h> |
87c99203 | 17 | #include <linux/types.h> |
1da177e4 | 18 | #include <asm/hazards.h> |
9267a30d | 19 | #include <asm/war.h> |
1da177e4 LT |
20 | |
21 | /* | |
22 | * The following macros are especially useful for __asm__ | |
23 | * inline assembler. | |
24 | */ | |
25 | #ifndef __STR | |
26 | #define __STR(x) #x | |
27 | #endif | |
28 | #ifndef STR | |
29 | #define STR(x) __STR(x) | |
30 | #endif | |
31 | ||
32 | /* | |
33 | * Configure language | |
34 | */ | |
35 | #ifdef __ASSEMBLY__ | |
36 | #define _ULCAST_ | |
f359a111 | 37 | #define _U64CAST_ |
1da177e4 LT |
38 | #else |
39 | #define _ULCAST_ (unsigned long) | |
f359a111 | 40 | #define _U64CAST_ (u64) |
1da177e4 LT |
41 | #endif |
42 | ||
43 | /* | |
44 | * Coprocessor 0 register names | |
45 | */ | |
46 | #define CP0_INDEX $0 | |
47 | #define CP0_RANDOM $1 | |
48 | #define CP0_ENTRYLO0 $2 | |
49 | #define CP0_ENTRYLO1 $3 | |
50 | #define CP0_CONF $3 | |
c6593dde | 51 | #define CP0_GLOBALNUMBER $3, 1 |
1da177e4 LT |
52 | #define CP0_CONTEXT $4 |
53 | #define CP0_PAGEMASK $5 | |
5c33f8b2 MR |
54 | #define CP0_SEGCTL0 $5, 2 |
55 | #define CP0_SEGCTL1 $5, 3 | |
56 | #define CP0_SEGCTL2 $5, 4 | |
1da177e4 LT |
57 | #define CP0_WIRED $6 |
58 | #define CP0_INFO $7 | |
aff565aa | 59 | #define CP0_HWRENA $7 |
1da177e4 | 60 | #define CP0_BADVADDR $8 |
609cf6f2 | 61 | #define CP0_BADINSTR $8, 1 |
1da177e4 LT |
62 | #define CP0_COUNT $9 |
63 | #define CP0_ENTRYHI $10 | |
f913e9ea JH |
64 | #define CP0_GUESTCTL1 $10, 4 |
65 | #define CP0_GUESTCTL2 $10, 5 | |
66 | #define CP0_GUESTCTL3 $10, 6 | |
1da177e4 | 67 | #define CP0_COMPARE $11 |
f913e9ea | 68 | #define CP0_GUESTCTL0EXT $11, 4 |
1da177e4 | 69 | #define CP0_STATUS $12 |
f913e9ea JH |
70 | #define CP0_GUESTCTL0 $12, 6 |
71 | #define CP0_GTOFFSET $12, 7 | |
1da177e4 LT |
72 | #define CP0_CAUSE $13 |
73 | #define CP0_EPC $14 | |
74 | #define CP0_PRID $15 | |
609cf6f2 PB |
75 | #define CP0_EBASE $15, 1 |
76 | #define CP0_CMGCRBASE $15, 3 | |
1da177e4 | 77 | #define CP0_CONFIG $16 |
195cee92 JH |
78 | #define CP0_CONFIG3 $16, 3 |
79 | #define CP0_CONFIG5 $16, 5 | |
1da177e4 LT |
80 | #define CP0_LLADDR $17 |
81 | #define CP0_WATCHLO $18 | |
82 | #define CP0_WATCHHI $19 | |
83 | #define CP0_XCONTEXT $20 | |
84 | #define CP0_FRAMEMASK $21 | |
85 | #define CP0_DIAGNOSTIC $22 | |
86 | #define CP0_DEBUG $23 | |
87 | #define CP0_DEPC $24 | |
88 | #define CP0_PERFORMANCE $25 | |
89 | #define CP0_ECC $26 | |
90 | #define CP0_CACHEERR $27 | |
91 | #define CP0_TAGLO $28 | |
92 | #define CP0_TAGHI $29 | |
93 | #define CP0_ERROREPC $30 | |
94 | #define CP0_DESAVE $31 | |
95 | ||
96 | /* | |
97 | * R4640/R4650 cp0 register names. These registers are listed | |
98 | * here only for completeness; without MMU these CPUs are not useable | |
99 | * by Linux. A future ELKS port might take make Linux run on them | |
100 | * though ... | |
101 | */ | |
102 | #define CP0_IBASE $0 | |
103 | #define CP0_IBOUND $1 | |
104 | #define CP0_DBASE $2 | |
105 | #define CP0_DBOUND $3 | |
106 | #define CP0_CALG $17 | |
107 | #define CP0_IWATCH $18 | |
108 | #define CP0_DWATCH $19 | |
109 | ||
110 | /* | |
111 | * Coprocessor 0 Set 1 register names | |
112 | */ | |
113 | #define CP0_S1_DERRADDR0 $26 | |
114 | #define CP0_S1_DERRADDR1 $27 | |
115 | #define CP0_S1_INTCONTROL $20 | |
116 | ||
7a0fc58c RB |
117 | /* |
118 | * Coprocessor 0 Set 2 register names | |
119 | */ | |
120 | #define CP0_S2_SRSCTL $12 /* MIPSR2 */ | |
121 | ||
122 | /* | |
123 | * Coprocessor 0 Set 3 register names | |
124 | */ | |
125 | #define CP0_S3_SRSMAP $12 /* MIPSR2 */ | |
126 | ||
1da177e4 LT |
127 | /* |
128 | * TX39 Series | |
129 | */ | |
130 | #define CP0_TX39_CACHE $7 | |
131 | ||
1da177e4 | 132 | |
bae637a2 JH |
133 | /* Generic EntryLo bit definitions */ |
134 | #define ENTRYLO_G (_ULCAST_(1) << 0) | |
135 | #define ENTRYLO_V (_ULCAST_(1) << 1) | |
136 | #define ENTRYLO_D (_ULCAST_(1) << 2) | |
137 | #define ENTRYLO_C_SHIFT 3 | |
138 | #define ENTRYLO_C (_ULCAST_(7) << ENTRYLO_C_SHIFT) | |
139 | ||
140 | /* R3000 EntryLo bit definitions */ | |
141 | #define R3K_ENTRYLO_G (_ULCAST_(1) << 8) | |
142 | #define R3K_ENTRYLO_V (_ULCAST_(1) << 9) | |
143 | #define R3K_ENTRYLO_D (_ULCAST_(1) << 10) | |
144 | #define R3K_ENTRYLO_N (_ULCAST_(1) << 11) | |
145 | ||
146 | /* MIPS32/64 EntryLo bit definitions */ | |
c6956728 PB |
147 | #define MIPS_ENTRYLO_PFN_SHIFT 6 |
148 | #define MIPS_ENTRYLO_XI (_ULCAST_(1) << (BITS_PER_LONG - 2)) | |
149 | #define MIPS_ENTRYLO_RI (_ULCAST_(1) << (BITS_PER_LONG - 1)) | |
bae637a2 | 150 | |
c6593dde PB |
151 | /* |
152 | * MIPSr6+ GlobalNumber register definitions | |
153 | */ | |
154 | #define MIPS_GLOBALNUMBER_VP_SHF 0 | |
155 | #define MIPS_GLOBALNUMBER_VP (_ULCAST_(0xff) << MIPS_GLOBALNUMBER_VP_SHF) | |
156 | #define MIPS_GLOBALNUMBER_CORE_SHF 8 | |
157 | #define MIPS_GLOBALNUMBER_CORE (_ULCAST_(0xff) << MIPS_GLOBALNUMBER_CORE_SHF) | |
158 | #define MIPS_GLOBALNUMBER_CLUSTER_SHF 16 | |
159 | #define MIPS_GLOBALNUMBER_CLUSTER (_ULCAST_(0xf) << MIPS_GLOBALNUMBER_CLUSTER_SHF) | |
160 | ||
1da177e4 LT |
161 | /* |
162 | * Values for PageMask register | |
163 | */ | |
164 | #ifdef CONFIG_CPU_VR41XX | |
165 | ||
166 | /* Why doesn't stupidity hurt ... */ | |
167 | ||
168 | #define PM_1K 0x00000000 | |
169 | #define PM_4K 0x00001800 | |
170 | #define PM_16K 0x00007800 | |
171 | #define PM_64K 0x0001f800 | |
172 | #define PM_256K 0x0007f800 | |
173 | ||
174 | #else | |
175 | ||
176 | #define PM_4K 0x00000000 | |
c52399be | 177 | #define PM_8K 0x00002000 |
1da177e4 | 178 | #define PM_16K 0x00006000 |
c52399be | 179 | #define PM_32K 0x0000e000 |
1da177e4 | 180 | #define PM_64K 0x0001e000 |
c52399be | 181 | #define PM_128K 0x0003e000 |
1da177e4 | 182 | #define PM_256K 0x0007e000 |
c52399be | 183 | #define PM_512K 0x000fe000 |
1da177e4 | 184 | #define PM_1M 0x001fe000 |
c52399be | 185 | #define PM_2M 0x003fe000 |
1da177e4 | 186 | #define PM_4M 0x007fe000 |
c52399be | 187 | #define PM_8M 0x00ffe000 |
1da177e4 | 188 | #define PM_16M 0x01ffe000 |
c52399be | 189 | #define PM_32M 0x03ffe000 |
1da177e4 LT |
190 | #define PM_64M 0x07ffe000 |
191 | #define PM_256M 0x1fffe000 | |
542c1020 | 192 | #define PM_1G 0x7fffe000 |
1da177e4 LT |
193 | |
194 | #endif | |
195 | ||
196 | /* | |
197 | * Default page size for a given kernel configuration | |
198 | */ | |
199 | #ifdef CONFIG_PAGE_SIZE_4KB | |
70342287 | 200 | #define PM_DEFAULT_MASK PM_4K |
c52399be | 201 | #elif defined(CONFIG_PAGE_SIZE_8KB) |
70342287 | 202 | #define PM_DEFAULT_MASK PM_8K |
1da177e4 | 203 | #elif defined(CONFIG_PAGE_SIZE_16KB) |
70342287 | 204 | #define PM_DEFAULT_MASK PM_16K |
c52399be | 205 | #elif defined(CONFIG_PAGE_SIZE_32KB) |
70342287 | 206 | #define PM_DEFAULT_MASK PM_32K |
1da177e4 | 207 | #elif defined(CONFIG_PAGE_SIZE_64KB) |
70342287 | 208 | #define PM_DEFAULT_MASK PM_64K |
1da177e4 LT |
209 | #else |
210 | #error Bad page size configuration! | |
211 | #endif | |
212 | ||
dd794392 DD |
213 | /* |
214 | * Default huge tlb size for a given kernel configuration | |
215 | */ | |
216 | #ifdef CONFIG_PAGE_SIZE_4KB | |
217 | #define PM_HUGE_MASK PM_1M | |
218 | #elif defined(CONFIG_PAGE_SIZE_8KB) | |
219 | #define PM_HUGE_MASK PM_4M | |
220 | #elif defined(CONFIG_PAGE_SIZE_16KB) | |
221 | #define PM_HUGE_MASK PM_16M | |
222 | #elif defined(CONFIG_PAGE_SIZE_32KB) | |
223 | #define PM_HUGE_MASK PM_64M | |
224 | #elif defined(CONFIG_PAGE_SIZE_64KB) | |
225 | #define PM_HUGE_MASK PM_256M | |
aa1762f4 | 226 | #elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT) |
dd794392 DD |
227 | #error Bad page size configuration for hugetlbfs! |
228 | #endif | |
1da177e4 | 229 | |
10313980 PB |
230 | /* |
231 | * Wired register bits | |
232 | */ | |
eb0bab38 JH |
233 | #define MIPSR6_WIRED_LIMIT_SHIFT 16 |
234 | #define MIPSR6_WIRED_LIMIT (_ULCAST_(0xffff) << MIPSR6_WIRED_LIMIT_SHIFT) | |
235 | #define MIPSR6_WIRED_WIRED_SHIFT 0 | |
236 | #define MIPSR6_WIRED_WIRED (_ULCAST_(0xffff) << MIPSR6_WIRED_WIRED_SHIFT) | |
10313980 | 237 | |
1da177e4 LT |
238 | /* |
239 | * Values used for computation of new tlb entries | |
240 | */ | |
241 | #define PL_4K 12 | |
242 | #define PL_16K 14 | |
243 | #define PL_64K 16 | |
244 | #define PL_256K 18 | |
245 | #define PL_1M 20 | |
246 | #define PL_4M 22 | |
247 | #define PL_16M 24 | |
248 | #define PL_64M 26 | |
249 | #define PL_256M 28 | |
250 | ||
9fe2e9d6 DD |
251 | /* |
252 | * PageGrain bits | |
253 | */ | |
70342287 RB |
254 | #define PG_RIE (_ULCAST_(1) << 31) |
255 | #define PG_XIE (_ULCAST_(1) << 30) | |
256 | #define PG_ELPA (_ULCAST_(1) << 29) | |
257 | #define PG_ESP (_ULCAST_(1) << 28) | |
6575b1d4 | 258 | #define PG_IEC (_ULCAST_(1) << 27) |
9fe2e9d6 | 259 | |
bae637a2 JH |
260 | /* MIPS32/64 EntryHI bit definitions */ |
261 | #define MIPS_ENTRYHI_EHINV (_ULCAST_(1) << 10) | |
9b5c3399 JH |
262 | #define MIPS_ENTRYHI_ASIDX (_ULCAST_(0x3) << 8) |
263 | #define MIPS_ENTRYHI_ASID (_ULCAST_(0xff) << 0) | |
bae637a2 | 264 | |
1da177e4 LT |
265 | /* |
266 | * R4x00 interrupt enable / cause bits | |
267 | */ | |
70342287 RB |
268 | #define IE_SW0 (_ULCAST_(1) << 8) |
269 | #define IE_SW1 (_ULCAST_(1) << 9) | |
270 | #define IE_IRQ0 (_ULCAST_(1) << 10) | |
271 | #define IE_IRQ1 (_ULCAST_(1) << 11) | |
272 | #define IE_IRQ2 (_ULCAST_(1) << 12) | |
273 | #define IE_IRQ3 (_ULCAST_(1) << 13) | |
274 | #define IE_IRQ4 (_ULCAST_(1) << 14) | |
275 | #define IE_IRQ5 (_ULCAST_(1) << 15) | |
1da177e4 LT |
276 | |
277 | /* | |
278 | * R4x00 interrupt cause bits | |
279 | */ | |
70342287 RB |
280 | #define C_SW0 (_ULCAST_(1) << 8) |
281 | #define C_SW1 (_ULCAST_(1) << 9) | |
282 | #define C_IRQ0 (_ULCAST_(1) << 10) | |
283 | #define C_IRQ1 (_ULCAST_(1) << 11) | |
284 | #define C_IRQ2 (_ULCAST_(1) << 12) | |
285 | #define C_IRQ3 (_ULCAST_(1) << 13) | |
286 | #define C_IRQ4 (_ULCAST_(1) << 14) | |
287 | #define C_IRQ5 (_ULCAST_(1) << 15) | |
1da177e4 LT |
288 | |
289 | /* | |
290 | * Bitfields in the R4xx0 cp0 status register | |
291 | */ | |
292 | #define ST0_IE 0x00000001 | |
293 | #define ST0_EXL 0x00000002 | |
294 | #define ST0_ERL 0x00000004 | |
295 | #define ST0_KSU 0x00000018 | |
296 | # define KSU_USER 0x00000010 | |
297 | # define KSU_SUPERVISOR 0x00000008 | |
298 | # define KSU_KERNEL 0x00000000 | |
299 | #define ST0_UX 0x00000020 | |
300 | #define ST0_SX 0x00000040 | |
70342287 | 301 | #define ST0_KX 0x00000080 |
1da177e4 LT |
302 | #define ST0_DE 0x00010000 |
303 | #define ST0_CE 0x00020000 | |
304 | ||
305 | /* | |
306 | * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate | |
307 | * cacheops in userspace. This bit exists only on RM7000 and RM9000 | |
308 | * processors. | |
309 | */ | |
310 | #define ST0_CO 0x08000000 | |
311 | ||
312 | /* | |
313 | * Bitfields in the R[23]000 cp0 status register. | |
314 | */ | |
70342287 | 315 | #define ST0_IEC 0x00000001 |
1da177e4 LT |
316 | #define ST0_KUC 0x00000002 |
317 | #define ST0_IEP 0x00000004 | |
318 | #define ST0_KUP 0x00000008 | |
319 | #define ST0_IEO 0x00000010 | |
320 | #define ST0_KUO 0x00000020 | |
321 | /* bits 6 & 7 are reserved on R[23]000 */ | |
322 | #define ST0_ISC 0x00010000 | |
323 | #define ST0_SWC 0x00020000 | |
324 | #define ST0_CM 0x00080000 | |
325 | ||
326 | /* | |
327 | * Bits specific to the R4640/R4650 | |
328 | */ | |
70342287 | 329 | #define ST0_UM (_ULCAST_(1) << 4) |
1da177e4 LT |
330 | #define ST0_IL (_ULCAST_(1) << 23) |
331 | #define ST0_DL (_ULCAST_(1) << 24) | |
332 | ||
e50c0a8f | 333 | /* |
3301edcb | 334 | * Enable the MIPS MDMX and DSP ASEs |
e50c0a8f RB |
335 | */ |
336 | #define ST0_MX 0x01000000 | |
337 | ||
1da177e4 LT |
338 | /* |
339 | * Status register bits available in all MIPS CPUs. | |
340 | */ | |
341 | #define ST0_IM 0x0000ff00 | |
70342287 RB |
342 | #define STATUSB_IP0 8 |
343 | #define STATUSF_IP0 (_ULCAST_(1) << 8) | |
344 | #define STATUSB_IP1 9 | |
345 | #define STATUSF_IP1 (_ULCAST_(1) << 9) | |
346 | #define STATUSB_IP2 10 | |
347 | #define STATUSF_IP2 (_ULCAST_(1) << 10) | |
348 | #define STATUSB_IP3 11 | |
349 | #define STATUSF_IP3 (_ULCAST_(1) << 11) | |
350 | #define STATUSB_IP4 12 | |
351 | #define STATUSF_IP4 (_ULCAST_(1) << 12) | |
352 | #define STATUSB_IP5 13 | |
353 | #define STATUSF_IP5 (_ULCAST_(1) << 13) | |
354 | #define STATUSB_IP6 14 | |
355 | #define STATUSF_IP6 (_ULCAST_(1) << 14) | |
356 | #define STATUSB_IP7 15 | |
357 | #define STATUSF_IP7 (_ULCAST_(1) << 15) | |
358 | #define STATUSB_IP8 0 | |
359 | #define STATUSF_IP8 (_ULCAST_(1) << 0) | |
360 | #define STATUSB_IP9 1 | |
361 | #define STATUSF_IP9 (_ULCAST_(1) << 1) | |
362 | #define STATUSB_IP10 2 | |
363 | #define STATUSF_IP10 (_ULCAST_(1) << 2) | |
364 | #define STATUSB_IP11 3 | |
365 | #define STATUSF_IP11 (_ULCAST_(1) << 3) | |
366 | #define STATUSB_IP12 4 | |
367 | #define STATUSF_IP12 (_ULCAST_(1) << 4) | |
368 | #define STATUSB_IP13 5 | |
369 | #define STATUSF_IP13 (_ULCAST_(1) << 5) | |
370 | #define STATUSB_IP14 6 | |
371 | #define STATUSF_IP14 (_ULCAST_(1) << 6) | |
372 | #define STATUSB_IP15 7 | |
373 | #define STATUSF_IP15 (_ULCAST_(1) << 7) | |
1da177e4 | 374 | #define ST0_CH 0x00040000 |
96ffa02d | 375 | #define ST0_NMI 0x00080000 |
1da177e4 LT |
376 | #define ST0_SR 0x00100000 |
377 | #define ST0_TS 0x00200000 | |
378 | #define ST0_BEV 0x00400000 | |
379 | #define ST0_RE 0x02000000 | |
380 | #define ST0_FR 0x04000000 | |
381 | #define ST0_CU 0xf0000000 | |
382 | #define ST0_CU0 0x10000000 | |
383 | #define ST0_CU1 0x20000000 | |
384 | #define ST0_CU2 0x40000000 | |
385 | #define ST0_CU3 0x80000000 | |
386 | #define ST0_XX 0x80000000 /* MIPS IV naming */ | |
387 | ||
010c108d DV |
388 | /* |
389 | * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2) | |
010c108d | 390 | */ |
9323f84f JH |
391 | #define INTCTLB_IPFDC 23 |
392 | #define INTCTLF_IPFDC (_ULCAST_(7) << INTCTLB_IPFDC) | |
010c108d DV |
393 | #define INTCTLB_IPPCI 26 |
394 | #define INTCTLF_IPPCI (_ULCAST_(7) << INTCTLB_IPPCI) | |
395 | #define INTCTLB_IPTI 29 | |
396 | #define INTCTLF_IPTI (_ULCAST_(7) << INTCTLB_IPTI) | |
397 | ||
1da177e4 LT |
398 | /* |
399 | * Bitfields and bit numbers in the coprocessor 0 cause register. | |
400 | * | |
401 | * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. | |
402 | */ | |
1054533a MR |
403 | #define CAUSEB_EXCCODE 2 |
404 | #define CAUSEF_EXCCODE (_ULCAST_(31) << 2) | |
405 | #define CAUSEB_IP 8 | |
406 | #define CAUSEF_IP (_ULCAST_(255) << 8) | |
70342287 RB |
407 | #define CAUSEB_IP0 8 |
408 | #define CAUSEF_IP0 (_ULCAST_(1) << 8) | |
409 | #define CAUSEB_IP1 9 | |
410 | #define CAUSEF_IP1 (_ULCAST_(1) << 9) | |
411 | #define CAUSEB_IP2 10 | |
412 | #define CAUSEF_IP2 (_ULCAST_(1) << 10) | |
413 | #define CAUSEB_IP3 11 | |
414 | #define CAUSEF_IP3 (_ULCAST_(1) << 11) | |
415 | #define CAUSEB_IP4 12 | |
416 | #define CAUSEF_IP4 (_ULCAST_(1) << 12) | |
417 | #define CAUSEB_IP5 13 | |
418 | #define CAUSEF_IP5 (_ULCAST_(1) << 13) | |
419 | #define CAUSEB_IP6 14 | |
420 | #define CAUSEF_IP6 (_ULCAST_(1) << 14) | |
421 | #define CAUSEB_IP7 15 | |
422 | #define CAUSEF_IP7 (_ULCAST_(1) << 15) | |
1054533a MR |
423 | #define CAUSEB_FDCI 21 |
424 | #define CAUSEF_FDCI (_ULCAST_(1) << 21) | |
e233c733 JH |
425 | #define CAUSEB_WP 22 |
426 | #define CAUSEF_WP (_ULCAST_(1) << 22) | |
1054533a MR |
427 | #define CAUSEB_IV 23 |
428 | #define CAUSEF_IV (_ULCAST_(1) << 23) | |
429 | #define CAUSEB_PCI 26 | |
430 | #define CAUSEF_PCI (_ULCAST_(1) << 26) | |
9fd4af63 JH |
431 | #define CAUSEB_DC 27 |
432 | #define CAUSEF_DC (_ULCAST_(1) << 27) | |
1054533a MR |
433 | #define CAUSEB_CE 28 |
434 | #define CAUSEF_CE (_ULCAST_(3) << 28) | |
435 | #define CAUSEB_TI 30 | |
436 | #define CAUSEF_TI (_ULCAST_(1) << 30) | |
437 | #define CAUSEB_BD 31 | |
438 | #define CAUSEF_BD (_ULCAST_(1) << 31) | |
1da177e4 | 439 | |
16d100db JH |
440 | /* |
441 | * Cause.ExcCode trap codes. | |
442 | */ | |
443 | #define EXCCODE_INT 0 /* Interrupt pending */ | |
444 | #define EXCCODE_MOD 1 /* TLB modified fault */ | |
445 | #define EXCCODE_TLBL 2 /* TLB miss on load or ifetch */ | |
446 | #define EXCCODE_TLBS 3 /* TLB miss on a store */ | |
447 | #define EXCCODE_ADEL 4 /* Address error on a load or ifetch */ | |
448 | #define EXCCODE_ADES 5 /* Address error on a store */ | |
449 | #define EXCCODE_IBE 6 /* Bus error on an ifetch */ | |
450 | #define EXCCODE_DBE 7 /* Bus error on a load or store */ | |
451 | #define EXCCODE_SYS 8 /* System call */ | |
452 | #define EXCCODE_BP 9 /* Breakpoint */ | |
453 | #define EXCCODE_RI 10 /* Reserved instruction exception */ | |
454 | #define EXCCODE_CPU 11 /* Coprocessor unusable */ | |
455 | #define EXCCODE_OV 12 /* Arithmetic overflow */ | |
456 | #define EXCCODE_TR 13 /* Trap instruction */ | |
16d100db JH |
457 | #define EXCCODE_MSAFPE 14 /* MSA floating point exception */ |
458 | #define EXCCODE_FPE 15 /* Floating point exception */ | |
044c9bb8 JH |
459 | #define EXCCODE_TLBRI 19 /* TLB Read-Inhibit exception */ |
460 | #define EXCCODE_TLBXI 20 /* TLB Execution-Inhibit exception */ | |
16d100db | 461 | #define EXCCODE_MSADIS 21 /* MSA disabled exception */ |
044c9bb8 | 462 | #define EXCCODE_MDMX 22 /* MDMX unusable exception */ |
16d100db | 463 | #define EXCCODE_WATCH 23 /* Watch address reference */ |
044c9bb8 JH |
464 | #define EXCCODE_MCHECK 24 /* Machine check */ |
465 | #define EXCCODE_THREAD 25 /* Thread exceptions (MT) */ | |
466 | #define EXCCODE_DSPDIS 26 /* DSP disabled exception */ | |
467 | #define EXCCODE_GE 27 /* Virtualized guest exception (VZ) */ | |
468 | ||
469 | /* Implementation specific trap codes used by MIPS cores */ | |
470 | #define MIPS_EXCCODE_TLBPAR 16 /* TLB parity error exception */ | |
16d100db | 471 | |
1da177e4 LT |
472 | /* |
473 | * Bits in the coprocessor 0 config register. | |
474 | */ | |
475 | /* Generic bits. */ | |
476 | #define CONF_CM_CACHABLE_NO_WA 0 | |
477 | #define CONF_CM_CACHABLE_WA 1 | |
478 | #define CONF_CM_UNCACHED 2 | |
479 | #define CONF_CM_CACHABLE_NONCOHERENT 3 | |
480 | #define CONF_CM_CACHABLE_CE 4 | |
481 | #define CONF_CM_CACHABLE_COW 5 | |
482 | #define CONF_CM_CACHABLE_CUW 6 | |
483 | #define CONF_CM_CACHABLE_ACCELERATED 7 | |
484 | #define CONF_CM_CMASK 7 | |
485 | #define CONF_BE (_ULCAST_(1) << 15) | |
486 | ||
487 | /* Bits common to various processors. */ | |
70342287 RB |
488 | #define CONF_CU (_ULCAST_(1) << 3) |
489 | #define CONF_DB (_ULCAST_(1) << 4) | |
490 | #define CONF_IB (_ULCAST_(1) << 5) | |
491 | #define CONF_DC (_ULCAST_(7) << 6) | |
492 | #define CONF_IC (_ULCAST_(7) << 9) | |
1da177e4 LT |
493 | #define CONF_EB (_ULCAST_(1) << 13) |
494 | #define CONF_EM (_ULCAST_(1) << 14) | |
495 | #define CONF_SM (_ULCAST_(1) << 16) | |
496 | #define CONF_SC (_ULCAST_(1) << 17) | |
497 | #define CONF_EW (_ULCAST_(3) << 18) | |
498 | #define CONF_EP (_ULCAST_(15)<< 24) | |
499 | #define CONF_EC (_ULCAST_(7) << 28) | |
500 | #define CONF_CM (_ULCAST_(1) << 31) | |
501 | ||
70342287 | 502 | /* Bits specific to the R4xx0. */ |
1da177e4 LT |
503 | #define R4K_CONF_SW (_ULCAST_(1) << 20) |
504 | #define R4K_CONF_SS (_ULCAST_(1) << 21) | |
e20368d5 | 505 | #define R4K_CONF_SB (_ULCAST_(3) << 22) |
1da177e4 | 506 | |
70342287 | 507 | /* Bits specific to the R5000. */ |
1da177e4 LT |
508 | #define R5K_CONF_SE (_ULCAST_(1) << 12) |
509 | #define R5K_CONF_SS (_ULCAST_(3) << 20) | |
510 | ||
70342287 RB |
511 | /* Bits specific to the RM7000. */ |
512 | #define RM7K_CONF_SE (_ULCAST_(1) << 3) | |
c6ad7b7d MR |
513 | #define RM7K_CONF_TE (_ULCAST_(1) << 12) |
514 | #define RM7K_CONF_CLK (_ULCAST_(1) << 16) | |
515 | #define RM7K_CONF_TC (_ULCAST_(1) << 17) | |
516 | #define RM7K_CONF_SI (_ULCAST_(3) << 20) | |
517 | #define RM7K_CONF_SC (_ULCAST_(1) << 31) | |
ba5187db | 518 | |
70342287 RB |
519 | /* Bits specific to the R10000. */ |
520 | #define R10K_CONF_DN (_ULCAST_(3) << 3) | |
521 | #define R10K_CONF_CT (_ULCAST_(1) << 5) | |
522 | #define R10K_CONF_PE (_ULCAST_(1) << 6) | |
523 | #define R10K_CONF_PM (_ULCAST_(3) << 7) | |
524 | #define R10K_CONF_EC (_ULCAST_(15)<< 9) | |
1da177e4 LT |
525 | #define R10K_CONF_SB (_ULCAST_(1) << 13) |
526 | #define R10K_CONF_SK (_ULCAST_(1) << 14) | |
527 | #define R10K_CONF_SS (_ULCAST_(7) << 16) | |
528 | #define R10K_CONF_SC (_ULCAST_(7) << 19) | |
529 | #define R10K_CONF_DC (_ULCAST_(7) << 26) | |
530 | #define R10K_CONF_IC (_ULCAST_(7) << 29) | |
531 | ||
70342287 | 532 | /* Bits specific to the VR41xx. */ |
1da177e4 | 533 | #define VR41_CONF_CS (_ULCAST_(1) << 12) |
2874fe55 | 534 | #define VR41_CONF_P4K (_ULCAST_(1) << 13) |
4e8ab361 | 535 | #define VR41_CONF_BP (_ULCAST_(1) << 16) |
1da177e4 LT |
536 | #define VR41_CONF_M16 (_ULCAST_(1) << 20) |
537 | #define VR41_CONF_AD (_ULCAST_(1) << 23) | |
538 | ||
70342287 | 539 | /* Bits specific to the R30xx. */ |
1da177e4 LT |
540 | #define R30XX_CONF_FDM (_ULCAST_(1) << 19) |
541 | #define R30XX_CONF_REV (_ULCAST_(1) << 22) | |
542 | #define R30XX_CONF_AC (_ULCAST_(1) << 23) | |
543 | #define R30XX_CONF_RF (_ULCAST_(1) << 24) | |
544 | #define R30XX_CONF_HALT (_ULCAST_(1) << 25) | |
545 | #define R30XX_CONF_FPINT (_ULCAST_(7) << 26) | |
546 | #define R30XX_CONF_DBR (_ULCAST_(1) << 29) | |
547 | #define R30XX_CONF_SB (_ULCAST_(1) << 30) | |
548 | #define R30XX_CONF_LOCK (_ULCAST_(1) << 31) | |
549 | ||
550 | /* Bits specific to the TX49. */ | |
551 | #define TX49_CONF_DC (_ULCAST_(1) << 16) | |
552 | #define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */ | |
553 | #define TX49_CONF_HALT (_ULCAST_(1) << 18) | |
554 | #define TX49_CONF_CWFON (_ULCAST_(1) << 27) | |
555 | ||
70342287 | 556 | /* Bits specific to the MIPS32/64 PRA. */ |
4b34bca0 | 557 | #define MIPS_CONF_VI (_ULCAST_(1) << 3) |
70342287 | 558 | #define MIPS_CONF_MT (_ULCAST_(7) << 7) |
2f6f3136 JH |
559 | #define MIPS_CONF_MT_TLB (_ULCAST_(1) << 7) |
560 | #define MIPS_CONF_MT_FTLB (_ULCAST_(4) << 7) | |
1da177e4 LT |
561 | #define MIPS_CONF_AR (_ULCAST_(7) << 10) |
562 | #define MIPS_CONF_AT (_ULCAST_(3) << 13) | |
563 | #define MIPS_CONF_M (_ULCAST_(1) << 31) | |
564 | ||
4194318c RB |
565 | /* |
566 | * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above. | |
567 | */ | |
70342287 RB |
568 | #define MIPS_CONF1_FP (_ULCAST_(1) << 0) |
569 | #define MIPS_CONF1_EP (_ULCAST_(1) << 1) | |
570 | #define MIPS_CONF1_CA (_ULCAST_(1) << 2) | |
571 | #define MIPS_CONF1_WR (_ULCAST_(1) << 3) | |
572 | #define MIPS_CONF1_PC (_ULCAST_(1) << 4) | |
573 | #define MIPS_CONF1_MD (_ULCAST_(1) << 5) | |
574 | #define MIPS_CONF1_C2 (_ULCAST_(1) << 6) | |
20a8d5d5 PB |
575 | #define MIPS_CONF1_DA_SHF 7 |
576 | #define MIPS_CONF1_DA_SZ 3 | |
70342287 | 577 | #define MIPS_CONF1_DA (_ULCAST_(7) << 7) |
20a8d5d5 PB |
578 | #define MIPS_CONF1_DL_SHF 10 |
579 | #define MIPS_CONF1_DL_SZ 3 | |
4194318c | 580 | #define MIPS_CONF1_DL (_ULCAST_(7) << 10) |
20a8d5d5 PB |
581 | #define MIPS_CONF1_DS_SHF 13 |
582 | #define MIPS_CONF1_DS_SZ 3 | |
4194318c | 583 | #define MIPS_CONF1_DS (_ULCAST_(7) << 13) |
20a8d5d5 PB |
584 | #define MIPS_CONF1_IA_SHF 16 |
585 | #define MIPS_CONF1_IA_SZ 3 | |
4194318c | 586 | #define MIPS_CONF1_IA (_ULCAST_(7) << 16) |
20a8d5d5 PB |
587 | #define MIPS_CONF1_IL_SHF 19 |
588 | #define MIPS_CONF1_IL_SZ 3 | |
4194318c | 589 | #define MIPS_CONF1_IL (_ULCAST_(7) << 19) |
20a8d5d5 PB |
590 | #define MIPS_CONF1_IS_SHF 22 |
591 | #define MIPS_CONF1_IS_SZ 3 | |
4194318c | 592 | #define MIPS_CONF1_IS (_ULCAST_(7) << 22) |
691038ba LY |
593 | #define MIPS_CONF1_TLBS_SHIFT (25) |
594 | #define MIPS_CONF1_TLBS_SIZE (6) | |
595 | #define MIPS_CONF1_TLBS (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT) | |
4194318c | 596 | |
70342287 RB |
597 | #define MIPS_CONF2_SA (_ULCAST_(15)<< 0) |
598 | #define MIPS_CONF2_SL (_ULCAST_(15)<< 4) | |
599 | #define MIPS_CONF2_SS (_ULCAST_(15)<< 8) | |
4194318c RB |
600 | #define MIPS_CONF2_SU (_ULCAST_(15)<< 12) |
601 | #define MIPS_CONF2_TA (_ULCAST_(15)<< 16) | |
602 | #define MIPS_CONF2_TL (_ULCAST_(15)<< 20) | |
603 | #define MIPS_CONF2_TS (_ULCAST_(15)<< 24) | |
604 | #define MIPS_CONF2_TU (_ULCAST_(7) << 28) | |
605 | ||
70342287 RB |
606 | #define MIPS_CONF3_TL (_ULCAST_(1) << 0) |
607 | #define MIPS_CONF3_SM (_ULCAST_(1) << 1) | |
608 | #define MIPS_CONF3_MT (_ULCAST_(1) << 2) | |
691038ba | 609 | #define MIPS_CONF3_CDMM (_ULCAST_(1) << 3) |
70342287 RB |
610 | #define MIPS_CONF3_SP (_ULCAST_(1) << 4) |
611 | #define MIPS_CONF3_VINT (_ULCAST_(1) << 5) | |
612 | #define MIPS_CONF3_VEIC (_ULCAST_(1) << 6) | |
613 | #define MIPS_CONF3_LPA (_ULCAST_(1) << 7) | |
691038ba LY |
614 | #define MIPS_CONF3_ITL (_ULCAST_(1) << 8) |
615 | #define MIPS_CONF3_CTXTC (_ULCAST_(1) << 9) | |
e50c0a8f | 616 | #define MIPS_CONF3_DSP (_ULCAST_(1) << 10) |
ee80f7c7 | 617 | #define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11) |
b2ab4f08 | 618 | #define MIPS_CONF3_RXI (_ULCAST_(1) << 12) |
a3692020 | 619 | #define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) |
f8fa4811 | 620 | #define MIPS_CONF3_ISA (_ULCAST_(3) << 14) |
c6213c6c | 621 | #define MIPS_CONF3_ISA_OE (_ULCAST_(1) << 16) |
691038ba LY |
622 | #define MIPS_CONF3_MCU (_ULCAST_(1) << 17) |
623 | #define MIPS_CONF3_MMAR (_ULCAST_(7) << 18) | |
624 | #define MIPS_CONF3_IPLW (_ULCAST_(3) << 21) | |
1e7decdb | 625 | #define MIPS_CONF3_VZ (_ULCAST_(1) << 23) |
691038ba LY |
626 | #define MIPS_CONF3_PW (_ULCAST_(1) << 24) |
627 | #define MIPS_CONF3_SC (_ULCAST_(1) << 25) | |
628 | #define MIPS_CONF3_BI (_ULCAST_(1) << 26) | |
629 | #define MIPS_CONF3_BP (_ULCAST_(1) << 27) | |
630 | #define MIPS_CONF3_MSA (_ULCAST_(1) << 28) | |
631 | #define MIPS_CONF3_CMGCR (_ULCAST_(1) << 29) | |
632 | #define MIPS_CONF3_BPG (_ULCAST_(1) << 30) | |
633 | ||
634 | #define MIPS_CONF4_MMUSIZEEXT_SHIFT (0) | |
1b362e3e | 635 | #define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0) |
691038ba | 636 | #define MIPS_CONF4_FTLBSETS_SHIFT (0) |
691038ba LY |
637 | #define MIPS_CONF4_FTLBSETS (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT) |
638 | #define MIPS_CONF4_FTLBWAYS_SHIFT (4) | |
639 | #define MIPS_CONF4_FTLBWAYS (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT) | |
640 | #define MIPS_CONF4_FTLBPAGESIZE_SHIFT (8) | |
641 | /* bits 10:8 in FTLB-only configurations */ | |
642 | #define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT) | |
643 | /* bits 12:8 in VTLB-FTLB only configurations */ | |
644 | #define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT) | |
1b362e3e DD |
645 | #define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14) |
646 | #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14) | |
691038ba LY |
647 | #define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT (_ULCAST_(2) << 14) |
648 | #define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT (_ULCAST_(3) << 14) | |
9e575f75 JH |
649 | #define MIPS_CONF4_KSCREXIST_SHIFT (16) |
650 | #define MIPS_CONF4_KSCREXIST (_ULCAST_(255) << MIPS_CONF4_KSCREXIST_SHIFT) | |
691038ba LY |
651 | #define MIPS_CONF4_VTLBSIZEEXT_SHIFT (24) |
652 | #define MIPS_CONF4_VTLBSIZEEXT (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT) | |
653 | #define MIPS_CONF4_AE (_ULCAST_(1) << 28) | |
654 | #define MIPS_CONF4_IE (_ULCAST_(3) << 29) | |
655 | #define MIPS_CONF4_TLBINV (_ULCAST_(2) << 29) | |
1b362e3e | 656 | |
2f9ee82c RB |
657 | #define MIPS_CONF5_NF (_ULCAST_(1) << 0) |
658 | #define MIPS_CONF5_UFR (_ULCAST_(1) << 2) | |
e19d5dba | 659 | #define MIPS_CONF5_MRP (_ULCAST_(1) << 3) |
5aed9da1 | 660 | #define MIPS_CONF5_LLB (_ULCAST_(1) << 4) |
23d06e4f | 661 | #define MIPS_CONF5_MVH (_ULCAST_(1) << 5) |
f270d881 | 662 | #define MIPS_CONF5_VP (_ULCAST_(1) << 7) |
eb0bab38 | 663 | #define MIPS_CONF5_SBRI (_ULCAST_(1) << 6) |
5ff04a84 PB |
664 | #define MIPS_CONF5_FRE (_ULCAST_(1) << 8) |
665 | #define MIPS_CONF5_UFE (_ULCAST_(1) << 9) | |
8d1630f1 | 666 | #define MIPS_CONF5_CA2 (_ULCAST_(1) << 14) |
256211f2 | 667 | #define MIPS_CONF5_CRCP (_ULCAST_(1) << 18) |
2f9ee82c RB |
668 | #define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27) |
669 | #define MIPS_CONF5_EVA (_ULCAST_(1) << 28) | |
670 | #define MIPS_CONF5_CV (_ULCAST_(1) << 29) | |
671 | #define MIPS_CONF5_K (_ULCAST_(1) << 30) | |
672 | ||
006a851b | 673 | #define MIPS_CONF6_SYND (_ULCAST_(1) << 13) |
75b5b5e0 LY |
674 | /* proAptiv FTLB on/off bit */ |
675 | #define MIPS_CONF6_FTLBEN (_ULCAST_(1) << 15) | |
b2edcfc8 HC |
676 | /* Loongson-3 FTLB on/off bit */ |
677 | #define MIPS_CONF6_FTLBDIS (_ULCAST_(1) << 22) | |
cf0a8aa0 MC |
678 | /* FTLB probability bits */ |
679 | #define MIPS_CONF6_FTLBP_SHIFT (16) | |
006a851b | 680 | |
4b3e975e RB |
681 | #define MIPS_CONF7_WII (_ULCAST_(1) << 31) |
682 | ||
9267a30d MSJ |
683 | #define MIPS_CONF7_RPS (_ULCAST_(1) << 2) |
684 | ||
02dc6bfb MC |
685 | #define MIPS_CONF7_IAR (_ULCAST_(1) << 10) |
686 | #define MIPS_CONF7_AR (_ULCAST_(1) << 16) | |
687 | ||
8270ab48 MR |
688 | /* Config7 Bits specific to MIPS Technologies. */ |
689 | ||
690 | /* Performance counters implemented Per TC */ | |
691 | #define MTI_CONF7_PTC (_ULCAST_(1) << 19) | |
692 | ||
50af501c JH |
693 | /* WatchLo* register definitions */ |
694 | #define MIPS_WATCHLO_IRW (_ULCAST_(0x7) << 0) | |
695 | ||
696 | /* WatchHi* register definitions */ | |
697 | #define MIPS_WATCHHI_M (_ULCAST_(1) << 31) | |
698 | #define MIPS_WATCHHI_G (_ULCAST_(1) << 30) | |
699 | #define MIPS_WATCHHI_WM (_ULCAST_(0x3) << 28) | |
700 | #define MIPS_WATCHHI_WM_R_RVA (_ULCAST_(0) << 28) | |
701 | #define MIPS_WATCHHI_WM_R_GPA (_ULCAST_(1) << 28) | |
702 | #define MIPS_WATCHHI_WM_G_GVA (_ULCAST_(2) << 28) | |
703 | #define MIPS_WATCHHI_EAS (_ULCAST_(0x3) << 24) | |
704 | #define MIPS_WATCHHI_ASID (_ULCAST_(0xff) << 16) | |
705 | #define MIPS_WATCHHI_MASK (_ULCAST_(0x1ff) << 3) | |
706 | #define MIPS_WATCHHI_I (_ULCAST_(1) << 2) | |
707 | #define MIPS_WATCHHI_R (_ULCAST_(1) << 1) | |
708 | #define MIPS_WATCHHI_W (_ULCAST_(1) << 0) | |
709 | #define MIPS_WATCHHI_IRW (_ULCAST_(0x7) << 0) | |
710 | ||
2654294b JH |
711 | /* PerfCnt control register definitions */ |
712 | #define MIPS_PERFCTRL_EXL (_ULCAST_(1) << 0) | |
713 | #define MIPS_PERFCTRL_K (_ULCAST_(1) << 1) | |
714 | #define MIPS_PERFCTRL_S (_ULCAST_(1) << 2) | |
715 | #define MIPS_PERFCTRL_U (_ULCAST_(1) << 3) | |
716 | #define MIPS_PERFCTRL_IE (_ULCAST_(1) << 4) | |
717 | #define MIPS_PERFCTRL_EVENT_S 5 | |
718 | #define MIPS_PERFCTRL_EVENT (_ULCAST_(0x3ff) << MIPS_PERFCTRL_EVENT_S) | |
719 | #define MIPS_PERFCTRL_PCTD (_ULCAST_(1) << 15) | |
720 | #define MIPS_PERFCTRL_EC (_ULCAST_(0x3) << 23) | |
721 | #define MIPS_PERFCTRL_EC_R (_ULCAST_(0) << 23) | |
722 | #define MIPS_PERFCTRL_EC_RI (_ULCAST_(1) << 23) | |
723 | #define MIPS_PERFCTRL_EC_G (_ULCAST_(2) << 23) | |
724 | #define MIPS_PERFCTRL_EC_GRI (_ULCAST_(3) << 23) | |
725 | #define MIPS_PERFCTRL_W (_ULCAST_(1) << 30) | |
726 | #define MIPS_PERFCTRL_M (_ULCAST_(1) << 31) | |
727 | ||
728 | /* PerfCnt control register MT extensions used by MIPS cores */ | |
729 | #define MIPS_PERFCTRL_VPEID_S 16 | |
730 | #define MIPS_PERFCTRL_VPEID (_ULCAST_(0xf) << MIPS_PERFCTRL_VPEID_S) | |
731 | #define MIPS_PERFCTRL_TCID_S 22 | |
732 | #define MIPS_PERFCTRL_TCID (_ULCAST_(0xff) << MIPS_PERFCTRL_TCID_S) | |
733 | #define MIPS_PERFCTRL_MT_EN (_ULCAST_(0x3) << 20) | |
734 | #define MIPS_PERFCTRL_MT_EN_ALL (_ULCAST_(0) << 20) | |
735 | #define MIPS_PERFCTRL_MT_EN_VPE (_ULCAST_(1) << 20) | |
736 | #define MIPS_PERFCTRL_MT_EN_TC (_ULCAST_(2) << 20) | |
737 | ||
738 | /* PerfCnt control register MT extensions used by BMIPS5000 */ | |
739 | #define BRCM_PERFCTRL_TC (_ULCAST_(1) << 30) | |
740 | ||
741 | /* PerfCnt control register MT extensions used by Netlogic XLR */ | |
742 | #define XLR_PERFCTRL_ALLTHREADS (_ULCAST_(1) << 13) | |
743 | ||
e19d5dba | 744 | /* MAAR bit definitions */ |
f359a111 | 745 | #define MIPS_MAAR_VH (_U64CAST_(1) << 63) |
e19d5dba PB |
746 | #define MIPS_MAAR_ADDR ((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12) |
747 | #define MIPS_MAAR_ADDR_SHIFT 12 | |
748 | #define MIPS_MAAR_S (_ULCAST_(1) << 1) | |
f359a111 JH |
749 | #define MIPS_MAAR_VL (_ULCAST_(1) << 0) |
750 | ||
751 | /* MAARI bit definitions */ | |
752 | #define MIPS_MAARI_INDEX (_ULCAST_(0x3f) << 0) | |
e19d5dba | 753 | |
37af2f30 JH |
754 | /* EBase bit definitions */ |
755 | #define MIPS_EBASE_CPUNUM_SHIFT 0 | |
756 | #define MIPS_EBASE_CPUNUM (_ULCAST_(0x3ff) << 0) | |
757 | #define MIPS_EBASE_WG_SHIFT 11 | |
758 | #define MIPS_EBASE_WG (_ULCAST_(1) << 11) | |
759 | #define MIPS_EBASE_BASE_SHIFT 12 | |
760 | #define MIPS_EBASE_BASE (~_ULCAST_((1 << MIPS_EBASE_BASE_SHIFT) - 1)) | |
761 | ||
4dd8ee5d PB |
762 | /* CMGCRBase bit definitions */ |
763 | #define MIPS_CMGCRB_BASE 11 | |
764 | #define MIPS_CMGCRF_BASE (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1)) | |
765 | ||
eb0bab38 JH |
766 | /* LLAddr bit definitions */ |
767 | #define MIPS_LLADDR_LLB_SHIFT 0 | |
768 | #define MIPS_LLADDR_LLB (_ULCAST_(1) << MIPS_LLADDR_LLB_SHIFT) | |
769 | ||
4a0156fb SH |
770 | /* |
771 | * Bits in the MIPS32 Memory Segmentation registers. | |
772 | */ | |
773 | #define MIPS_SEGCFG_PA_SHIFT 9 | |
774 | #define MIPS_SEGCFG_PA (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT) | |
775 | #define MIPS_SEGCFG_AM_SHIFT 4 | |
776 | #define MIPS_SEGCFG_AM (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT) | |
777 | #define MIPS_SEGCFG_EU_SHIFT 3 | |
778 | #define MIPS_SEGCFG_EU (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT) | |
779 | #define MIPS_SEGCFG_C_SHIFT 0 | |
780 | #define MIPS_SEGCFG_C (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT) | |
781 | ||
782 | #define MIPS_SEGCFG_UUSK _ULCAST_(7) | |
783 | #define MIPS_SEGCFG_USK _ULCAST_(5) | |
784 | #define MIPS_SEGCFG_MUSUK _ULCAST_(4) | |
785 | #define MIPS_SEGCFG_MUSK _ULCAST_(3) | |
786 | #define MIPS_SEGCFG_MSK _ULCAST_(2) | |
787 | #define MIPS_SEGCFG_MK _ULCAST_(1) | |
788 | #define MIPS_SEGCFG_UK _ULCAST_(0) | |
789 | ||
87d08bc9 MC |
790 | #define MIPS_PWFIELD_GDI_SHIFT 24 |
791 | #define MIPS_PWFIELD_GDI_MASK 0x3f000000 | |
792 | #define MIPS_PWFIELD_UDI_SHIFT 18 | |
793 | #define MIPS_PWFIELD_UDI_MASK 0x00fc0000 | |
794 | #define MIPS_PWFIELD_MDI_SHIFT 12 | |
795 | #define MIPS_PWFIELD_MDI_MASK 0x0003f000 | |
796 | #define MIPS_PWFIELD_PTI_SHIFT 6 | |
797 | #define MIPS_PWFIELD_PTI_MASK 0x00000fc0 | |
798 | #define MIPS_PWFIELD_PTEI_SHIFT 0 | |
799 | #define MIPS_PWFIELD_PTEI_MASK 0x0000003f | |
800 | ||
6446e6cf JH |
801 | #define MIPS_PWSIZE_PS_SHIFT 30 |
802 | #define MIPS_PWSIZE_PS_MASK 0x40000000 | |
87d08bc9 MC |
803 | #define MIPS_PWSIZE_GDW_SHIFT 24 |
804 | #define MIPS_PWSIZE_GDW_MASK 0x3f000000 | |
805 | #define MIPS_PWSIZE_UDW_SHIFT 18 | |
806 | #define MIPS_PWSIZE_UDW_MASK 0x00fc0000 | |
807 | #define MIPS_PWSIZE_MDW_SHIFT 12 | |
808 | #define MIPS_PWSIZE_MDW_MASK 0x0003f000 | |
809 | #define MIPS_PWSIZE_PTW_SHIFT 6 | |
810 | #define MIPS_PWSIZE_PTW_MASK 0x00000fc0 | |
811 | #define MIPS_PWSIZE_PTEW_SHIFT 0 | |
812 | #define MIPS_PWSIZE_PTEW_MASK 0x0000003f | |
813 | ||
814 | #define MIPS_PWCTL_PWEN_SHIFT 31 | |
815 | #define MIPS_PWCTL_PWEN_MASK 0x80000000 | |
6446e6cf JH |
816 | #define MIPS_PWCTL_XK_SHIFT 28 |
817 | #define MIPS_PWCTL_XK_MASK 0x10000000 | |
818 | #define MIPS_PWCTL_XS_SHIFT 27 | |
819 | #define MIPS_PWCTL_XS_MASK 0x08000000 | |
820 | #define MIPS_PWCTL_XU_SHIFT 26 | |
821 | #define MIPS_PWCTL_XU_MASK 0x04000000 | |
87d08bc9 MC |
822 | #define MIPS_PWCTL_DPH_SHIFT 7 |
823 | #define MIPS_PWCTL_DPH_MASK 0x00000080 | |
824 | #define MIPS_PWCTL_HUGEPG_SHIFT 6 | |
825 | #define MIPS_PWCTL_HUGEPG_MASK 0x00000060 | |
826 | #define MIPS_PWCTL_PSN_SHIFT 0 | |
827 | #define MIPS_PWCTL_PSN_MASK 0x0000003f | |
828 | ||
f913e9ea JH |
829 | /* GuestCtl0 fields */ |
830 | #define MIPS_GCTL0_GM_SHIFT 31 | |
831 | #define MIPS_GCTL0_GM (_ULCAST_(1) << MIPS_GCTL0_GM_SHIFT) | |
832 | #define MIPS_GCTL0_RI_SHIFT 30 | |
833 | #define MIPS_GCTL0_RI (_ULCAST_(1) << MIPS_GCTL0_RI_SHIFT) | |
834 | #define MIPS_GCTL0_MC_SHIFT 29 | |
835 | #define MIPS_GCTL0_MC (_ULCAST_(1) << MIPS_GCTL0_MC_SHIFT) | |
836 | #define MIPS_GCTL0_CP0_SHIFT 28 | |
837 | #define MIPS_GCTL0_CP0 (_ULCAST_(1) << MIPS_GCTL0_CP0_SHIFT) | |
838 | #define MIPS_GCTL0_AT_SHIFT 26 | |
839 | #define MIPS_GCTL0_AT (_ULCAST_(0x3) << MIPS_GCTL0_AT_SHIFT) | |
840 | #define MIPS_GCTL0_GT_SHIFT 25 | |
841 | #define MIPS_GCTL0_GT (_ULCAST_(1) << MIPS_GCTL0_GT_SHIFT) | |
842 | #define MIPS_GCTL0_CG_SHIFT 24 | |
843 | #define MIPS_GCTL0_CG (_ULCAST_(1) << MIPS_GCTL0_CG_SHIFT) | |
844 | #define MIPS_GCTL0_CF_SHIFT 23 | |
845 | #define MIPS_GCTL0_CF (_ULCAST_(1) << MIPS_GCTL0_CF_SHIFT) | |
846 | #define MIPS_GCTL0_G1_SHIFT 22 | |
847 | #define MIPS_GCTL0_G1 (_ULCAST_(1) << MIPS_GCTL0_G1_SHIFT) | |
848 | #define MIPS_GCTL0_G0E_SHIFT 19 | |
849 | #define MIPS_GCTL0_G0E (_ULCAST_(1) << MIPS_GCTL0_G0E_SHIFT) | |
850 | #define MIPS_GCTL0_PT_SHIFT 18 | |
851 | #define MIPS_GCTL0_PT (_ULCAST_(1) << MIPS_GCTL0_PT_SHIFT) | |
852 | #define MIPS_GCTL0_RAD_SHIFT 9 | |
853 | #define MIPS_GCTL0_RAD (_ULCAST_(1) << MIPS_GCTL0_RAD_SHIFT) | |
854 | #define MIPS_GCTL0_DRG_SHIFT 8 | |
855 | #define MIPS_GCTL0_DRG (_ULCAST_(1) << MIPS_GCTL0_DRG_SHIFT) | |
856 | #define MIPS_GCTL0_G2_SHIFT 7 | |
857 | #define MIPS_GCTL0_G2 (_ULCAST_(1) << MIPS_GCTL0_G2_SHIFT) | |
858 | #define MIPS_GCTL0_GEXC_SHIFT 2 | |
859 | #define MIPS_GCTL0_GEXC (_ULCAST_(0x1f) << MIPS_GCTL0_GEXC_SHIFT) | |
860 | #define MIPS_GCTL0_SFC2_SHIFT 1 | |
861 | #define MIPS_GCTL0_SFC2 (_ULCAST_(1) << MIPS_GCTL0_SFC2_SHIFT) | |
862 | #define MIPS_GCTL0_SFC1_SHIFT 0 | |
863 | #define MIPS_GCTL0_SFC1 (_ULCAST_(1) << MIPS_GCTL0_SFC1_SHIFT) | |
864 | ||
865 | /* GuestCtl0.AT Guest address translation control */ | |
866 | #define MIPS_GCTL0_AT_ROOT 1 /* Guest MMU under Root control */ | |
867 | #define MIPS_GCTL0_AT_GUEST 3 /* Guest MMU under Guest control */ | |
868 | ||
869 | /* GuestCtl0.GExcCode Hypervisor exception cause codes */ | |
870 | #define MIPS_GCTL0_GEXC_GPSI 0 /* Guest Privileged Sensitive Instruction */ | |
871 | #define MIPS_GCTL0_GEXC_GSFC 1 /* Guest Software Field Change */ | |
872 | #define MIPS_GCTL0_GEXC_HC 2 /* Hypercall */ | |
873 | #define MIPS_GCTL0_GEXC_GRR 3 /* Guest Reserved Instruction Redirect */ | |
874 | #define MIPS_GCTL0_GEXC_GVA 8 /* Guest Virtual Address available */ | |
875 | #define MIPS_GCTL0_GEXC_GHFC 9 /* Guest Hardware Field Change */ | |
876 | #define MIPS_GCTL0_GEXC_GPA 10 /* Guest Physical Address available */ | |
877 | ||
878 | /* GuestCtl0Ext fields */ | |
879 | #define MIPS_GCTL0EXT_RPW_SHIFT 8 | |
880 | #define MIPS_GCTL0EXT_RPW (_ULCAST_(0x3) << MIPS_GCTL0EXT_RPW_SHIFT) | |
881 | #define MIPS_GCTL0EXT_NCC_SHIFT 6 | |
882 | #define MIPS_GCTL0EXT_NCC (_ULCAST_(0x3) << MIPS_GCTL0EXT_NCC_SHIFT) | |
883 | #define MIPS_GCTL0EXT_CGI_SHIFT 4 | |
884 | #define MIPS_GCTL0EXT_CGI (_ULCAST_(1) << MIPS_GCTL0EXT_CGI_SHIFT) | |
885 | #define MIPS_GCTL0EXT_FCD_SHIFT 3 | |
886 | #define MIPS_GCTL0EXT_FCD (_ULCAST_(1) << MIPS_GCTL0EXT_FCD_SHIFT) | |
887 | #define MIPS_GCTL0EXT_OG_SHIFT 2 | |
888 | #define MIPS_GCTL0EXT_OG (_ULCAST_(1) << MIPS_GCTL0EXT_OG_SHIFT) | |
889 | #define MIPS_GCTL0EXT_BG_SHIFT 1 | |
890 | #define MIPS_GCTL0EXT_BG (_ULCAST_(1) << MIPS_GCTL0EXT_BG_SHIFT) | |
891 | #define MIPS_GCTL0EXT_MG_SHIFT 0 | |
892 | #define MIPS_GCTL0EXT_MG (_ULCAST_(1) << MIPS_GCTL0EXT_MG_SHIFT) | |
893 | ||
894 | /* GuestCtl0Ext.RPW Root page walk configuration */ | |
895 | #define MIPS_GCTL0EXT_RPW_BOTH 0 /* Root PW for GPA->RPA and RVA->RPA */ | |
896 | #define MIPS_GCTL0EXT_RPW_GPA 2 /* Root PW for GPA->RPA */ | |
897 | #define MIPS_GCTL0EXT_RPW_RVA 3 /* Root PW for RVA->RPA */ | |
898 | ||
899 | /* GuestCtl0Ext.NCC Nested cache coherency attributes */ | |
900 | #define MIPS_GCTL0EXT_NCC_IND 0 /* Guest CCA independent of Root CCA */ | |
901 | #define MIPS_GCTL0EXT_NCC_MOD 1 /* Guest CCA modified by Root CCA */ | |
902 | ||
903 | /* GuestCtl1 fields */ | |
904 | #define MIPS_GCTL1_ID_SHIFT 0 | |
905 | #define MIPS_GCTL1_ID_WIDTH 8 | |
906 | #define MIPS_GCTL1_ID (_ULCAST_(0xff) << MIPS_GCTL1_ID_SHIFT) | |
907 | #define MIPS_GCTL1_RID_SHIFT 16 | |
908 | #define MIPS_GCTL1_RID_WIDTH 8 | |
909 | #define MIPS_GCTL1_RID (_ULCAST_(0xff) << MIPS_GCTL1_RID_SHIFT) | |
910 | #define MIPS_GCTL1_EID_SHIFT 24 | |
911 | #define MIPS_GCTL1_EID_WIDTH 8 | |
912 | #define MIPS_GCTL1_EID (_ULCAST_(0xff) << MIPS_GCTL1_EID_SHIFT) | |
913 | ||
914 | /* GuestID reserved for root context */ | |
915 | #define MIPS_GCTL1_ROOT_GUESTID 0 | |
916 | ||
9b3274bd JH |
917 | /* CDMMBase register bit definitions */ |
918 | #define MIPS_CDMMBASE_SIZE_SHIFT 0 | |
919 | #define MIPS_CDMMBASE_SIZE (_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT) | |
920 | #define MIPS_CDMMBASE_CI (_ULCAST_(1) << 9) | |
921 | #define MIPS_CDMMBASE_EN (_ULCAST_(1) << 10) | |
922 | #define MIPS_CDMMBASE_ADDR_SHIFT 11 | |
923 | #define MIPS_CDMMBASE_ADDR_START 15 | |
924 | ||
aff565aa JH |
925 | /* RDHWR register numbers */ |
926 | #define MIPS_HWR_CPUNUM 0 /* CPU number */ | |
927 | #define MIPS_HWR_SYNCISTEP 1 /* SYNCI step size */ | |
928 | #define MIPS_HWR_CC 2 /* Cycle counter */ | |
929 | #define MIPS_HWR_CCRES 3 /* Cycle counter resolution */ | |
930 | #define MIPS_HWR_ULR 29 /* UserLocal */ | |
931 | #define MIPS_HWR_IMPL1 30 /* Implementation dependent */ | |
932 | #define MIPS_HWR_IMPL2 31 /* Implementation dependent */ | |
933 | ||
934 | /* Bits in HWREna register */ | |
935 | #define MIPS_HWRENA_CPUNUM (_ULCAST_(1) << MIPS_HWR_CPUNUM) | |
936 | #define MIPS_HWRENA_SYNCISTEP (_ULCAST_(1) << MIPS_HWR_SYNCISTEP) | |
937 | #define MIPS_HWRENA_CC (_ULCAST_(1) << MIPS_HWR_CC) | |
938 | #define MIPS_HWRENA_CCRES (_ULCAST_(1) << MIPS_HWR_CCRES) | |
939 | #define MIPS_HWRENA_ULR (_ULCAST_(1) << MIPS_HWR_ULR) | |
940 | #define MIPS_HWRENA_IMPL1 (_ULCAST_(1) << MIPS_HWR_IMPL1) | |
941 | #define MIPS_HWRENA_IMPL2 (_ULCAST_(1) << MIPS_HWR_IMPL2) | |
942 | ||
e08384ca MR |
943 | /* |
944 | * Bitfields in the TX39 family CP0 Configuration Register 3 | |
945 | */ | |
946 | #define TX39_CONF_ICS_SHIFT 19 | |
947 | #define TX39_CONF_ICS_MASK 0x00380000 | |
948 | #define TX39_CONF_ICS_1KB 0x00000000 | |
949 | #define TX39_CONF_ICS_2KB 0x00080000 | |
950 | #define TX39_CONF_ICS_4KB 0x00100000 | |
951 | #define TX39_CONF_ICS_8KB 0x00180000 | |
952 | #define TX39_CONF_ICS_16KB 0x00200000 | |
953 | ||
954 | #define TX39_CONF_DCS_SHIFT 16 | |
955 | #define TX39_CONF_DCS_MASK 0x00070000 | |
956 | #define TX39_CONF_DCS_1KB 0x00000000 | |
957 | #define TX39_CONF_DCS_2KB 0x00010000 | |
958 | #define TX39_CONF_DCS_4KB 0x00020000 | |
959 | #define TX39_CONF_DCS_8KB 0x00030000 | |
960 | #define TX39_CONF_DCS_16KB 0x00040000 | |
961 | ||
962 | #define TX39_CONF_CWFON 0x00004000 | |
963 | #define TX39_CONF_WBON 0x00002000 | |
964 | #define TX39_CONF_RF_SHIFT 10 | |
965 | #define TX39_CONF_RF_MASK 0x00000c00 | |
966 | #define TX39_CONF_DOZE 0x00000200 | |
967 | #define TX39_CONF_HALT 0x00000100 | |
968 | #define TX39_CONF_LOCK 0x00000080 | |
969 | #define TX39_CONF_ICE 0x00000020 | |
970 | #define TX39_CONF_DCE 0x00000010 | |
971 | #define TX39_CONF_IRSIZE_SHIFT 2 | |
972 | #define TX39_CONF_IRSIZE_MASK 0x0000000c | |
973 | #define TX39_CONF_DRSIZE_SHIFT 0 | |
974 | #define TX39_CONF_DRSIZE_MASK 0x00000003 | |
975 | ||
8d5ded16 JK |
976 | /* |
977 | * Interesting Bits in the R10K CP0 Branch Diagnostic Register | |
978 | */ | |
979 | /* Disable Branch Target Address Cache */ | |
980 | #define R10K_DIAG_D_BTAC (_ULCAST_(1) << 27) | |
981 | /* Enable Branch Prediction Global History */ | |
982 | #define R10K_DIAG_E_GHIST (_ULCAST_(1) << 26) | |
983 | /* Disable Branch Return Cache */ | |
984 | #define R10K_DIAG_D_BRC (_ULCAST_(1) << 22) | |
fda51906 | 985 | |
06e4814e HC |
986 | /* Flush ITLB */ |
987 | #define LOONGSON_DIAG_ITLB (_ULCAST_(1) << 2) | |
988 | /* Flush DTLB */ | |
989 | #define LOONGSON_DIAG_DTLB (_ULCAST_(1) << 3) | |
990 | /* Flush VTLB */ | |
991 | #define LOONGSON_DIAG_VTLB (_ULCAST_(1) << 12) | |
992 | /* Flush FTLB */ | |
993 | #define LOONGSON_DIAG_FTLB (_ULCAST_(1) << 13) | |
994 | ||
7d8a528d JH |
995 | /* CvmCtl register field definitions */ |
996 | #define CVMCTL_IPPCI_SHIFT 7 | |
997 | #define CVMCTL_IPPCI (_U64CAST_(0x7) << CVMCTL_IPPCI_SHIFT) | |
998 | #define CVMCTL_IPTI_SHIFT 4 | |
999 | #define CVMCTL_IPTI (_U64CAST_(0x7) << CVMCTL_IPTI_SHIFT) | |
1000 | ||
1001 | /* CvmMemCtl2 register field definitions */ | |
1002 | #define CVMMEMCTL2_INHIBITTS (_U64CAST_(1) << 17) | |
1003 | ||
1004 | /* CvmVMConfig register field definitions */ | |
1005 | #define CVMVMCONF_DGHT (_U64CAST_(1) << 60) | |
1006 | #define CVMVMCONF_MMUSIZEM1_S 12 | |
1007 | #define CVMVMCONF_MMUSIZEM1 (_U64CAST_(0xff) << CVMVMCONF_MMUSIZEM1_S) | |
1008 | #define CVMVMCONF_RMMUSIZEM1_S 0 | |
1009 | #define CVMVMCONF_RMMUSIZEM1 (_U64CAST_(0xff) << CVMVMCONF_RMMUSIZEM1_S) | |
1010 | ||
fda51906 MR |
1011 | /* |
1012 | * Coprocessor 1 (FPU) register names | |
1013 | */ | |
c491cfa2 MR |
1014 | #define CP1_REVISION $0 |
1015 | #define CP1_UFR $1 | |
1016 | #define CP1_UNFR $4 | |
1017 | #define CP1_FCCR $25 | |
1018 | #define CP1_FEXR $26 | |
1019 | #define CP1_FENR $28 | |
1020 | #define CP1_STATUS $31 | |
fda51906 MR |
1021 | |
1022 | ||
1023 | /* | |
1024 | * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register. | |
1025 | */ | |
1026 | #define MIPS_FPIR_S (_ULCAST_(1) << 16) | |
1027 | #define MIPS_FPIR_D (_ULCAST_(1) << 17) | |
1028 | #define MIPS_FPIR_PS (_ULCAST_(1) << 18) | |
1029 | #define MIPS_FPIR_3D (_ULCAST_(1) << 19) | |
1030 | #define MIPS_FPIR_W (_ULCAST_(1) << 20) | |
1031 | #define MIPS_FPIR_L (_ULCAST_(1) << 21) | |
1032 | #define MIPS_FPIR_F64 (_ULCAST_(1) << 22) | |
f1f3b7eb MR |
1033 | #define MIPS_FPIR_HAS2008 (_ULCAST_(1) << 23) |
1034 | #define MIPS_FPIR_UFRP (_ULCAST_(1) << 28) | |
fda51906 MR |
1035 | #define MIPS_FPIR_FREP (_ULCAST_(1) << 29) |
1036 | ||
c491cfa2 MR |
1037 | /* |
1038 | * Bits in the MIPS32/64 coprocessor 1 (FPU) condition codes register. | |
1039 | */ | |
1040 | #define MIPS_FCCR_CONDX_S 0 | |
1041 | #define MIPS_FCCR_CONDX (_ULCAST_(255) << MIPS_FCCR_CONDX_S) | |
1042 | #define MIPS_FCCR_COND0_S 0 | |
1043 | #define MIPS_FCCR_COND0 (_ULCAST_(1) << MIPS_FCCR_COND0_S) | |
1044 | #define MIPS_FCCR_COND1_S 1 | |
1045 | #define MIPS_FCCR_COND1 (_ULCAST_(1) << MIPS_FCCR_COND1_S) | |
1046 | #define MIPS_FCCR_COND2_S 2 | |
1047 | #define MIPS_FCCR_COND2 (_ULCAST_(1) << MIPS_FCCR_COND2_S) | |
1048 | #define MIPS_FCCR_COND3_S 3 | |
1049 | #define MIPS_FCCR_COND3 (_ULCAST_(1) << MIPS_FCCR_COND3_S) | |
1050 | #define MIPS_FCCR_COND4_S 4 | |
1051 | #define MIPS_FCCR_COND4 (_ULCAST_(1) << MIPS_FCCR_COND4_S) | |
1052 | #define MIPS_FCCR_COND5_S 5 | |
1053 | #define MIPS_FCCR_COND5 (_ULCAST_(1) << MIPS_FCCR_COND5_S) | |
1054 | #define MIPS_FCCR_COND6_S 6 | |
1055 | #define MIPS_FCCR_COND6 (_ULCAST_(1) << MIPS_FCCR_COND6_S) | |
1056 | #define MIPS_FCCR_COND7_S 7 | |
1057 | #define MIPS_FCCR_COND7 (_ULCAST_(1) << MIPS_FCCR_COND7_S) | |
1058 | ||
1059 | /* | |
1060 | * Bits in the MIPS32/64 coprocessor 1 (FPU) enables register. | |
1061 | */ | |
1062 | #define MIPS_FENR_FS_S 2 | |
1063 | #define MIPS_FENR_FS (_ULCAST_(1) << MIPS_FENR_FS_S) | |
1064 | ||
fda51906 MR |
1065 | /* |
1066 | * FPU Status Register Values | |
1067 | */ | |
c491cfa2 MR |
1068 | #define FPU_CSR_COND_S 23 /* $fcc0 */ |
1069 | #define FPU_CSR_COND (_ULCAST_(1) << FPU_CSR_COND_S) | |
1070 | ||
1071 | #define FPU_CSR_FS_S 24 /* flush denormalised results to 0 */ | |
1072 | #define FPU_CSR_FS (_ULCAST_(1) << FPU_CSR_FS_S) | |
1073 | ||
1074 | #define FPU_CSR_CONDX_S 25 /* $fcc[7:1] */ | |
1075 | #define FPU_CSR_CONDX (_ULCAST_(127) << FPU_CSR_CONDX_S) | |
1076 | #define FPU_CSR_COND1_S 25 /* $fcc1 */ | |
1077 | #define FPU_CSR_COND1 (_ULCAST_(1) << FPU_CSR_COND1_S) | |
1078 | #define FPU_CSR_COND2_S 26 /* $fcc2 */ | |
1079 | #define FPU_CSR_COND2 (_ULCAST_(1) << FPU_CSR_COND2_S) | |
1080 | #define FPU_CSR_COND3_S 27 /* $fcc3 */ | |
1081 | #define FPU_CSR_COND3 (_ULCAST_(1) << FPU_CSR_COND3_S) | |
1082 | #define FPU_CSR_COND4_S 28 /* $fcc4 */ | |
1083 | #define FPU_CSR_COND4 (_ULCAST_(1) << FPU_CSR_COND4_S) | |
1084 | #define FPU_CSR_COND5_S 29 /* $fcc5 */ | |
1085 | #define FPU_CSR_COND5 (_ULCAST_(1) << FPU_CSR_COND5_S) | |
1086 | #define FPU_CSR_COND6_S 30 /* $fcc6 */ | |
1087 | #define FPU_CSR_COND6 (_ULCAST_(1) << FPU_CSR_COND6_S) | |
1088 | #define FPU_CSR_COND7_S 31 /* $fcc7 */ | |
1089 | #define FPU_CSR_COND7 (_ULCAST_(1) << FPU_CSR_COND7_S) | |
fda51906 MR |
1090 | |
1091 | /* | |
f1f3b7eb | 1092 | * Bits 22:20 of the FPU Status Register will be read as 0, |
fda51906 MR |
1093 | * and should be written as zero. |
1094 | */ | |
f1f3b7eb MR |
1095 | #define FPU_CSR_RSVD (_ULCAST_(7) << 20) |
1096 | ||
1097 | #define FPU_CSR_ABS2008 (_ULCAST_(1) << 19) | |
1098 | #define FPU_CSR_NAN2008 (_ULCAST_(1) << 18) | |
fda51906 MR |
1099 | |
1100 | /* | |
1101 | * X the exception cause indicator | |
1102 | * E the exception enable | |
1103 | * S the sticky/flag bit | |
1104 | */ | |
1105 | #define FPU_CSR_ALL_X 0x0003f000 | |
1106 | #define FPU_CSR_UNI_X 0x00020000 | |
1107 | #define FPU_CSR_INV_X 0x00010000 | |
1108 | #define FPU_CSR_DIV_X 0x00008000 | |
1109 | #define FPU_CSR_OVF_X 0x00004000 | |
1110 | #define FPU_CSR_UDF_X 0x00002000 | |
1111 | #define FPU_CSR_INE_X 0x00001000 | |
1112 | ||
1113 | #define FPU_CSR_ALL_E 0x00000f80 | |
1114 | #define FPU_CSR_INV_E 0x00000800 | |
1115 | #define FPU_CSR_DIV_E 0x00000400 | |
1116 | #define FPU_CSR_OVF_E 0x00000200 | |
1117 | #define FPU_CSR_UDF_E 0x00000100 | |
1118 | #define FPU_CSR_INE_E 0x00000080 | |
1119 | ||
1120 | #define FPU_CSR_ALL_S 0x0000007c | |
1121 | #define FPU_CSR_INV_S 0x00000040 | |
1122 | #define FPU_CSR_DIV_S 0x00000020 | |
1123 | #define FPU_CSR_OVF_S 0x00000010 | |
1124 | #define FPU_CSR_UDF_S 0x00000008 | |
1125 | #define FPU_CSR_INE_S 0x00000004 | |
1126 | ||
1127 | /* Bits 0 and 1 of FPU Status Register specify the rounding mode */ | |
1128 | #define FPU_CSR_RM 0x00000003 | |
1129 | #define FPU_CSR_RN 0x0 /* nearest */ | |
1130 | #define FPU_CSR_RZ 0x1 /* towards zero */ | |
1131 | #define FPU_CSR_RU 0x2 /* towards +Infinity */ | |
1132 | #define FPU_CSR_RD 0x3 /* towards -Infinity */ | |
1133 | ||
1134 | ||
1da177e4 LT |
1135 | #ifndef __ASSEMBLY__ |
1136 | ||
bfd08baa | 1137 | /* |
377cb1b6 | 1138 | * Macros for handling the ISA mode bit for MIPS16 and microMIPS. |
bfd08baa | 1139 | */ |
377cb1b6 RB |
1140 | #if defined(CONFIG_SYS_SUPPORTS_MIPS16) || \ |
1141 | defined(CONFIG_SYS_SUPPORTS_MICROMIPS) | |
bfd08baa SH |
1142 | #define get_isa16_mode(x) ((x) & 0x1) |
1143 | #define msk_isa16_mode(x) ((x) & ~0x1) | |
1144 | #define set_isa16_mode(x) do { (x) |= 0x1; } while(0) | |
377cb1b6 RB |
1145 | #else |
1146 | #define get_isa16_mode(x) 0 | |
1147 | #define msk_isa16_mode(x) (x) | |
1148 | #define set_isa16_mode(x) do { } while(0) | |
1149 | #endif | |
bfd08baa SH |
1150 | |
1151 | /* | |
1152 | * microMIPS instructions can be 16-bit or 32-bit in length. This | |
1153 | * returns a 1 if the instruction is 16-bit and a 0 if 32-bit. | |
1154 | */ | |
1155 | static inline int mm_insn_16bit(u16 insn) | |
1156 | { | |
1157 | u16 opcode = (insn >> 10) & 0x7; | |
1158 | ||
1159 | return (opcode >= 1 && opcode <= 3) ? 1 : 0; | |
1160 | } | |
1161 | ||
0dfa1c12 JH |
1162 | /* |
1163 | * Helper macros for generating raw instruction encodings in inline asm. | |
1164 | */ | |
1165 | #ifdef CONFIG_CPU_MICROMIPS | |
1166 | #define _ASM_INSN16_IF_MM(_enc) \ | |
1167 | ".insn\n\t" \ | |
1168 | ".hword (" #_enc ")\n\t" | |
1169 | #define _ASM_INSN32_IF_MM(_enc) \ | |
1170 | ".insn\n\t" \ | |
1171 | ".hword ((" #_enc ") >> 16)\n\t" \ | |
1172 | ".hword ((" #_enc ") & 0xffff)\n\t" | |
1173 | #else | |
1174 | #define _ASM_INSN_IF_MIPS(_enc) \ | |
1175 | ".insn\n\t" \ | |
1176 | ".word (" #_enc ")\n\t" | |
1177 | #endif | |
1178 | ||
1179 | #ifndef _ASM_INSN16_IF_MM | |
1180 | #define _ASM_INSN16_IF_MM(_enc) | |
1181 | #endif | |
1182 | #ifndef _ASM_INSN32_IF_MM | |
1183 | #define _ASM_INSN32_IF_MM(_enc) | |
1184 | #endif | |
1185 | #ifndef _ASM_INSN_IF_MIPS | |
1186 | #define _ASM_INSN_IF_MIPS(_enc) | |
1187 | #endif | |
1188 | ||
fc62f53b JH |
1189 | /* |
1190 | * parse_r var, r - Helper assembler macro for parsing register names. | |
1191 | * | |
1192 | * This converts the register name in $n form provided in \r to the | |
1193 | * corresponding register number, which is assigned to the variable \var. It is | |
1194 | * needed to allow explicit encoding of instructions in inline assembly where | |
1195 | * registers are chosen by the compiler in $n form, allowing us to avoid using | |
1196 | * fixed register numbers. | |
1197 | * | |
1198 | * It also allows newer instructions (not implemented by the assembler) to be | |
1199 | * transparently implemented using assembler macros, instead of needing separate | |
1200 | * cases depending on toolchain support. | |
1201 | * | |
1202 | * Simple usage example: | |
1203 | * __asm__ __volatile__("parse_r __rt, %0\n\t" | |
1204 | * ".insn\n\t" | |
1205 | * "# di %0\n\t" | |
1206 | * ".word (0x41606000 | (__rt << 16))" | |
1207 | * : "=r" (status); | |
1208 | */ | |
1209 | ||
1210 | /* Match an individual register number and assign to \var */ | |
1211 | #define _IFC_REG(n) \ | |
1212 | ".ifc \\r, $" #n "\n\t" \ | |
1213 | "\\var = " #n "\n\t" \ | |
1214 | ".endif\n\t" | |
1215 | ||
1216 | __asm__(".macro parse_r var r\n\t" | |
1217 | "\\var = -1\n\t" | |
1218 | _IFC_REG(0) _IFC_REG(1) _IFC_REG(2) _IFC_REG(3) | |
1219 | _IFC_REG(4) _IFC_REG(5) _IFC_REG(6) _IFC_REG(7) | |
1220 | _IFC_REG(8) _IFC_REG(9) _IFC_REG(10) _IFC_REG(11) | |
1221 | _IFC_REG(12) _IFC_REG(13) _IFC_REG(14) _IFC_REG(15) | |
1222 | _IFC_REG(16) _IFC_REG(17) _IFC_REG(18) _IFC_REG(19) | |
1223 | _IFC_REG(20) _IFC_REG(21) _IFC_REG(22) _IFC_REG(23) | |
1224 | _IFC_REG(24) _IFC_REG(25) _IFC_REG(26) _IFC_REG(27) | |
1225 | _IFC_REG(28) _IFC_REG(29) _IFC_REG(30) _IFC_REG(31) | |
1226 | ".iflt \\var\n\t" | |
1227 | ".error \"Unable to parse register name \\r\"\n\t" | |
1228 | ".endif\n\t" | |
1229 | ".endm"); | |
1230 | ||
1231 | #undef _IFC_REG | |
1232 | ||
1233 | /* | |
1234 | * C macros for generating assembler macros for common instruction formats. | |
1235 | * | |
1236 | * The names of the operands can be chosen by the caller, and the encoding of | |
1237 | * register operand \<Rn> is assigned to __<Rn> where it can be accessed from | |
1238 | * the ENC encodings. | |
1239 | */ | |
1240 | ||
1241 | /* Instructions with no operands */ | |
1242 | #define _ASM_MACRO_0(OP, ENC) \ | |
1243 | __asm__(".macro " #OP "\n\t" \ | |
1244 | ENC \ | |
1245 | ".endm") | |
1246 | ||
1247 | /* Instructions with 2 register operands */ | |
1248 | #define _ASM_MACRO_2R(OP, R1, R2, ENC) \ | |
1249 | __asm__(".macro " #OP " " #R1 ", " #R2 "\n\t" \ | |
1250 | "parse_r __" #R1 ", \\" #R1 "\n\t" \ | |
1251 | "parse_r __" #R2 ", \\" #R2 "\n\t" \ | |
1252 | ENC \ | |
1253 | ".endm") | |
1254 | ||
1255 | /* Instructions with 3 register operands */ | |
1256 | #define _ASM_MACRO_3R(OP, R1, R2, R3, ENC) \ | |
1257 | __asm__(".macro " #OP " " #R1 ", " #R2 ", " #R3 "\n\t" \ | |
1258 | "parse_r __" #R1 ", \\" #R1 "\n\t" \ | |
1259 | "parse_r __" #R2 ", \\" #R2 "\n\t" \ | |
1260 | "parse_r __" #R3 ", \\" #R3 "\n\t" \ | |
1261 | ENC \ | |
1262 | ".endm") | |
1263 | ||
1264 | /* Instructions with 2 register operands and 1 optional select operand */ | |
1265 | #define _ASM_MACRO_2R_1S(OP, R1, R2, SEL3, ENC) \ | |
1266 | __asm__(".macro " #OP " " #R1 ", " #R2 ", " #SEL3 " = 0\n\t" \ | |
1267 | "parse_r __" #R1 ", \\" #R1 "\n\t" \ | |
1268 | "parse_r __" #R2 ", \\" #R2 "\n\t" \ | |
1269 | ENC \ | |
1270 | ".endm") | |
1271 | ||
198bb4ce LY |
1272 | /* |
1273 | * TLB Invalidate Flush | |
1274 | */ | |
1275 | static inline void tlbinvf(void) | |
1276 | { | |
1277 | __asm__ __volatile__( | |
1278 | ".set push\n\t" | |
1279 | ".set noreorder\n\t" | |
c84700cc JH |
1280 | "# tlbinvf\n\t" |
1281 | _ASM_INSN_IF_MIPS(0x42000004) | |
1282 | _ASM_INSN32_IF_MM(0x0000537c) | |
198bb4ce LY |
1283 | ".set pop"); |
1284 | } | |
1285 | ||
1286 | ||
1da177e4 | 1287 | /* |
70342287 | 1288 | * Functions to access the R10000 performance counters. These are basically |
1da177e4 LT |
1289 | * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit |
1290 | * performance counter number encoded into bits 1 ... 5 of the instruction. | |
1291 | * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware | |
1292 | * disassembler these will look like an access to sel 0 or 1. | |
1293 | */ | |
1294 | #define read_r10k_perf_cntr(counter) \ | |
1295 | ({ \ | |
1296 | unsigned int __res; \ | |
1297 | __asm__ __volatile__( \ | |
1298 | "mfpc\t%0, %1" \ | |
70342287 | 1299 | : "=r" (__res) \ |
1da177e4 LT |
1300 | : "i" (counter)); \ |
1301 | \ | |
70342287 | 1302 | __res; \ |
1da177e4 LT |
1303 | }) |
1304 | ||
70342287 | 1305 | #define write_r10k_perf_cntr(counter,val) \ |
1da177e4 LT |
1306 | do { \ |
1307 | __asm__ __volatile__( \ | |
1308 | "mtpc\t%0, %1" \ | |
1309 | : \ | |
1310 | : "r" (val), "i" (counter)); \ | |
1311 | } while (0) | |
1312 | ||
1313 | #define read_r10k_perf_event(counter) \ | |
1314 | ({ \ | |
1315 | unsigned int __res; \ | |
1316 | __asm__ __volatile__( \ | |
1317 | "mfps\t%0, %1" \ | |
70342287 | 1318 | : "=r" (__res) \ |
1da177e4 LT |
1319 | : "i" (counter)); \ |
1320 | \ | |
70342287 | 1321 | __res; \ |
1da177e4 LT |
1322 | }) |
1323 | ||
70342287 | 1324 | #define write_r10k_perf_cntl(counter,val) \ |
1da177e4 LT |
1325 | do { \ |
1326 | __asm__ __volatile__( \ | |
1327 | "mtps\t%0, %1" \ | |
1328 | : \ | |
1329 | : "r" (val), "i" (counter)); \ | |
1330 | } while (0) | |
1331 | ||
1332 | ||
1333 | /* | |
1334 | * Macros to access the system control coprocessor | |
1335 | */ | |
1336 | ||
cd1e0737 | 1337 | #define ___read_32bit_c0_register(source, sel, vol) \ |
82eb8f73 | 1338 | ({ unsigned int __res; \ |
1da177e4 | 1339 | if (sel == 0) \ |
cd1e0737 | 1340 | __asm__ vol( \ |
1da177e4 LT |
1341 | "mfc0\t%0, " #source "\n\t" \ |
1342 | : "=r" (__res)); \ | |
1343 | else \ | |
cd1e0737 | 1344 | __asm__ vol( \ |
1da177e4 LT |
1345 | ".set\tmips32\n\t" \ |
1346 | "mfc0\t%0, " #source ", " #sel "\n\t" \ | |
1347 | ".set\tmips0\n\t" \ | |
1348 | : "=r" (__res)); \ | |
1349 | __res; \ | |
1350 | }) | |
1351 | ||
cd1e0737 | 1352 | #define ___read_64bit_c0_register(source, sel, vol) \ |
1da177e4 LT |
1353 | ({ unsigned long long __res; \ |
1354 | if (sizeof(unsigned long) == 4) \ | |
cd1e0737 | 1355 | __res = __read_64bit_c0_split(source, sel, vol); \ |
1da177e4 | 1356 | else if (sel == 0) \ |
cd1e0737 | 1357 | __asm__ vol( \ |
1da177e4 LT |
1358 | ".set\tmips3\n\t" \ |
1359 | "dmfc0\t%0, " #source "\n\t" \ | |
1360 | ".set\tmips0" \ | |
1361 | : "=r" (__res)); \ | |
1362 | else \ | |
cd1e0737 | 1363 | __asm__ vol( \ |
1da177e4 LT |
1364 | ".set\tmips64\n\t" \ |
1365 | "dmfc0\t%0, " #source ", " #sel "\n\t" \ | |
1366 | ".set\tmips0" \ | |
1367 | : "=r" (__res)); \ | |
1368 | __res; \ | |
1369 | }) | |
1370 | ||
cd1e0737 JH |
1371 | #define __read_32bit_c0_register(source, sel) \ |
1372 | ___read_32bit_c0_register(source, sel, __volatile__) | |
1373 | ||
1374 | #define __read_const_32bit_c0_register(source, sel) \ | |
1375 | ___read_32bit_c0_register(source, sel,) | |
1376 | ||
1377 | #define __read_64bit_c0_register(source, sel) \ | |
1378 | ___read_64bit_c0_register(source, sel, __volatile__) | |
1379 | ||
1380 | #define __read_const_64bit_c0_register(source, sel) \ | |
1381 | ___read_64bit_c0_register(source, sel,) | |
1382 | ||
1da177e4 LT |
1383 | #define __write_32bit_c0_register(register, sel, value) \ |
1384 | do { \ | |
1385 | if (sel == 0) \ | |
1386 | __asm__ __volatile__( \ | |
1387 | "mtc0\t%z0, " #register "\n\t" \ | |
0952e290 | 1388 | : : "Jr" ((unsigned int)(value))); \ |
1da177e4 LT |
1389 | else \ |
1390 | __asm__ __volatile__( \ | |
1391 | ".set\tmips32\n\t" \ | |
1392 | "mtc0\t%z0, " #register ", " #sel "\n\t" \ | |
1393 | ".set\tmips0" \ | |
0952e290 | 1394 | : : "Jr" ((unsigned int)(value))); \ |
1da177e4 LT |
1395 | } while (0) |
1396 | ||
1397 | #define __write_64bit_c0_register(register, sel, value) \ | |
1398 | do { \ | |
1399 | if (sizeof(unsigned long) == 4) \ | |
1400 | __write_64bit_c0_split(register, sel, value); \ | |
1401 | else if (sel == 0) \ | |
1402 | __asm__ __volatile__( \ | |
1403 | ".set\tmips3\n\t" \ | |
1404 | "dmtc0\t%z0, " #register "\n\t" \ | |
1405 | ".set\tmips0" \ | |
1406 | : : "Jr" (value)); \ | |
1407 | else \ | |
1408 | __asm__ __volatile__( \ | |
1409 | ".set\tmips64\n\t" \ | |
1410 | "dmtc0\t%z0, " #register ", " #sel "\n\t" \ | |
1411 | ".set\tmips0" \ | |
1412 | : : "Jr" (value)); \ | |
1413 | } while (0) | |
1414 | ||
1415 | #define __read_ulong_c0_register(reg, sel) \ | |
1416 | ((sizeof(unsigned long) == 4) ? \ | |
1417 | (unsigned long) __read_32bit_c0_register(reg, sel) : \ | |
1418 | (unsigned long) __read_64bit_c0_register(reg, sel)) | |
1419 | ||
cd1e0737 JH |
1420 | #define __read_const_ulong_c0_register(reg, sel) \ |
1421 | ((sizeof(unsigned long) == 4) ? \ | |
1422 | (unsigned long) __read_const_32bit_c0_register(reg, sel) : \ | |
1423 | (unsigned long) __read_const_64bit_c0_register(reg, sel)) | |
1424 | ||
1da177e4 LT |
1425 | #define __write_ulong_c0_register(reg, sel, val) \ |
1426 | do { \ | |
1427 | if (sizeof(unsigned long) == 4) \ | |
1428 | __write_32bit_c0_register(reg, sel, val); \ | |
1429 | else \ | |
1430 | __write_64bit_c0_register(reg, sel, val); \ | |
1431 | } while (0) | |
1432 | ||
1433 | /* | |
1434 | * On RM7000/RM9000 these are uses to access cop0 set 1 registers | |
1435 | */ | |
1436 | #define __read_32bit_c0_ctrl_register(source) \ | |
82eb8f73 | 1437 | ({ unsigned int __res; \ |
1da177e4 LT |
1438 | __asm__ __volatile__( \ |
1439 | "cfc0\t%0, " #source "\n\t" \ | |
1440 | : "=r" (__res)); \ | |
1441 | __res; \ | |
1442 | }) | |
1443 | ||
1444 | #define __write_32bit_c0_ctrl_register(register, value) \ | |
1445 | do { \ | |
1446 | __asm__ __volatile__( \ | |
1447 | "ctc0\t%z0, " #register "\n\t" \ | |
0952e290 | 1448 | : : "Jr" ((unsigned int)(value))); \ |
1da177e4 LT |
1449 | } while (0) |
1450 | ||
1451 | /* | |
1452 | * These versions are only needed for systems with more than 38 bits of | |
1453 | * physical address space running the 32-bit kernel. That's none atm :-) | |
1454 | */ | |
cd1e0737 | 1455 | #define __read_64bit_c0_split(source, sel, vol) \ |
1da177e4 | 1456 | ({ \ |
87d43dd4 AN |
1457 | unsigned long long __val; \ |
1458 | unsigned long __flags; \ | |
1da177e4 | 1459 | \ |
87d43dd4 | 1460 | local_irq_save(__flags); \ |
1da177e4 | 1461 | if (sel == 0) \ |
cd1e0737 | 1462 | __asm__ vol( \ |
1da177e4 | 1463 | ".set\tmips64\n\t" \ |
d3a0b968 MR |
1464 | "dmfc0\t%L0, " #source "\n\t" \ |
1465 | "dsra\t%M0, %L0, 32\n\t" \ | |
1466 | "sll\t%L0, %L0, 0\n\t" \ | |
1da177e4 | 1467 | ".set\tmips0" \ |
87d43dd4 | 1468 | : "=r" (__val)); \ |
1da177e4 | 1469 | else \ |
cd1e0737 | 1470 | __asm__ vol( \ |
1da177e4 | 1471 | ".set\tmips64\n\t" \ |
d3a0b968 MR |
1472 | "dmfc0\t%L0, " #source ", " #sel "\n\t" \ |
1473 | "dsra\t%M0, %L0, 32\n\t" \ | |
1474 | "sll\t%L0, %L0, 0\n\t" \ | |
1da177e4 | 1475 | ".set\tmips0" \ |
87d43dd4 AN |
1476 | : "=r" (__val)); \ |
1477 | local_irq_restore(__flags); \ | |
1da177e4 | 1478 | \ |
87d43dd4 | 1479 | __val; \ |
1da177e4 LT |
1480 | }) |
1481 | ||
1482 | #define __write_64bit_c0_split(source, sel, val) \ | |
1483 | do { \ | |
c22c8043 | 1484 | unsigned long long __tmp; \ |
87d43dd4 | 1485 | unsigned long __flags; \ |
1da177e4 | 1486 | \ |
87d43dd4 | 1487 | local_irq_save(__flags); \ |
1da177e4 LT |
1488 | if (sel == 0) \ |
1489 | __asm__ __volatile__( \ | |
1490 | ".set\tmips64\n\t" \ | |
c22c8043 | 1491 | "dsll\t%L0, %L1, 32\n\t" \ |
1da177e4 | 1492 | "dsrl\t%L0, %L0, 32\n\t" \ |
c22c8043 | 1493 | "dsll\t%M0, %M1, 32\n\t" \ |
1da177e4 LT |
1494 | "or\t%L0, %L0, %M0\n\t" \ |
1495 | "dmtc0\t%L0, " #source "\n\t" \ | |
1496 | ".set\tmips0" \ | |
c22c8043 JH |
1497 | : "=&r,r" (__tmp) \ |
1498 | : "r,0" (val)); \ | |
1da177e4 LT |
1499 | else \ |
1500 | __asm__ __volatile__( \ | |
1501 | ".set\tmips64\n\t" \ | |
c22c8043 | 1502 | "dsll\t%L0, %L1, 32\n\t" \ |
1da177e4 | 1503 | "dsrl\t%L0, %L0, 32\n\t" \ |
c22c8043 | 1504 | "dsll\t%M0, %M1, 32\n\t" \ |
1da177e4 LT |
1505 | "or\t%L0, %L0, %M0\n\t" \ |
1506 | "dmtc0\t%L0, " #source ", " #sel "\n\t" \ | |
1507 | ".set\tmips0" \ | |
c22c8043 JH |
1508 | : "=&r,r" (__tmp) \ |
1509 | : "r,0" (val)); \ | |
87d43dd4 | 1510 | local_irq_restore(__flags); \ |
1da177e4 LT |
1511 | } while (0) |
1512 | ||
8e4789d2 JH |
1513 | #ifndef TOOLCHAIN_SUPPORTS_XPA |
1514 | _ASM_MACRO_2R_1S(mfhc0, rt, rs, sel, | |
1515 | _ASM_INSN_IF_MIPS(0x40400000 | __rt << 16 | __rs << 11 | \\sel) | |
1516 | _ASM_INSN32_IF_MM(0x000000f4 | __rt << 21 | __rs << 16 | \\sel << 11)); | |
1517 | _ASM_MACRO_2R_1S(mthc0, rt, rd, sel, | |
1518 | _ASM_INSN_IF_MIPS(0x40c00000 | __rt << 16 | __rd << 11 | \\sel) | |
1519 | _ASM_INSN32_IF_MM(0x000002f4 | __rt << 21 | __rd << 16 | \\sel << 11)); | |
1520 | #define _ASM_SET_XPA "" | |
1521 | #else /* !TOOLCHAIN_SUPPORTS_XPA */ | |
1522 | #define _ASM_SET_XPA ".set\txpa\n\t" | |
1523 | #endif | |
1524 | ||
abbd52fd | 1525 | #define __readx_32bit_c0_register(source, sel) \ |
23d06e4f SH |
1526 | ({ \ |
1527 | unsigned int __res; \ | |
1528 | \ | |
1529 | __asm__ __volatile__( \ | |
1530 | " .set push \n" \ | |
23d06e4f | 1531 | " .set mips32r2 \n" \ |
8e4789d2 | 1532 | _ASM_SET_XPA \ |
abbd52fd | 1533 | " mfhc0 %0, " #source ", %1 \n" \ |
23d06e4f SH |
1534 | " .set pop \n" \ |
1535 | : "=r" (__res) \ | |
abbd52fd | 1536 | : "i" (sel)); \ |
23d06e4f SH |
1537 | __res; \ |
1538 | }) | |
1539 | ||
abbd52fd | 1540 | #define __writex_32bit_c0_register(register, sel, value) \ |
23d06e4f SH |
1541 | do { \ |
1542 | __asm__ __volatile__( \ | |
1543 | " .set push \n" \ | |
23d06e4f | 1544 | " .set mips32r2 \n" \ |
8e4789d2 | 1545 | _ASM_SET_XPA \ |
abbd52fd | 1546 | " mthc0 %z0, " #register ", %1 \n" \ |
23d06e4f SH |
1547 | " .set pop \n" \ |
1548 | : \ | |
abbd52fd | 1549 | : "Jr" (value), "i" (sel)); \ |
23d06e4f SH |
1550 | } while (0) |
1551 | ||
1da177e4 LT |
1552 | #define read_c0_index() __read_32bit_c0_register($0, 0) |
1553 | #define write_c0_index(val) __write_32bit_c0_register($0, 0, val) | |
1554 | ||
272bace7 RB |
1555 | #define read_c0_random() __read_32bit_c0_register($1, 0) |
1556 | #define write_c0_random(val) __write_32bit_c0_register($1, 0, val) | |
1557 | ||
1da177e4 LT |
1558 | #define read_c0_entrylo0() __read_ulong_c0_register($2, 0) |
1559 | #define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val) | |
1560 | ||
abbd52fd JH |
1561 | #define readx_c0_entrylo0() __readx_32bit_c0_register($2, 0) |
1562 | #define writex_c0_entrylo0(val) __writex_32bit_c0_register($2, 0, val) | |
23d06e4f | 1563 | |
1da177e4 LT |
1564 | #define read_c0_entrylo1() __read_ulong_c0_register($3, 0) |
1565 | #define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val) | |
1566 | ||
abbd52fd JH |
1567 | #define readx_c0_entrylo1() __readx_32bit_c0_register($3, 0) |
1568 | #define writex_c0_entrylo1(val) __writex_32bit_c0_register($3, 0, val) | |
23d06e4f | 1569 | |
1da177e4 LT |
1570 | #define read_c0_conf() __read_32bit_c0_register($3, 0) |
1571 | #define write_c0_conf(val) __write_32bit_c0_register($3, 0, val) | |
1572 | ||
c6593dde PB |
1573 | #define read_c0_globalnumber() __read_32bit_c0_register($3, 1) |
1574 | ||
1da177e4 LT |
1575 | #define read_c0_context() __read_ulong_c0_register($4, 0) |
1576 | #define write_c0_context(val) __write_ulong_c0_register($4, 0, val) | |
1577 | ||
f18bdfa1 JH |
1578 | #define read_c0_contextconfig() __read_32bit_c0_register($4, 1) |
1579 | #define write_c0_contextconfig(val) __write_32bit_c0_register($4, 1, val) | |
1580 | ||
a3692020 | 1581 | #define read_c0_userlocal() __read_ulong_c0_register($4, 2) |
70342287 | 1582 | #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val) |
a3692020 | 1583 | |
f18bdfa1 JH |
1584 | #define read_c0_xcontextconfig() __read_ulong_c0_register($4, 3) |
1585 | #define write_c0_xcontextconfig(val) __write_ulong_c0_register($4, 3, val) | |
1586 | ||
1da177e4 LT |
1587 | #define read_c0_pagemask() __read_32bit_c0_register($5, 0) |
1588 | #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) | |
1589 | ||
9fe2e9d6 | 1590 | #define read_c0_pagegrain() __read_32bit_c0_register($5, 1) |
70342287 | 1591 | #define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val) |
9fe2e9d6 | 1592 | |
1da177e4 LT |
1593 | #define read_c0_wired() __read_32bit_c0_register($6, 0) |
1594 | #define write_c0_wired(val) __write_32bit_c0_register($6, 0, val) | |
1595 | ||
1596 | #define read_c0_info() __read_32bit_c0_register($7, 0) | |
1597 | ||
70342287 | 1598 | #define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */ |
1da177e4 LT |
1599 | #define write_c0_cache(val) __write_32bit_c0_register($7, 0, val) |
1600 | ||
15c4f67a RB |
1601 | #define read_c0_badvaddr() __read_ulong_c0_register($8, 0) |
1602 | #define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val) | |
1603 | ||
e06a1548 JH |
1604 | #define read_c0_badinstr() __read_32bit_c0_register($8, 1) |
1605 | #define read_c0_badinstrp() __read_32bit_c0_register($8, 2) | |
1606 | ||
1da177e4 LT |
1607 | #define read_c0_count() __read_32bit_c0_register($9, 0) |
1608 | #define write_c0_count(val) __write_32bit_c0_register($9, 0, val) | |
1609 | ||
bdf21b18 PP |
1610 | #define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */ |
1611 | #define write_c0_count2(val) __write_32bit_c0_register($9, 6, val) | |
1612 | ||
1613 | #define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */ | |
1614 | #define write_c0_count3(val) __write_32bit_c0_register($9, 7, val) | |
1615 | ||
1da177e4 LT |
1616 | #define read_c0_entryhi() __read_ulong_c0_register($10, 0) |
1617 | #define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val) | |
1618 | ||
f913e9ea JH |
1619 | #define read_c0_guestctl1() __read_32bit_c0_register($10, 4) |
1620 | #define write_c0_guestctl1(val) __write_32bit_c0_register($10, 4, val) | |
1621 | ||
1622 | #define read_c0_guestctl2() __read_32bit_c0_register($10, 5) | |
1623 | #define write_c0_guestctl2(val) __write_32bit_c0_register($10, 5, val) | |
1624 | ||
1625 | #define read_c0_guestctl3() __read_32bit_c0_register($10, 6) | |
1626 | #define write_c0_guestctl3(val) __write_32bit_c0_register($10, 6, val) | |
1627 | ||
1da177e4 LT |
1628 | #define read_c0_compare() __read_32bit_c0_register($11, 0) |
1629 | #define write_c0_compare(val) __write_32bit_c0_register($11, 0, val) | |
1630 | ||
f913e9ea JH |
1631 | #define read_c0_guestctl0ext() __read_32bit_c0_register($11, 4) |
1632 | #define write_c0_guestctl0ext(val) __write_32bit_c0_register($11, 4, val) | |
1633 | ||
bdf21b18 PP |
1634 | #define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */ |
1635 | #define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val) | |
1636 | ||
1637 | #define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */ | |
1638 | #define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val) | |
1639 | ||
1da177e4 | 1640 | #define read_c0_status() __read_32bit_c0_register($12, 0) |
b633648c | 1641 | |
1da177e4 LT |
1642 | #define write_c0_status(val) __write_32bit_c0_register($12, 0, val) |
1643 | ||
f913e9ea JH |
1644 | #define read_c0_guestctl0() __read_32bit_c0_register($12, 6) |
1645 | #define write_c0_guestctl0(val) __write_32bit_c0_register($12, 6, val) | |
1646 | ||
1647 | #define read_c0_gtoffset() __read_32bit_c0_register($12, 7) | |
1648 | #define write_c0_gtoffset(val) __write_32bit_c0_register($12, 7, val) | |
1649 | ||
1da177e4 LT |
1650 | #define read_c0_cause() __read_32bit_c0_register($13, 0) |
1651 | #define write_c0_cause(val) __write_32bit_c0_register($13, 0, val) | |
1652 | ||
1653 | #define read_c0_epc() __read_ulong_c0_register($14, 0) | |
1654 | #define write_c0_epc(val) __write_ulong_c0_register($14, 0, val) | |
1655 | ||
6538953f | 1656 | #define read_c0_prid() __read_const_32bit_c0_register($15, 0) |
1da177e4 | 1657 | |
4dd8ee5d PB |
1658 | #define read_c0_cmgcrbase() __read_ulong_c0_register($15, 3) |
1659 | ||
1da177e4 LT |
1660 | #define read_c0_config() __read_32bit_c0_register($16, 0) |
1661 | #define read_c0_config1() __read_32bit_c0_register($16, 1) | |
1662 | #define read_c0_config2() __read_32bit_c0_register($16, 2) | |
1663 | #define read_c0_config3() __read_32bit_c0_register($16, 3) | |
0efe2761 RB |
1664 | #define read_c0_config4() __read_32bit_c0_register($16, 4) |
1665 | #define read_c0_config5() __read_32bit_c0_register($16, 5) | |
1666 | #define read_c0_config6() __read_32bit_c0_register($16, 6) | |
1667 | #define read_c0_config7() __read_32bit_c0_register($16, 7) | |
1da177e4 LT |
1668 | #define write_c0_config(val) __write_32bit_c0_register($16, 0, val) |
1669 | #define write_c0_config1(val) __write_32bit_c0_register($16, 1, val) | |
1670 | #define write_c0_config2(val) __write_32bit_c0_register($16, 2, val) | |
1671 | #define write_c0_config3(val) __write_32bit_c0_register($16, 3, val) | |
0efe2761 RB |
1672 | #define write_c0_config4(val) __write_32bit_c0_register($16, 4, val) |
1673 | #define write_c0_config5(val) __write_32bit_c0_register($16, 5, val) | |
1674 | #define write_c0_config6(val) __write_32bit_c0_register($16, 6, val) | |
1675 | #define write_c0_config7(val) __write_32bit_c0_register($16, 7, val) | |
1da177e4 | 1676 | |
b55b9e27 MC |
1677 | #define read_c0_lladdr() __read_ulong_c0_register($17, 0) |
1678 | #define write_c0_lladdr(val) __write_ulong_c0_register($17, 0, val) | |
e19d5dba PB |
1679 | #define read_c0_maar() __read_ulong_c0_register($17, 1) |
1680 | #define write_c0_maar(val) __write_ulong_c0_register($17, 1, val) | |
1681 | #define read_c0_maari() __read_32bit_c0_register($17, 2) | |
1682 | #define write_c0_maari(val) __write_32bit_c0_register($17, 2, val) | |
1683 | ||
1da177e4 | 1684 | /* |
25985edc | 1685 | * The WatchLo register. There may be up to 8 of them. |
1da177e4 LT |
1686 | */ |
1687 | #define read_c0_watchlo0() __read_ulong_c0_register($18, 0) | |
1688 | #define read_c0_watchlo1() __read_ulong_c0_register($18, 1) | |
1689 | #define read_c0_watchlo2() __read_ulong_c0_register($18, 2) | |
1690 | #define read_c0_watchlo3() __read_ulong_c0_register($18, 3) | |
1691 | #define read_c0_watchlo4() __read_ulong_c0_register($18, 4) | |
1692 | #define read_c0_watchlo5() __read_ulong_c0_register($18, 5) | |
1693 | #define read_c0_watchlo6() __read_ulong_c0_register($18, 6) | |
1694 | #define read_c0_watchlo7() __read_ulong_c0_register($18, 7) | |
1695 | #define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val) | |
1696 | #define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val) | |
1697 | #define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val) | |
1698 | #define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val) | |
1699 | #define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val) | |
1700 | #define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val) | |
1701 | #define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val) | |
1702 | #define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val) | |
1703 | ||
1704 | /* | |
25985edc | 1705 | * The WatchHi register. There may be up to 8 of them. |
1da177e4 LT |
1706 | */ |
1707 | #define read_c0_watchhi0() __read_32bit_c0_register($19, 0) | |
1708 | #define read_c0_watchhi1() __read_32bit_c0_register($19, 1) | |
1709 | #define read_c0_watchhi2() __read_32bit_c0_register($19, 2) | |
1710 | #define read_c0_watchhi3() __read_32bit_c0_register($19, 3) | |
1711 | #define read_c0_watchhi4() __read_32bit_c0_register($19, 4) | |
1712 | #define read_c0_watchhi5() __read_32bit_c0_register($19, 5) | |
1713 | #define read_c0_watchhi6() __read_32bit_c0_register($19, 6) | |
1714 | #define read_c0_watchhi7() __read_32bit_c0_register($19, 7) | |
1715 | ||
1716 | #define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val) | |
1717 | #define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val) | |
1718 | #define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val) | |
1719 | #define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val) | |
1720 | #define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val) | |
1721 | #define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val) | |
1722 | #define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val) | |
1723 | #define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val) | |
1724 | ||
1725 | #define read_c0_xcontext() __read_ulong_c0_register($20, 0) | |
1726 | #define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val) | |
1727 | ||
1728 | #define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20) | |
1729 | #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val) | |
1730 | ||
1731 | #define read_c0_framemask() __read_32bit_c0_register($21, 0) | |
70342287 | 1732 | #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val) |
1da177e4 | 1733 | |
1da177e4 LT |
1734 | #define read_c0_diag() __read_32bit_c0_register($22, 0) |
1735 | #define write_c0_diag(val) __write_32bit_c0_register($22, 0, val) | |
1736 | ||
8d5ded16 JK |
1737 | /* R10K CP0 Branch Diagnostic register is 64bits wide */ |
1738 | #define read_c0_r10k_diag() __read_64bit_c0_register($22, 0) | |
1739 | #define write_c0_r10k_diag(val) __write_64bit_c0_register($22, 0, val) | |
1740 | ||
1da177e4 LT |
1741 | #define read_c0_diag1() __read_32bit_c0_register($22, 1) |
1742 | #define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val) | |
1743 | ||
1744 | #define read_c0_diag2() __read_32bit_c0_register($22, 2) | |
1745 | #define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val) | |
1746 | ||
1747 | #define read_c0_diag3() __read_32bit_c0_register($22, 3) | |
1748 | #define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val) | |
1749 | ||
1750 | #define read_c0_diag4() __read_32bit_c0_register($22, 4) | |
1751 | #define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val) | |
1752 | ||
1753 | #define read_c0_diag5() __read_32bit_c0_register($22, 5) | |
1754 | #define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val) | |
1755 | ||
1756 | #define read_c0_debug() __read_32bit_c0_register($23, 0) | |
1757 | #define write_c0_debug(val) __write_32bit_c0_register($23, 0, val) | |
1758 | ||
1759 | #define read_c0_depc() __read_ulong_c0_register($24, 0) | |
1760 | #define write_c0_depc(val) __write_ulong_c0_register($24, 0, val) | |
1761 | ||
1762 | /* | |
1763 | * MIPS32 / MIPS64 performance counters | |
1764 | */ | |
1765 | #define read_c0_perfctrl0() __read_32bit_c0_register($25, 0) | |
70342287 | 1766 | #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val) |
1da177e4 | 1767 | #define read_c0_perfcntr0() __read_32bit_c0_register($25, 1) |
70342287 | 1768 | #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val) |
4d36f59d DD |
1769 | #define read_c0_perfcntr0_64() __read_64bit_c0_register($25, 1) |
1770 | #define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val) | |
1da177e4 | 1771 | #define read_c0_perfctrl1() __read_32bit_c0_register($25, 2) |
70342287 | 1772 | #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val) |
1da177e4 | 1773 | #define read_c0_perfcntr1() __read_32bit_c0_register($25, 3) |
70342287 | 1774 | #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val) |
4d36f59d DD |
1775 | #define read_c0_perfcntr1_64() __read_64bit_c0_register($25, 3) |
1776 | #define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val) | |
1da177e4 | 1777 | #define read_c0_perfctrl2() __read_32bit_c0_register($25, 4) |
70342287 | 1778 | #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val) |
1da177e4 | 1779 | #define read_c0_perfcntr2() __read_32bit_c0_register($25, 5) |
70342287 | 1780 | #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val) |
4d36f59d DD |
1781 | #define read_c0_perfcntr2_64() __read_64bit_c0_register($25, 5) |
1782 | #define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val) | |
1da177e4 | 1783 | #define read_c0_perfctrl3() __read_32bit_c0_register($25, 6) |
70342287 | 1784 | #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val) |
1da177e4 | 1785 | #define read_c0_perfcntr3() __read_32bit_c0_register($25, 7) |
70342287 | 1786 | #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val) |
4d36f59d DD |
1787 | #define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7) |
1788 | #define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val) | |
1da177e4 | 1789 | |
1da177e4 LT |
1790 | #define read_c0_ecc() __read_32bit_c0_register($26, 0) |
1791 | #define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val) | |
1792 | ||
1793 | #define read_c0_derraddr0() __read_ulong_c0_register($26, 1) | |
70342287 | 1794 | #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val) |
1da177e4 LT |
1795 | |
1796 | #define read_c0_cacheerr() __read_32bit_c0_register($27, 0) | |
1797 | ||
1798 | #define read_c0_derraddr1() __read_ulong_c0_register($27, 1) | |
70342287 | 1799 | #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val) |
1da177e4 LT |
1800 | |
1801 | #define read_c0_taglo() __read_32bit_c0_register($28, 0) | |
1802 | #define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val) | |
1803 | ||
41c594ab RB |
1804 | #define read_c0_dtaglo() __read_32bit_c0_register($28, 2) |
1805 | #define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val) | |
1806 | ||
af231172 KC |
1807 | #define read_c0_ddatalo() __read_32bit_c0_register($28, 3) |
1808 | #define write_c0_ddatalo(val) __write_32bit_c0_register($28, 3, val) | |
1809 | ||
1810 | #define read_c0_staglo() __read_32bit_c0_register($28, 4) | |
1811 | #define write_c0_staglo(val) __write_32bit_c0_register($28, 4, val) | |
1812 | ||
1da177e4 LT |
1813 | #define read_c0_taghi() __read_32bit_c0_register($29, 0) |
1814 | #define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val) | |
1815 | ||
1816 | #define read_c0_errorepc() __read_ulong_c0_register($30, 0) | |
1817 | #define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val) | |
1818 | ||
7a0fc58c | 1819 | /* MIPSR2 */ |
21a151d8 | 1820 | #define read_c0_hwrena() __read_32bit_c0_register($7, 0) |
7a0fc58c RB |
1821 | #define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val) |
1822 | ||
1823 | #define read_c0_intctl() __read_32bit_c0_register($12, 1) | |
1824 | #define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val) | |
1825 | ||
1826 | #define read_c0_srsctl() __read_32bit_c0_register($12, 2) | |
1827 | #define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val) | |
1828 | ||
1829 | #define read_c0_srsmap() __read_32bit_c0_register($12, 3) | |
1830 | #define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val) | |
1831 | ||
21a151d8 | 1832 | #define read_c0_ebase() __read_32bit_c0_register($15, 1) |
7a0fc58c RB |
1833 | #define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) |
1834 | ||
37fb60f8 JH |
1835 | #define read_c0_ebase_64() __read_64bit_c0_register($15, 1) |
1836 | #define write_c0_ebase_64(val) __write_64bit_c0_register($15, 1, val) | |
1837 | ||
9b3274bd JH |
1838 | #define read_c0_cdmmbase() __read_ulong_c0_register($15, 2) |
1839 | #define write_c0_cdmmbase(val) __write_ulong_c0_register($15, 2, val) | |
1840 | ||
4a0156fb SH |
1841 | /* MIPSR3 */ |
1842 | #define read_c0_segctl0() __read_32bit_c0_register($5, 2) | |
1843 | #define write_c0_segctl0(val) __write_32bit_c0_register($5, 2, val) | |
1844 | ||
1845 | #define read_c0_segctl1() __read_32bit_c0_register($5, 3) | |
1846 | #define write_c0_segctl1(val) __write_32bit_c0_register($5, 3, val) | |
1847 | ||
1848 | #define read_c0_segctl2() __read_32bit_c0_register($5, 4) | |
1849 | #define write_c0_segctl2(val) __write_32bit_c0_register($5, 4, val) | |
ed918c2d | 1850 | |
87d08bc9 MC |
1851 | /* Hardware Page Table Walker */ |
1852 | #define read_c0_pwbase() __read_ulong_c0_register($5, 5) | |
1853 | #define write_c0_pwbase(val) __write_ulong_c0_register($5, 5, val) | |
1854 | ||
1855 | #define read_c0_pwfield() __read_ulong_c0_register($5, 6) | |
1856 | #define write_c0_pwfield(val) __write_ulong_c0_register($5, 6, val) | |
1857 | ||
1858 | #define read_c0_pwsize() __read_ulong_c0_register($5, 7) | |
1859 | #define write_c0_pwsize(val) __write_ulong_c0_register($5, 7, val) | |
1860 | ||
1861 | #define read_c0_pwctl() __read_32bit_c0_register($6, 6) | |
1862 | #define write_c0_pwctl(val) __write_32bit_c0_register($6, 6, val) | |
1863 | ||
380cd582 HC |
1864 | #define read_c0_pgd() __read_64bit_c0_register($9, 7) |
1865 | #define write_c0_pgd(val) __write_64bit_c0_register($9, 7, val) | |
1866 | ||
1867 | #define read_c0_kpgd() __read_64bit_c0_register($31, 7) | |
1868 | #define write_c0_kpgd(val) __write_64bit_c0_register($31, 7, val) | |
1869 | ||
ed918c2d DD |
1870 | /* Cavium OCTEON (cnMIPS) */ |
1871 | #define read_c0_cvmcount() __read_ulong_c0_register($9, 6) | |
1872 | #define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val) | |
1873 | ||
1874 | #define read_c0_cvmctl() __read_64bit_c0_register($9, 7) | |
1875 | #define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val) | |
1876 | ||
1877 | #define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7) | |
70342287 | 1878 | #define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val) |
7d8a528d JH |
1879 | |
1880 | #define read_c0_cvmmemctl2() __read_64bit_c0_register($16, 6) | |
1881 | #define write_c0_cvmmemctl2(val) __write_64bit_c0_register($16, 6, val) | |
1882 | ||
1883 | #define read_c0_cvmvmconfig() __read_64bit_c0_register($16, 7) | |
1884 | #define write_c0_cvmvmconfig(val) __write_64bit_c0_register($16, 7, val) | |
1885 | ||
ed918c2d | 1886 | /* |
70342287 | 1887 | * The cacheerr registers are not standardized. On OCTEON, they are |
ed918c2d DD |
1888 | * 64 bits wide. |
1889 | */ | |
1890 | #define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0) | |
1891 | #define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val) | |
1892 | ||
1893 | #define read_octeon_c0_dcacheerr() __read_64bit_c0_register($27, 1) | |
1894 | #define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val) | |
1895 | ||
af231172 KC |
1896 | /* BMIPS3300 */ |
1897 | #define read_c0_brcm_config_0() __read_32bit_c0_register($22, 0) | |
1898 | #define write_c0_brcm_config_0(val) __write_32bit_c0_register($22, 0, val) | |
1899 | ||
1900 | #define read_c0_brcm_bus_pll() __read_32bit_c0_register($22, 4) | |
1901 | #define write_c0_brcm_bus_pll(val) __write_32bit_c0_register($22, 4, val) | |
1902 | ||
1903 | #define read_c0_brcm_reset() __read_32bit_c0_register($22, 5) | |
1904 | #define write_c0_brcm_reset(val) __write_32bit_c0_register($22, 5, val) | |
1905 | ||
020232f1 | 1906 | /* BMIPS43xx */ |
af231172 KC |
1907 | #define read_c0_brcm_cmt_intr() __read_32bit_c0_register($22, 1) |
1908 | #define write_c0_brcm_cmt_intr(val) __write_32bit_c0_register($22, 1, val) | |
1909 | ||
1910 | #define read_c0_brcm_cmt_ctrl() __read_32bit_c0_register($22, 2) | |
1911 | #define write_c0_brcm_cmt_ctrl(val) __write_32bit_c0_register($22, 2, val) | |
1912 | ||
1913 | #define read_c0_brcm_cmt_local() __read_32bit_c0_register($22, 3) | |
1914 | #define write_c0_brcm_cmt_local(val) __write_32bit_c0_register($22, 3, val) | |
1915 | ||
1916 | #define read_c0_brcm_config_1() __read_32bit_c0_register($22, 5) | |
1917 | #define write_c0_brcm_config_1(val) __write_32bit_c0_register($22, 5, val) | |
1918 | ||
1919 | #define read_c0_brcm_cbr() __read_32bit_c0_register($22, 6) | |
1920 | #define write_c0_brcm_cbr(val) __write_32bit_c0_register($22, 6, val) | |
1921 | ||
1922 | /* BMIPS5000 */ | |
1923 | #define read_c0_brcm_config() __read_32bit_c0_register($22, 0) | |
1924 | #define write_c0_brcm_config(val) __write_32bit_c0_register($22, 0, val) | |
1925 | ||
1926 | #define read_c0_brcm_mode() __read_32bit_c0_register($22, 1) | |
1927 | #define write_c0_brcm_mode(val) __write_32bit_c0_register($22, 1, val) | |
1928 | ||
1929 | #define read_c0_brcm_action() __read_32bit_c0_register($22, 2) | |
1930 | #define write_c0_brcm_action(val) __write_32bit_c0_register($22, 2, val) | |
1931 | ||
1932 | #define read_c0_brcm_edsp() __read_32bit_c0_register($22, 3) | |
1933 | #define write_c0_brcm_edsp(val) __write_32bit_c0_register($22, 3, val) | |
1934 | ||
1935 | #define read_c0_brcm_bootvec() __read_32bit_c0_register($22, 4) | |
1936 | #define write_c0_brcm_bootvec(val) __write_32bit_c0_register($22, 4, val) | |
1937 | ||
1938 | #define read_c0_brcm_sleepcount() __read_32bit_c0_register($22, 7) | |
1939 | #define write_c0_brcm_sleepcount(val) __write_32bit_c0_register($22, 7, val) | |
1940 | ||
7eb91118 JH |
1941 | /* |
1942 | * Macros to access the guest system control coprocessor | |
1943 | */ | |
1944 | ||
00b4eb40 JH |
1945 | #ifndef TOOLCHAIN_SUPPORTS_VIRT |
1946 | _ASM_MACRO_2R_1S(mfgc0, rt, rs, sel, | |
1947 | _ASM_INSN_IF_MIPS(0x40600000 | __rt << 16 | __rs << 11 | \\sel) | |
1948 | _ASM_INSN32_IF_MM(0x000004fc | __rt << 21 | __rs << 16 | \\sel << 11)); | |
1949 | _ASM_MACRO_2R_1S(dmfgc0, rt, rs, sel, | |
1950 | _ASM_INSN_IF_MIPS(0x40600100 | __rt << 16 | __rs << 11 | \\sel) | |
1951 | _ASM_INSN32_IF_MM(0x580004fc | __rt << 21 | __rs << 16 | \\sel << 11)); | |
1952 | _ASM_MACRO_2R_1S(mtgc0, rt, rd, sel, | |
1953 | _ASM_INSN_IF_MIPS(0x40600200 | __rt << 16 | __rd << 11 | \\sel) | |
1954 | _ASM_INSN32_IF_MM(0x000006fc | __rt << 21 | __rd << 16 | \\sel << 11)); | |
1955 | _ASM_MACRO_2R_1S(dmtgc0, rt, rd, sel, | |
1956 | _ASM_INSN_IF_MIPS(0x40600300 | __rt << 16 | __rd << 11 | \\sel) | |
1957 | _ASM_INSN32_IF_MM(0x580006fc | __rt << 21 | __rd << 16 | \\sel << 11)); | |
1958 | _ASM_MACRO_0(tlbgp, _ASM_INSN_IF_MIPS(0x42000010) | |
1959 | _ASM_INSN32_IF_MM(0x0000017c)); | |
1960 | _ASM_MACRO_0(tlbgr, _ASM_INSN_IF_MIPS(0x42000009) | |
1961 | _ASM_INSN32_IF_MM(0x0000117c)); | |
1962 | _ASM_MACRO_0(tlbgwi, _ASM_INSN_IF_MIPS(0x4200000a) | |
1963 | _ASM_INSN32_IF_MM(0x0000217c)); | |
1964 | _ASM_MACRO_0(tlbgwr, _ASM_INSN_IF_MIPS(0x4200000e) | |
1965 | _ASM_INSN32_IF_MM(0x0000317c)); | |
1966 | _ASM_MACRO_0(tlbginvf, _ASM_INSN_IF_MIPS(0x4200000c) | |
1967 | _ASM_INSN32_IF_MM(0x0000517c)); | |
1968 | #define _ASM_SET_VIRT "" | |
1969 | #else /* !TOOLCHAIN_SUPPORTS_VIRT */ | |
1970 | #define _ASM_SET_VIRT ".set\tvirt\n\t" | |
1971 | #endif | |
bad50d79 | 1972 | |
7eb91118 JH |
1973 | #define __read_32bit_gc0_register(source, sel) \ |
1974 | ({ int __res; \ | |
1975 | __asm__ __volatile__( \ | |
1976 | ".set\tpush\n\t" \ | |
1977 | ".set\tmips32r2\n\t" \ | |
00b4eb40 | 1978 | _ASM_SET_VIRT \ |
ed21e007 | 1979 | "mfgc0\t%0, " #source ", %1\n\t" \ |
7eb91118 | 1980 | ".set\tpop" \ |
bad50d79 | 1981 | : "=r" (__res) \ |
ed21e007 | 1982 | : "i" (sel)); \ |
7eb91118 JH |
1983 | __res; \ |
1984 | }) | |
1985 | ||
1986 | #define __read_64bit_gc0_register(source, sel) \ | |
1987 | ({ unsigned long long __res; \ | |
1988 | __asm__ __volatile__( \ | |
1989 | ".set\tpush\n\t" \ | |
1990 | ".set\tmips64r2\n\t" \ | |
00b4eb40 | 1991 | _ASM_SET_VIRT \ |
ed21e007 | 1992 | "dmfgc0\t%0, " #source ", %1\n\t" \ |
7eb91118 | 1993 | ".set\tpop" \ |
bad50d79 | 1994 | : "=r" (__res) \ |
ed21e007 | 1995 | : "i" (sel)); \ |
7eb91118 JH |
1996 | __res; \ |
1997 | }) | |
1998 | ||
1999 | #define __write_32bit_gc0_register(register, sel, value) \ | |
2000 | do { \ | |
2001 | __asm__ __volatile__( \ | |
2002 | ".set\tpush\n\t" \ | |
2003 | ".set\tmips32r2\n\t" \ | |
00b4eb40 | 2004 | _ASM_SET_VIRT \ |
ed21e007 | 2005 | "mtgc0\t%z0, " #register ", %1\n\t" \ |
7eb91118 | 2006 | ".set\tpop" \ |
bad50d79 | 2007 | : : "Jr" ((unsigned int)(value)), \ |
ed21e007 | 2008 | "i" (sel)); \ |
7eb91118 JH |
2009 | } while (0) |
2010 | ||
2011 | #define __write_64bit_gc0_register(register, sel, value) \ | |
2012 | do { \ | |
2013 | __asm__ __volatile__( \ | |
2014 | ".set\tpush\n\t" \ | |
2015 | ".set\tmips64r2\n\t" \ | |
00b4eb40 | 2016 | _ASM_SET_VIRT \ |
ed21e007 | 2017 | "dmtgc0\t%z0, " #register ", %1\n\t" \ |
bad50d79 JH |
2018 | ".set\tpop" \ |
2019 | : : "Jr" (value), \ | |
ed21e007 | 2020 | "i" (sel)); \ |
bad50d79 JH |
2021 | } while (0) |
2022 | ||
7eb91118 JH |
2023 | #define __read_ulong_gc0_register(reg, sel) \ |
2024 | ((sizeof(unsigned long) == 4) ? \ | |
2025 | (unsigned long) __read_32bit_gc0_register(reg, sel) : \ | |
2026 | (unsigned long) __read_64bit_gc0_register(reg, sel)) | |
2027 | ||
2028 | #define __write_ulong_gc0_register(reg, sel, val) \ | |
2029 | do { \ | |
2030 | if (sizeof(unsigned long) == 4) \ | |
2031 | __write_32bit_gc0_register(reg, sel, val); \ | |
2032 | else \ | |
2033 | __write_64bit_gc0_register(reg, sel, val); \ | |
2034 | } while (0) | |
2035 | ||
ed21e007 JH |
2036 | #define read_gc0_index() __read_32bit_gc0_register($0, 0) |
2037 | #define write_gc0_index(val) __write_32bit_gc0_register($0, 0, val) | |
7eb91118 | 2038 | |
ed21e007 JH |
2039 | #define read_gc0_entrylo0() __read_ulong_gc0_register($2, 0) |
2040 | #define write_gc0_entrylo0(val) __write_ulong_gc0_register($2, 0, val) | |
7eb91118 | 2041 | |
ed21e007 JH |
2042 | #define read_gc0_entrylo1() __read_ulong_gc0_register($3, 0) |
2043 | #define write_gc0_entrylo1(val) __write_ulong_gc0_register($3, 0, val) | |
7eb91118 | 2044 | |
ed21e007 JH |
2045 | #define read_gc0_context() __read_ulong_gc0_register($4, 0) |
2046 | #define write_gc0_context(val) __write_ulong_gc0_register($4, 0, val) | |
7eb91118 | 2047 | |
ed21e007 JH |
2048 | #define read_gc0_contextconfig() __read_32bit_gc0_register($4, 1) |
2049 | #define write_gc0_contextconfig(val) __write_32bit_gc0_register($4, 1, val) | |
7eb91118 | 2050 | |
ed21e007 JH |
2051 | #define read_gc0_userlocal() __read_ulong_gc0_register($4, 2) |
2052 | #define write_gc0_userlocal(val) __write_ulong_gc0_register($4, 2, val) | |
7eb91118 | 2053 | |
ed21e007 JH |
2054 | #define read_gc0_xcontextconfig() __read_ulong_gc0_register($4, 3) |
2055 | #define write_gc0_xcontextconfig(val) __write_ulong_gc0_register($4, 3, val) | |
7eb91118 | 2056 | |
ed21e007 JH |
2057 | #define read_gc0_pagemask() __read_32bit_gc0_register($5, 0) |
2058 | #define write_gc0_pagemask(val) __write_32bit_gc0_register($5, 0, val) | |
7eb91118 | 2059 | |
ed21e007 JH |
2060 | #define read_gc0_pagegrain() __read_32bit_gc0_register($5, 1) |
2061 | #define write_gc0_pagegrain(val) __write_32bit_gc0_register($5, 1, val) | |
7eb91118 | 2062 | |
ed21e007 JH |
2063 | #define read_gc0_segctl0() __read_ulong_gc0_register($5, 2) |
2064 | #define write_gc0_segctl0(val) __write_ulong_gc0_register($5, 2, val) | |
7eb91118 | 2065 | |
ed21e007 JH |
2066 | #define read_gc0_segctl1() __read_ulong_gc0_register($5, 3) |
2067 | #define write_gc0_segctl1(val) __write_ulong_gc0_register($5, 3, val) | |
7eb91118 | 2068 | |
ed21e007 JH |
2069 | #define read_gc0_segctl2() __read_ulong_gc0_register($5, 4) |
2070 | #define write_gc0_segctl2(val) __write_ulong_gc0_register($5, 4, val) | |
bad50d79 | 2071 | |
ed21e007 JH |
2072 | #define read_gc0_pwbase() __read_ulong_gc0_register($5, 5) |
2073 | #define write_gc0_pwbase(val) __write_ulong_gc0_register($5, 5, val) | |
bad50d79 | 2074 | |
ed21e007 JH |
2075 | #define read_gc0_pwfield() __read_ulong_gc0_register($5, 6) |
2076 | #define write_gc0_pwfield(val) __write_ulong_gc0_register($5, 6, val) | |
bad50d79 | 2077 | |
ed21e007 JH |
2078 | #define read_gc0_pwsize() __read_ulong_gc0_register($5, 7) |
2079 | #define write_gc0_pwsize(val) __write_ulong_gc0_register($5, 7, val) | |
bad50d79 | 2080 | |
ed21e007 JH |
2081 | #define read_gc0_wired() __read_32bit_gc0_register($6, 0) |
2082 | #define write_gc0_wired(val) __write_32bit_gc0_register($6, 0, val) | |
bad50d79 | 2083 | |
ed21e007 JH |
2084 | #define read_gc0_pwctl() __read_32bit_gc0_register($6, 6) |
2085 | #define write_gc0_pwctl(val) __write_32bit_gc0_register($6, 6, val) | |
2086 | ||
2087 | #define read_gc0_hwrena() __read_32bit_gc0_register($7, 0) | |
2088 | #define write_gc0_hwrena(val) __write_32bit_gc0_register($7, 0, val) | |
2089 | ||
2090 | #define read_gc0_badvaddr() __read_ulong_gc0_register($8, 0) | |
2091 | #define write_gc0_badvaddr(val) __write_ulong_gc0_register($8, 0, val) | |
2092 | ||
2093 | #define read_gc0_badinstr() __read_32bit_gc0_register($8, 1) | |
2094 | #define write_gc0_badinstr(val) __write_32bit_gc0_register($8, 1, val) | |
2095 | ||
2096 | #define read_gc0_badinstrp() __read_32bit_gc0_register($8, 2) | |
2097 | #define write_gc0_badinstrp(val) __write_32bit_gc0_register($8, 2, val) | |
2098 | ||
2099 | #define read_gc0_count() __read_32bit_gc0_register($9, 0) | |
2100 | ||
2101 | #define read_gc0_entryhi() __read_ulong_gc0_register($10, 0) | |
2102 | #define write_gc0_entryhi(val) __write_ulong_gc0_register($10, 0, val) | |
2103 | ||
2104 | #define read_gc0_compare() __read_32bit_gc0_register($11, 0) | |
2105 | #define write_gc0_compare(val) __write_32bit_gc0_register($11, 0, val) | |
2106 | ||
2107 | #define read_gc0_status() __read_32bit_gc0_register($12, 0) | |
2108 | #define write_gc0_status(val) __write_32bit_gc0_register($12, 0, val) | |
2109 | ||
2110 | #define read_gc0_intctl() __read_32bit_gc0_register($12, 1) | |
2111 | #define write_gc0_intctl(val) __write_32bit_gc0_register($12, 1, val) | |
2112 | ||
2113 | #define read_gc0_cause() __read_32bit_gc0_register($13, 0) | |
2114 | #define write_gc0_cause(val) __write_32bit_gc0_register($13, 0, val) | |
2115 | ||
2116 | #define read_gc0_epc() __read_ulong_gc0_register($14, 0) | |
2117 | #define write_gc0_epc(val) __write_ulong_gc0_register($14, 0, val) | |
2118 | ||
2119 | #define read_gc0_prid() __read_32bit_gc0_register($15, 0) | |
2120 | ||
2121 | #define read_gc0_ebase() __read_32bit_gc0_register($15, 1) | |
2122 | #define write_gc0_ebase(val) __write_32bit_gc0_register($15, 1, val) | |
2123 | ||
2124 | #define read_gc0_ebase_64() __read_64bit_gc0_register($15, 1) | |
2125 | #define write_gc0_ebase_64(val) __write_64bit_gc0_register($15, 1, val) | |
2126 | ||
2127 | #define read_gc0_config() __read_32bit_gc0_register($16, 0) | |
2128 | #define read_gc0_config1() __read_32bit_gc0_register($16, 1) | |
2129 | #define read_gc0_config2() __read_32bit_gc0_register($16, 2) | |
2130 | #define read_gc0_config3() __read_32bit_gc0_register($16, 3) | |
2131 | #define read_gc0_config4() __read_32bit_gc0_register($16, 4) | |
2132 | #define read_gc0_config5() __read_32bit_gc0_register($16, 5) | |
2133 | #define read_gc0_config6() __read_32bit_gc0_register($16, 6) | |
2134 | #define read_gc0_config7() __read_32bit_gc0_register($16, 7) | |
2135 | #define write_gc0_config(val) __write_32bit_gc0_register($16, 0, val) | |
2136 | #define write_gc0_config1(val) __write_32bit_gc0_register($16, 1, val) | |
2137 | #define write_gc0_config2(val) __write_32bit_gc0_register($16, 2, val) | |
2138 | #define write_gc0_config3(val) __write_32bit_gc0_register($16, 3, val) | |
2139 | #define write_gc0_config4(val) __write_32bit_gc0_register($16, 4, val) | |
2140 | #define write_gc0_config5(val) __write_32bit_gc0_register($16, 5, val) | |
2141 | #define write_gc0_config6(val) __write_32bit_gc0_register($16, 6, val) | |
2142 | #define write_gc0_config7(val) __write_32bit_gc0_register($16, 7, val) | |
2143 | ||
2144 | #define read_gc0_lladdr() __read_ulong_gc0_register($17, 0) | |
2145 | #define write_gc0_lladdr(val) __write_ulong_gc0_register($17, 0, val) | |
2146 | ||
2147 | #define read_gc0_watchlo0() __read_ulong_gc0_register($18, 0) | |
2148 | #define read_gc0_watchlo1() __read_ulong_gc0_register($18, 1) | |
2149 | #define read_gc0_watchlo2() __read_ulong_gc0_register($18, 2) | |
2150 | #define read_gc0_watchlo3() __read_ulong_gc0_register($18, 3) | |
2151 | #define read_gc0_watchlo4() __read_ulong_gc0_register($18, 4) | |
2152 | #define read_gc0_watchlo5() __read_ulong_gc0_register($18, 5) | |
2153 | #define read_gc0_watchlo6() __read_ulong_gc0_register($18, 6) | |
2154 | #define read_gc0_watchlo7() __read_ulong_gc0_register($18, 7) | |
2155 | #define write_gc0_watchlo0(val) __write_ulong_gc0_register($18, 0, val) | |
2156 | #define write_gc0_watchlo1(val) __write_ulong_gc0_register($18, 1, val) | |
2157 | #define write_gc0_watchlo2(val) __write_ulong_gc0_register($18, 2, val) | |
2158 | #define write_gc0_watchlo3(val) __write_ulong_gc0_register($18, 3, val) | |
2159 | #define write_gc0_watchlo4(val) __write_ulong_gc0_register($18, 4, val) | |
2160 | #define write_gc0_watchlo5(val) __write_ulong_gc0_register($18, 5, val) | |
2161 | #define write_gc0_watchlo6(val) __write_ulong_gc0_register($18, 6, val) | |
2162 | #define write_gc0_watchlo7(val) __write_ulong_gc0_register($18, 7, val) | |
2163 | ||
2164 | #define read_gc0_watchhi0() __read_32bit_gc0_register($19, 0) | |
2165 | #define read_gc0_watchhi1() __read_32bit_gc0_register($19, 1) | |
2166 | #define read_gc0_watchhi2() __read_32bit_gc0_register($19, 2) | |
2167 | #define read_gc0_watchhi3() __read_32bit_gc0_register($19, 3) | |
2168 | #define read_gc0_watchhi4() __read_32bit_gc0_register($19, 4) | |
2169 | #define read_gc0_watchhi5() __read_32bit_gc0_register($19, 5) | |
2170 | #define read_gc0_watchhi6() __read_32bit_gc0_register($19, 6) | |
2171 | #define read_gc0_watchhi7() __read_32bit_gc0_register($19, 7) | |
2172 | #define write_gc0_watchhi0(val) __write_32bit_gc0_register($19, 0, val) | |
2173 | #define write_gc0_watchhi1(val) __write_32bit_gc0_register($19, 1, val) | |
2174 | #define write_gc0_watchhi2(val) __write_32bit_gc0_register($19, 2, val) | |
2175 | #define write_gc0_watchhi3(val) __write_32bit_gc0_register($19, 3, val) | |
2176 | #define write_gc0_watchhi4(val) __write_32bit_gc0_register($19, 4, val) | |
2177 | #define write_gc0_watchhi5(val) __write_32bit_gc0_register($19, 5, val) | |
2178 | #define write_gc0_watchhi6(val) __write_32bit_gc0_register($19, 6, val) | |
2179 | #define write_gc0_watchhi7(val) __write_32bit_gc0_register($19, 7, val) | |
2180 | ||
2181 | #define read_gc0_xcontext() __read_ulong_gc0_register($20, 0) | |
2182 | #define write_gc0_xcontext(val) __write_ulong_gc0_register($20, 0, val) | |
2183 | ||
2184 | #define read_gc0_perfctrl0() __read_32bit_gc0_register($25, 0) | |
2185 | #define write_gc0_perfctrl0(val) __write_32bit_gc0_register($25, 0, val) | |
2186 | #define read_gc0_perfcntr0() __read_32bit_gc0_register($25, 1) | |
2187 | #define write_gc0_perfcntr0(val) __write_32bit_gc0_register($25, 1, val) | |
2188 | #define read_gc0_perfcntr0_64() __read_64bit_gc0_register($25, 1) | |
2189 | #define write_gc0_perfcntr0_64(val) __write_64bit_gc0_register($25, 1, val) | |
2190 | #define read_gc0_perfctrl1() __read_32bit_gc0_register($25, 2) | |
2191 | #define write_gc0_perfctrl1(val) __write_32bit_gc0_register($25, 2, val) | |
2192 | #define read_gc0_perfcntr1() __read_32bit_gc0_register($25, 3) | |
2193 | #define write_gc0_perfcntr1(val) __write_32bit_gc0_register($25, 3, val) | |
2194 | #define read_gc0_perfcntr1_64() __read_64bit_gc0_register($25, 3) | |
2195 | #define write_gc0_perfcntr1_64(val) __write_64bit_gc0_register($25, 3, val) | |
2196 | #define read_gc0_perfctrl2() __read_32bit_gc0_register($25, 4) | |
2197 | #define write_gc0_perfctrl2(val) __write_32bit_gc0_register($25, 4, val) | |
2198 | #define read_gc0_perfcntr2() __read_32bit_gc0_register($25, 5) | |
2199 | #define write_gc0_perfcntr2(val) __write_32bit_gc0_register($25, 5, val) | |
2200 | #define read_gc0_perfcntr2_64() __read_64bit_gc0_register($25, 5) | |
2201 | #define write_gc0_perfcntr2_64(val) __write_64bit_gc0_register($25, 5, val) | |
2202 | #define read_gc0_perfctrl3() __read_32bit_gc0_register($25, 6) | |
2203 | #define write_gc0_perfctrl3(val) __write_32bit_gc0_register($25, 6, val) | |
2204 | #define read_gc0_perfcntr3() __read_32bit_gc0_register($25, 7) | |
2205 | #define write_gc0_perfcntr3(val) __write_32bit_gc0_register($25, 7, val) | |
2206 | #define read_gc0_perfcntr3_64() __read_64bit_gc0_register($25, 7) | |
2207 | #define write_gc0_perfcntr3_64(val) __write_64bit_gc0_register($25, 7, val) | |
2208 | ||
2209 | #define read_gc0_errorepc() __read_ulong_gc0_register($30, 0) | |
2210 | #define write_gc0_errorepc(val) __write_ulong_gc0_register($30, 0, val) | |
2211 | ||
2212 | #define read_gc0_kscratch1() __read_ulong_gc0_register($31, 2) | |
2213 | #define read_gc0_kscratch2() __read_ulong_gc0_register($31, 3) | |
2214 | #define read_gc0_kscratch3() __read_ulong_gc0_register($31, 4) | |
2215 | #define read_gc0_kscratch4() __read_ulong_gc0_register($31, 5) | |
2216 | #define read_gc0_kscratch5() __read_ulong_gc0_register($31, 6) | |
2217 | #define read_gc0_kscratch6() __read_ulong_gc0_register($31, 7) | |
2218 | #define write_gc0_kscratch1(val) __write_ulong_gc0_register($31, 2, val) | |
2219 | #define write_gc0_kscratch2(val) __write_ulong_gc0_register($31, 3, val) | |
2220 | #define write_gc0_kscratch3(val) __write_ulong_gc0_register($31, 4, val) | |
2221 | #define write_gc0_kscratch4(val) __write_ulong_gc0_register($31, 5, val) | |
2222 | #define write_gc0_kscratch5(val) __write_ulong_gc0_register($31, 6, val) | |
2223 | #define write_gc0_kscratch6(val) __write_ulong_gc0_register($31, 7, val) | |
7eb91118 | 2224 | |
7d8a528d | 2225 | /* Cavium OCTEON (cnMIPS) */ |
ed21e007 JH |
2226 | #define read_gc0_cvmcount() __read_ulong_gc0_register($9, 6) |
2227 | #define write_gc0_cvmcount(val) __write_ulong_gc0_register($9, 6, val) | |
7d8a528d | 2228 | |
ed21e007 JH |
2229 | #define read_gc0_cvmctl() __read_64bit_gc0_register($9, 7) |
2230 | #define write_gc0_cvmctl(val) __write_64bit_gc0_register($9, 7, val) | |
7d8a528d | 2231 | |
ed21e007 JH |
2232 | #define read_gc0_cvmmemctl() __read_64bit_gc0_register($11, 7) |
2233 | #define write_gc0_cvmmemctl(val) __write_64bit_gc0_register($11, 7, val) | |
7d8a528d | 2234 | |
ed21e007 JH |
2235 | #define read_gc0_cvmmemctl2() __read_64bit_gc0_register($16, 6) |
2236 | #define write_gc0_cvmmemctl2(val) __write_64bit_gc0_register($16, 6, val) | |
7d8a528d | 2237 | |
1da177e4 LT |
2238 | /* |
2239 | * Macros to access the floating point coprocessor control registers | |
2240 | */ | |
842dfc11 | 2241 | #define _read_32bit_cp1_register(source, gas_hardfloat) \ |
b9688310 | 2242 | ({ \ |
c46a2f01 | 2243 | unsigned int __res; \ |
b9688310 SH |
2244 | \ |
2245 | __asm__ __volatile__( \ | |
2246 | " .set push \n" \ | |
2247 | " .set reorder \n" \ | |
2248 | " # gas fails to assemble cfc1 for some archs, \n" \ | |
2249 | " # like Octeon. \n" \ | |
2250 | " .set mips1 \n" \ | |
842dfc11 | 2251 | " "STR(gas_hardfloat)" \n" \ |
b9688310 SH |
2252 | " cfc1 %0,"STR(source)" \n" \ |
2253 | " .set pop \n" \ | |
2254 | : "=r" (__res)); \ | |
2255 | __res; \ | |
2256 | }) | |
1da177e4 | 2257 | |
5e32033e JH |
2258 | #define _write_32bit_cp1_register(dest, val, gas_hardfloat) \ |
2259 | do { \ | |
2260 | __asm__ __volatile__( \ | |
2261 | " .set push \n" \ | |
2262 | " .set reorder \n" \ | |
2263 | " "STR(gas_hardfloat)" \n" \ | |
2264 | " ctc1 %0,"STR(dest)" \n" \ | |
2265 | " .set pop \n" \ | |
2266 | : : "r" (val)); \ | |
2267 | } while (0) | |
2268 | ||
842dfc11 ML |
2269 | #ifdef GAS_HAS_SET_HARDFLOAT |
2270 | #define read_32bit_cp1_register(source) \ | |
2271 | _read_32bit_cp1_register(source, .set hardfloat) | |
5e32033e JH |
2272 | #define write_32bit_cp1_register(dest, val) \ |
2273 | _write_32bit_cp1_register(dest, val, .set hardfloat) | |
842dfc11 ML |
2274 | #else |
2275 | #define read_32bit_cp1_register(source) \ | |
2276 | _read_32bit_cp1_register(source, ) | |
5e32033e JH |
2277 | #define write_32bit_cp1_register(dest, val) \ |
2278 | _write_32bit_cp1_register(dest, val, ) | |
842dfc11 ML |
2279 | #endif |
2280 | ||
32a7ede6 | 2281 | #ifdef HAVE_AS_DSP |
e50c0a8f RB |
2282 | #define rddsp(mask) \ |
2283 | ({ \ | |
32a7ede6 | 2284 | unsigned int __dspctl; \ |
e50c0a8f RB |
2285 | \ |
2286 | __asm__ __volatile__( \ | |
63c2b681 FF |
2287 | " .set push \n" \ |
2288 | " .set dsp \n" \ | |
32a7ede6 | 2289 | " rddsp %0, %x1 \n" \ |
63c2b681 | 2290 | " .set pop \n" \ |
32a7ede6 | 2291 | : "=r" (__dspctl) \ |
e50c0a8f | 2292 | : "i" (mask)); \ |
32a7ede6 | 2293 | __dspctl; \ |
e50c0a8f RB |
2294 | }) |
2295 | ||
2296 | #define wrdsp(val, mask) \ | |
2297 | do { \ | |
e50c0a8f | 2298 | __asm__ __volatile__( \ |
63c2b681 FF |
2299 | " .set push \n" \ |
2300 | " .set dsp \n" \ | |
32a7ede6 | 2301 | " wrdsp %0, %x1 \n" \ |
63c2b681 | 2302 | " .set pop \n" \ |
70342287 | 2303 | : \ |
e50c0a8f | 2304 | : "r" (val), "i" (mask)); \ |
e50c0a8f RB |
2305 | } while (0) |
2306 | ||
63c2b681 FF |
2307 | #define mflo0() \ |
2308 | ({ \ | |
2309 | long mflo0; \ | |
2310 | __asm__( \ | |
2311 | " .set push \n" \ | |
2312 | " .set dsp \n" \ | |
2313 | " mflo %0, $ac0 \n" \ | |
2314 | " .set pop \n" \ | |
2315 | : "=r" (mflo0)); \ | |
2316 | mflo0; \ | |
2317 | }) | |
2318 | ||
2319 | #define mflo1() \ | |
2320 | ({ \ | |
2321 | long mflo1; \ | |
2322 | __asm__( \ | |
2323 | " .set push \n" \ | |
2324 | " .set dsp \n" \ | |
2325 | " mflo %0, $ac1 \n" \ | |
2326 | " .set pop \n" \ | |
2327 | : "=r" (mflo1)); \ | |
2328 | mflo1; \ | |
2329 | }) | |
2330 | ||
2331 | #define mflo2() \ | |
2332 | ({ \ | |
2333 | long mflo2; \ | |
2334 | __asm__( \ | |
2335 | " .set push \n" \ | |
2336 | " .set dsp \n" \ | |
2337 | " mflo %0, $ac2 \n" \ | |
2338 | " .set pop \n" \ | |
2339 | : "=r" (mflo2)); \ | |
2340 | mflo2; \ | |
2341 | }) | |
2342 | ||
2343 | #define mflo3() \ | |
2344 | ({ \ | |
2345 | long mflo3; \ | |
2346 | __asm__( \ | |
2347 | " .set push \n" \ | |
2348 | " .set dsp \n" \ | |
2349 | " mflo %0, $ac3 \n" \ | |
2350 | " .set pop \n" \ | |
2351 | : "=r" (mflo3)); \ | |
2352 | mflo3; \ | |
2353 | }) | |
2354 | ||
2355 | #define mfhi0() \ | |
2356 | ({ \ | |
2357 | long mfhi0; \ | |
2358 | __asm__( \ | |
2359 | " .set push \n" \ | |
2360 | " .set dsp \n" \ | |
2361 | " mfhi %0, $ac0 \n" \ | |
2362 | " .set pop \n" \ | |
2363 | : "=r" (mfhi0)); \ | |
2364 | mfhi0; \ | |
2365 | }) | |
2366 | ||
2367 | #define mfhi1() \ | |
2368 | ({ \ | |
2369 | long mfhi1; \ | |
2370 | __asm__( \ | |
2371 | " .set push \n" \ | |
2372 | " .set dsp \n" \ | |
2373 | " mfhi %0, $ac1 \n" \ | |
2374 | " .set pop \n" \ | |
2375 | : "=r" (mfhi1)); \ | |
2376 | mfhi1; \ | |
2377 | }) | |
2378 | ||
2379 | #define mfhi2() \ | |
2380 | ({ \ | |
2381 | long mfhi2; \ | |
2382 | __asm__( \ | |
2383 | " .set push \n" \ | |
2384 | " .set dsp \n" \ | |
2385 | " mfhi %0, $ac2 \n" \ | |
2386 | " .set pop \n" \ | |
2387 | : "=r" (mfhi2)); \ | |
2388 | mfhi2; \ | |
2389 | }) | |
2390 | ||
2391 | #define mfhi3() \ | |
2392 | ({ \ | |
2393 | long mfhi3; \ | |
2394 | __asm__( \ | |
2395 | " .set push \n" \ | |
2396 | " .set dsp \n" \ | |
2397 | " mfhi %0, $ac3 \n" \ | |
2398 | " .set pop \n" \ | |
2399 | : "=r" (mfhi3)); \ | |
2400 | mfhi3; \ | |
2401 | }) | |
2402 | ||
2403 | ||
2404 | #define mtlo0(x) \ | |
2405 | ({ \ | |
2406 | __asm__( \ | |
2407 | " .set push \n" \ | |
2408 | " .set dsp \n" \ | |
2409 | " mtlo %0, $ac0 \n" \ | |
2410 | " .set pop \n" \ | |
2411 | : \ | |
2412 | : "r" (x)); \ | |
2413 | }) | |
2414 | ||
2415 | #define mtlo1(x) \ | |
2416 | ({ \ | |
2417 | __asm__( \ | |
2418 | " .set push \n" \ | |
2419 | " .set dsp \n" \ | |
2420 | " mtlo %0, $ac1 \n" \ | |
2421 | " .set pop \n" \ | |
2422 | : \ | |
2423 | : "r" (x)); \ | |
2424 | }) | |
2425 | ||
2426 | #define mtlo2(x) \ | |
2427 | ({ \ | |
2428 | __asm__( \ | |
2429 | " .set push \n" \ | |
2430 | " .set dsp \n" \ | |
2431 | " mtlo %0, $ac2 \n" \ | |
2432 | " .set pop \n" \ | |
2433 | : \ | |
2434 | : "r" (x)); \ | |
2435 | }) | |
2436 | ||
2437 | #define mtlo3(x) \ | |
2438 | ({ \ | |
2439 | __asm__( \ | |
2440 | " .set push \n" \ | |
2441 | " .set dsp \n" \ | |
2442 | " mtlo %0, $ac3 \n" \ | |
2443 | " .set pop \n" \ | |
2444 | : \ | |
2445 | : "r" (x)); \ | |
2446 | }) | |
2447 | ||
2448 | #define mthi0(x) \ | |
2449 | ({ \ | |
2450 | __asm__( \ | |
2451 | " .set push \n" \ | |
2452 | " .set dsp \n" \ | |
2453 | " mthi %0, $ac0 \n" \ | |
2454 | " .set pop \n" \ | |
2455 | : \ | |
2456 | : "r" (x)); \ | |
2457 | }) | |
2458 | ||
2459 | #define mthi1(x) \ | |
2460 | ({ \ | |
2461 | __asm__( \ | |
2462 | " .set push \n" \ | |
2463 | " .set dsp \n" \ | |
2464 | " mthi %0, $ac1 \n" \ | |
2465 | " .set pop \n" \ | |
2466 | : \ | |
2467 | : "r" (x)); \ | |
2468 | }) | |
2469 | ||
2470 | #define mthi2(x) \ | |
2471 | ({ \ | |
2472 | __asm__( \ | |
2473 | " .set push \n" \ | |
2474 | " .set dsp \n" \ | |
2475 | " mthi %0, $ac2 \n" \ | |
2476 | " .set pop \n" \ | |
2477 | : \ | |
2478 | : "r" (x)); \ | |
2479 | }) | |
2480 | ||
2481 | #define mthi3(x) \ | |
2482 | ({ \ | |
2483 | __asm__( \ | |
2484 | " .set push \n" \ | |
2485 | " .set dsp \n" \ | |
2486 | " mthi %0, $ac3 \n" \ | |
2487 | " .set pop \n" \ | |
2488 | : \ | |
2489 | : "r" (x)); \ | |
2490 | }) | |
e50c0a8f RB |
2491 | |
2492 | #else | |
2493 | ||
d0c1b478 | 2494 | #define rddsp(mask) \ |
e50c0a8f | 2495 | ({ \ |
d0c1b478 | 2496 | unsigned int __res; \ |
e50c0a8f RB |
2497 | \ |
2498 | __asm__ __volatile__( \ | |
e50c0a8f RB |
2499 | " .set push \n" \ |
2500 | " .set noat \n" \ | |
d0c1b478 | 2501 | " # rddsp $1, %x1 \n" \ |
5aadab0c JH |
2502 | _ASM_INSN_IF_MIPS(0x7c000cb8 | (%x1 << 16)) \ |
2503 | _ASM_INSN32_IF_MM(0x0020067c | (%x1 << 14)) \ | |
d0c1b478 | 2504 | " move %0, $1 \n" \ |
e50c0a8f | 2505 | " .set pop \n" \ |
d0c1b478 SH |
2506 | : "=r" (__res) \ |
2507 | : "i" (mask)); \ | |
2508 | __res; \ | |
2509 | }) | |
e50c0a8f | 2510 | |
d0c1b478 | 2511 | #define wrdsp(val, mask) \ |
e50c0a8f RB |
2512 | do { \ |
2513 | __asm__ __volatile__( \ | |
2514 | " .set push \n" \ | |
2515 | " .set noat \n" \ | |
2516 | " move $1, %0 \n" \ | |
d0c1b478 | 2517 | " # wrdsp $1, %x1 \n" \ |
5aadab0c JH |
2518 | _ASM_INSN_IF_MIPS(0x7c2004f8 | (%x1 << 11)) \ |
2519 | _ASM_INSN32_IF_MM(0x0020167c | (%x1 << 14)) \ | |
e50c0a8f RB |
2520 | " .set pop \n" \ |
2521 | : \ | |
d0c1b478 | 2522 | : "r" (val), "i" (mask)); \ |
e50c0a8f RB |
2523 | } while (0) |
2524 | ||
5aadab0c | 2525 | #define _dsp_mfxxx(ins) \ |
d0c1b478 SH |
2526 | ({ \ |
2527 | unsigned long __treg; \ | |
2528 | \ | |
e50c0a8f RB |
2529 | __asm__ __volatile__( \ |
2530 | " .set push \n" \ | |
2531 | " .set noat \n" \ | |
5aadab0c JH |
2532 | _ASM_INSN_IF_MIPS(0x00000810 | %X1) \ |
2533 | _ASM_INSN32_IF_MM(0x0001007c | %x1) \ | |
d0c1b478 | 2534 | " move %0, $1 \n" \ |
e50c0a8f | 2535 | " .set pop \n" \ |
d0c1b478 SH |
2536 | : "=r" (__treg) \ |
2537 | : "i" (ins)); \ | |
2538 | __treg; \ | |
2539 | }) | |
e50c0a8f | 2540 | |
5aadab0c | 2541 | #define _dsp_mtxxx(val, ins) \ |
e50c0a8f RB |
2542 | do { \ |
2543 | __asm__ __volatile__( \ | |
2544 | " .set push \n" \ | |
2545 | " .set noat \n" \ | |
2546 | " move $1, %0 \n" \ | |
5aadab0c JH |
2547 | _ASM_INSN_IF_MIPS(0x00200011 | %X1) \ |
2548 | _ASM_INSN32_IF_MM(0x0001207c | %x1) \ | |
e50c0a8f RB |
2549 | " .set pop \n" \ |
2550 | : \ | |
d0c1b478 | 2551 | : "r" (val), "i" (ins)); \ |
e50c0a8f RB |
2552 | } while (0) |
2553 | ||
5aadab0c | 2554 | #ifdef CONFIG_CPU_MICROMIPS |
d0c1b478 | 2555 | |
5aadab0c JH |
2556 | #define _dsp_mflo(reg) _dsp_mfxxx((reg << 14) | 0x1000) |
2557 | #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 14) | 0x0000) | |
d0c1b478 | 2558 | |
5aadab0c JH |
2559 | #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x1000)) |
2560 | #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x0000)) | |
d0c1b478 SH |
2561 | |
2562 | #else /* !CONFIG_CPU_MICROMIPS */ | |
e50c0a8f | 2563 | |
4cb764b4 SH |
2564 | #define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002) |
2565 | #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000) | |
e50c0a8f | 2566 | |
4cb764b4 SH |
2567 | #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002)) |
2568 | #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000)) | |
e50c0a8f | 2569 | |
5aadab0c JH |
2570 | #endif /* CONFIG_CPU_MICROMIPS */ |
2571 | ||
4cb764b4 SH |
2572 | #define mflo0() _dsp_mflo(0) |
2573 | #define mflo1() _dsp_mflo(1) | |
2574 | #define mflo2() _dsp_mflo(2) | |
2575 | #define mflo3() _dsp_mflo(3) | |
e50c0a8f | 2576 | |
4cb764b4 SH |
2577 | #define mfhi0() _dsp_mfhi(0) |
2578 | #define mfhi1() _dsp_mfhi(1) | |
2579 | #define mfhi2() _dsp_mfhi(2) | |
2580 | #define mfhi3() _dsp_mfhi(3) | |
e50c0a8f | 2581 | |
4cb764b4 SH |
2582 | #define mtlo0(x) _dsp_mtlo(x, 0) |
2583 | #define mtlo1(x) _dsp_mtlo(x, 1) | |
2584 | #define mtlo2(x) _dsp_mtlo(x, 2) | |
2585 | #define mtlo3(x) _dsp_mtlo(x, 3) | |
e50c0a8f | 2586 | |
4cb764b4 SH |
2587 | #define mthi0(x) _dsp_mthi(x, 0) |
2588 | #define mthi1(x) _dsp_mthi(x, 1) | |
2589 | #define mthi2(x) _dsp_mthi(x, 2) | |
2590 | #define mthi3(x) _dsp_mthi(x, 3) | |
e50c0a8f RB |
2591 | |
2592 | #endif | |
2593 | ||
1da177e4 LT |
2594 | /* |
2595 | * TLB operations. | |
2596 | * | |
2597 | * It is responsibility of the caller to take care of any TLB hazards. | |
2598 | */ | |
2599 | static inline void tlb_probe(void) | |
2600 | { | |
2601 | __asm__ __volatile__( | |
2602 | ".set noreorder\n\t" | |
2603 | "tlbp\n\t" | |
2604 | ".set reorder"); | |
2605 | } | |
2606 | ||
2607 | static inline void tlb_read(void) | |
2608 | { | |
9267a30d MSJ |
2609 | #if MIPS34K_MISSED_ITLB_WAR |
2610 | int res = 0; | |
2611 | ||
2612 | __asm__ __volatile__( | |
2613 | " .set push \n" | |
2614 | " .set noreorder \n" | |
2615 | " .set noat \n" | |
2616 | " .set mips32r2 \n" | |
2617 | " .word 0x41610001 # dvpe $1 \n" | |
2618 | " move %0, $1 \n" | |
2619 | " ehb \n" | |
2620 | " .set pop \n" | |
2621 | : "=r" (res)); | |
2622 | ||
2623 | instruction_hazard(); | |
2624 | #endif | |
2625 | ||
1da177e4 LT |
2626 | __asm__ __volatile__( |
2627 | ".set noreorder\n\t" | |
2628 | "tlbr\n\t" | |
2629 | ".set reorder"); | |
9267a30d MSJ |
2630 | |
2631 | #if MIPS34K_MISSED_ITLB_WAR | |
2632 | if ((res & _ULCAST_(1))) | |
2633 | __asm__ __volatile__( | |
2634 | " .set push \n" | |
2635 | " .set noreorder \n" | |
2636 | " .set noat \n" | |
2637 | " .set mips32r2 \n" | |
2638 | " .word 0x41600021 # evpe \n" | |
2639 | " ehb \n" | |
2640 | " .set pop \n"); | |
2641 | #endif | |
1da177e4 LT |
2642 | } |
2643 | ||
2644 | static inline void tlb_write_indexed(void) | |
2645 | { | |
2646 | __asm__ __volatile__( | |
2647 | ".set noreorder\n\t" | |
2648 | "tlbwi\n\t" | |
2649 | ".set reorder"); | |
2650 | } | |
2651 | ||
2652 | static inline void tlb_write_random(void) | |
2653 | { | |
2654 | __asm__ __volatile__( | |
2655 | ".set noreorder\n\t" | |
2656 | "tlbwr\n\t" | |
2657 | ".set reorder"); | |
2658 | } | |
2659 | ||
2660 | /* | |
7eb91118 JH |
2661 | * Guest TLB operations. |
2662 | * | |
2663 | * It is responsibility of the caller to take care of any TLB hazards. | |
2664 | */ | |
2665 | static inline void guest_tlb_probe(void) | |
2666 | { | |
2667 | __asm__ __volatile__( | |
2668 | ".set push\n\t" | |
2669 | ".set noreorder\n\t" | |
00b4eb40 | 2670 | _ASM_SET_VIRT |
7eb91118 JH |
2671 | "tlbgp\n\t" |
2672 | ".set pop"); | |
2673 | } | |
2674 | ||
2675 | static inline void guest_tlb_read(void) | |
2676 | { | |
2677 | __asm__ __volatile__( | |
2678 | ".set push\n\t" | |
2679 | ".set noreorder\n\t" | |
00b4eb40 | 2680 | _ASM_SET_VIRT |
7eb91118 JH |
2681 | "tlbgr\n\t" |
2682 | ".set pop"); | |
2683 | } | |
2684 | ||
2685 | static inline void guest_tlb_write_indexed(void) | |
2686 | { | |
2687 | __asm__ __volatile__( | |
2688 | ".set push\n\t" | |
2689 | ".set noreorder\n\t" | |
00b4eb40 | 2690 | _ASM_SET_VIRT |
7eb91118 JH |
2691 | "tlbgwi\n\t" |
2692 | ".set pop"); | |
2693 | } | |
2694 | ||
2695 | static inline void guest_tlb_write_random(void) | |
2696 | { | |
2697 | __asm__ __volatile__( | |
2698 | ".set push\n\t" | |
2699 | ".set noreorder\n\t" | |
00b4eb40 | 2700 | _ASM_SET_VIRT |
7eb91118 JH |
2701 | "tlbgwr\n\t" |
2702 | ".set pop"); | |
2703 | } | |
2704 | ||
2705 | /* | |
2706 | * Guest TLB Invalidate Flush | |
1da177e4 | 2707 | */ |
7eb91118 JH |
2708 | static inline void guest_tlbinvf(void) |
2709 | { | |
2710 | __asm__ __volatile__( | |
2711 | ".set push\n\t" | |
2712 | ".set noreorder\n\t" | |
00b4eb40 | 2713 | _ASM_SET_VIRT |
7eb91118 JH |
2714 | "tlbginvf\n\t" |
2715 | ".set pop"); | |
2716 | } | |
2717 | ||
2718 | /* | |
2719 | * Manipulate bits in a register. | |
2720 | */ | |
2721 | #define __BUILD_SET_COMMON(name) \ | |
1da177e4 | 2722 | static inline unsigned int \ |
7eb91118 | 2723 | set_##name(unsigned int set) \ |
1da177e4 | 2724 | { \ |
89e18eb3 | 2725 | unsigned int res, new; \ |
1da177e4 | 2726 | \ |
7eb91118 | 2727 | res = read_##name(); \ |
89e18eb3 | 2728 | new = res | set; \ |
7eb91118 | 2729 | write_##name(new); \ |
1da177e4 LT |
2730 | \ |
2731 | return res; \ | |
2732 | } \ | |
2733 | \ | |
2734 | static inline unsigned int \ | |
7eb91118 | 2735 | clear_##name(unsigned int clear) \ |
1da177e4 | 2736 | { \ |
89e18eb3 | 2737 | unsigned int res, new; \ |
1da177e4 | 2738 | \ |
7eb91118 | 2739 | res = read_##name(); \ |
89e18eb3 | 2740 | new = res & ~clear; \ |
7eb91118 | 2741 | write_##name(new); \ |
1da177e4 LT |
2742 | \ |
2743 | return res; \ | |
2744 | } \ | |
2745 | \ | |
2746 | static inline unsigned int \ | |
7eb91118 | 2747 | change_##name(unsigned int change, unsigned int val) \ |
1da177e4 | 2748 | { \ |
89e18eb3 | 2749 | unsigned int res, new; \ |
1da177e4 | 2750 | \ |
7eb91118 | 2751 | res = read_##name(); \ |
89e18eb3 RB |
2752 | new = res & ~change; \ |
2753 | new |= (val & change); \ | |
7eb91118 | 2754 | write_##name(new); \ |
1da177e4 LT |
2755 | \ |
2756 | return res; \ | |
2757 | } | |
2758 | ||
7eb91118 JH |
2759 | /* |
2760 | * Manipulate bits in a c0 register. | |
2761 | */ | |
2762 | #define __BUILD_SET_C0(name) __BUILD_SET_COMMON(c0_##name) | |
2763 | ||
1da177e4 LT |
2764 | __BUILD_SET_C0(status) |
2765 | __BUILD_SET_C0(cause) | |
2766 | __BUILD_SET_C0(config) | |
7f65afb9 | 2767 | __BUILD_SET_C0(config5) |
1da177e4 | 2768 | __BUILD_SET_C0(intcontrol) |
7a0fc58c RB |
2769 | __BUILD_SET_C0(intctl) |
2770 | __BUILD_SET_C0(srsmap) | |
a5770df0 | 2771 | __BUILD_SET_C0(pagegrain) |
f913e9ea JH |
2772 | __BUILD_SET_C0(guestctl0) |
2773 | __BUILD_SET_C0(guestctl0ext) | |
2774 | __BUILD_SET_C0(guestctl1) | |
2775 | __BUILD_SET_C0(guestctl2) | |
2776 | __BUILD_SET_C0(guestctl3) | |
020232f1 KC |
2777 | __BUILD_SET_C0(brcm_config_0) |
2778 | __BUILD_SET_C0(brcm_bus_pll) | |
2779 | __BUILD_SET_C0(brcm_reset) | |
2780 | __BUILD_SET_C0(brcm_cmt_intr) | |
2781 | __BUILD_SET_C0(brcm_cmt_ctrl) | |
2782 | __BUILD_SET_C0(brcm_config) | |
2783 | __BUILD_SET_C0(brcm_mode) | |
1da177e4 | 2784 | |
7eb91118 JH |
2785 | /* |
2786 | * Manipulate bits in a guest c0 register. | |
2787 | */ | |
2788 | #define __BUILD_SET_GC0(name) __BUILD_SET_COMMON(gc0_##name) | |
2789 | ||
eb0bab38 | 2790 | __BUILD_SET_GC0(wired) |
7eb91118 JH |
2791 | __BUILD_SET_GC0(status) |
2792 | __BUILD_SET_GC0(cause) | |
2793 | __BUILD_SET_GC0(ebase) | |
eb0bab38 | 2794 | __BUILD_SET_GC0(config1) |
7eb91118 | 2795 | |
45b585c8 DD |
2796 | /* |
2797 | * Return low 10 bits of ebase. | |
2798 | * Note that under KVM (MIPSVZ) this returns vcpu id. | |
2799 | */ | |
2800 | static inline unsigned int get_ebase_cpunum(void) | |
2801 | { | |
37af2f30 | 2802 | return read_c0_ebase() & MIPS_EBASE_CPUNUM; |
45b585c8 DD |
2803 | } |
2804 | ||
1da177e4 LT |
2805 | #endif /* !__ASSEMBLY__ */ |
2806 | ||
2807 | #endif /* _ASM_MIPSREGS_H */ |