[linux-2.6-block.git] / arch / arm64 / mm / proc.S

/*
 * Based on arch/arm/mm/proc.S
 *
 * Copyright (C) 2001 Deep Blue Solutions Ltd.
 * Copyright (C) 2012 ARM Ltd.
 * Author: Catalin Marinas <catalin.marinas@arm.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/init.h>
#include <linux/linkage.h>
#include <asm/assembler.h>
#include <asm/asm-offsets.h>
#include <asm/hwcap.h>
#include <asm/pgtable.h>
#include <asm/pgtable-hwdef.h>
#include <asm/cpufeature.h>
#include <asm/alternative.h>

#ifdef CONFIG_ARM64_64K_PAGES
#define TCR_TG_FLAGS	TCR_TG0_64K | TCR_TG1_64K
#elif defined(CONFIG_ARM64_16K_PAGES)
#define TCR_TG_FLAGS	TCR_TG0_16K | TCR_TG1_16K
#else /* CONFIG_ARM64_4K_PAGES */
#define TCR_TG_FLAGS	TCR_TG0_4K | TCR_TG1_4K
#endif

#define TCR_SMP_FLAGS	TCR_SHARED

/* PTWs cacheable, inner/outer WBWA */
#define TCR_CACHE_FLAGS	TCR_IRGN_WBWA | TCR_ORGN_WBWA

#define MAIR(attr, mt)	((attr) << ((mt) * 8))

/*
 *	cpu_do_idle()
 *
 *	Idle the processor (wait for interrupt).
 */
ENTRY(cpu_do_idle)
	dsb	sy				// WFI may enter a low-power mode
	wfi
	ret
ENDPROC(cpu_do_idle)

#ifdef CONFIG_CPU_PM
/**
 * cpu_do_suspend - save CPU registers context
 *
 * x0: virtual address of context pointer
 */
ENTRY(cpu_do_suspend)
	mrs	x2, tpidr_el0
	mrs	x3, tpidrro_el0
	mrs	x4, contextidr_el1
	mrs	x5, cpacr_el1
	mrs	x6, tcr_el1
	mrs	x7, vbar_el1
	mrs	x8, mdscr_el1
	mrs	x9, oslsr_el1
	mrs	x10, sctlr_el1
	stp	x2, x3, [x0]
	stp	x4, xzr, [x0, #16]
	stp	x5, x6, [x0, #32]
	stp	x7, x8, [x0, #48]
	stp	x9, x10, [x0, #64]
	ret
ENDPROC(cpu_do_suspend)

/**
 * cpu_do_resume - restore CPU register context
 *
 * x0: Address of context pointer
 */
ENTRY(cpu_do_resume)
	ldp	x2, x3, [x0]
	ldp	x4, x5, [x0, #16]
	ldp	x6, x8, [x0, #32]
	ldp	x9, x10, [x0, #48]
	ldp	x11, x12, [x0, #64]
	msr	tpidr_el0, x2
	msr	tpidrro_el0, x3
	msr	contextidr_el1, x4
	msr	cpacr_el1, x6

	/* Don't change t0sz here, mask those bits when restoring */
	mrs	x5, tcr_el1
	bfi	x8, x5, TCR_T0SZ_OFFSET, TCR_TxSZ_WIDTH

	msr	tcr_el1, x8
	msr	vbar_el1, x9
	msr	mdscr_el1, x10
	msr	sctlr_el1, x12
	/*
	 * Restore oslsr_el1 by writing oslar_el1
	 */
	ubfx	x11, x11, #1, #1
	msr	oslar_el1, x11
	reset_pmuserenr_el0 x0			// Disable PMU access from EL0
	isb
	ret
ENDPROC(cpu_do_resume)
#endif

/*
 *	cpu_do_switch_mm(pgd_phys, tsk)
 *
 *	Set the translation table base pointer to be pgd_phys.
 *
 *	- pgd_phys - physical address of new TTB
 */
ENTRY(cpu_do_switch_mm)
	mmid	x1, x1				// get mm->context.id
	bfi	x0, x1, #48, #16		// set the ASID
	msr	ttbr0_el1, x0			// set TTBR0
	isb
alternative_if_not ARM64_WORKAROUND_CAVIUM_27456
	ret
	nop
	nop
	nop
alternative_else
	ic	iallu
	dsb	nsh
	isb
	ret
alternative_endif
ENDPROC(cpu_do_switch_mm)

	.pushsection ".idmap.text", "ax"
/*
 * void idmap_cpu_replace_ttbr1(phys_addr_t new_pgd)
 *
 * This is the low-level counterpart to cpu_replace_ttbr1, and should not be
 * called by anything else. It can only be executed from a TTBR0 mapping.
 */
ENTRY(idmap_cpu_replace_ttbr1)
	mrs	x2, daif
	msr	daifset, #0xf

	adrp	x1, empty_zero_page
	msr	ttbr1_el1, x1
	isb

	tlbi	vmalle1
	dsb	nsh
	isb

	msr	ttbr1_el1, x0
	isb

	msr	daif, x2

	ret
ENDPROC(idmap_cpu_replace_ttbr1)
	.popsection

/*
 *	__cpu_setup
 *
 *	Initialise the processor for turning the MMU on.  Return in x0 the
 *	value of the SCTLR_EL1 register.
 */
ENTRY(__cpu_setup)
	tlbi	vmalle1				// Invalidate local TLB
	dsb	nsh

	mov	x0, #3 << 20
	msr	cpacr_el1, x0			// Enable FP/ASIMD
	mov	x0, #1 << 12			// Reset mdscr_el1 and disable
	msr	mdscr_el1, x0			// access to the DCC from EL0
	reset_pmuserenr_el0 x0			// Disable PMU access from EL0
	/*
	 * Memory region attributes for LPAE:
	 *
	 *   n = AttrIndx[2:0]
	 *			n	MAIR
	 *   DEVICE_nGnRnE	000	00000000
	 *   DEVICE_nGnRE	001	00000100
	 *   DEVICE_GRE		010	00001100
	 *   NORMAL_NC		011	01000100
	 *   NORMAL		100	11111111
	 *   NORMAL_WT		101	10111011
	 */
	ldr	x5, =MAIR(0x00, MT_DEVICE_nGnRnE) | \
		     MAIR(0x04, MT_DEVICE_nGnRE) | \
		     MAIR(0x0c, MT_DEVICE_GRE) | \
		     MAIR(0x44, MT_NORMAL_NC) | \
		     MAIR(0xff, MT_NORMAL) | \
		     MAIR(0xbb, MT_NORMAL_WT)
	msr	mair_el1, x5
	/*
	 * Prepare SCTLR
	 */
	adr	x5, crval
	ldp	w5, w6, [x5]
	mrs	x0, sctlr_el1
	bic	x0, x0, x5			// clear bits
	orr	x0, x0, x6			// set bits
	/*
	 * Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for
	 * both user and kernel.
	 */
	ldr	x10, =TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \
			TCR_TG_FLAGS | TCR_ASID16 | TCR_TBI0
	tcr_set_idmap_t0sz	x10, x9

	/*
	 * Read the PARange bits from ID_AA64MMFR0_EL1 and set the IPS bits in
	 * TCR_EL1.
	 */
	mrs	x9, ID_AA64MMFR0_EL1
	bfi	x10, x9, #32, #3
#ifdef CONFIG_ARM64_HW_AFDBM
	/*
	 * Hardware update of the Access and Dirty bits.
	 */
	mrs	x9, ID_AA64MMFR1_EL1
	and	x9, x9, #0xf
	cbz	x9, 2f
	cmp	x9, #2
	b.lt	1f
	orr	x10, x10, #TCR_HD		// hardware Dirty flag update
1:	orr	x10, x10, #TCR_HA		// hardware Access flag update
2:
#endif	/* CONFIG_ARM64_HW_AFDBM */
	msr	tcr_el1, x10
	ret					// return to head.S
ENDPROC(__cpu_setup)

	/*
	 * We set the desired value explicitly, including those of the
	 * reserved bits. The values of bits EE & E0E were set early in
	 * el2_setup, which are left untouched below.
	 *
	 *                 n n            T
	 *       U E      WT T UD     US IHBS
	 *       CE0      XWHW CZ     ME TEEA S
	 * .... .IEE .... NEAI TE.I ..AD DEN0 ACAM
	 * 0011 0... 1101 ..0. ..0. 10.. .0.. .... < hardware reserved
	 * .... .1.. .... 01.1 11.1 ..01 0.01 1101 < software settings
	 */
	.type	crval, #object
crval:
	.word	0xfcffffff			// clear
	.word	0x34d5d91d			// set
Commit	Line	Data
9cce7a43 CM	1	/*
	2	* Based on arch/arm/mm/proc.S
	3	*
	4	* Copyright (C) 2001 Deep Blue Solutions Ltd.
	5	* Copyright (C) 2012 ARM Ltd.
	6	* Author: Catalin Marinas <catalin.marinas@arm.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	19	*/
	20
	21	#include <linux/init.h>
	22	#include <linux/linkage.h>
	23	#include <asm/assembler.h>
	24	#include <asm/asm-offsets.h>
	25	#include <asm/hwcap.h>
9cce7a43	26	#include <asm/pgtable.h>
cabe1c81	27	#include <asm/pgtable-hwdef.h>
104a0c02 AP	28	#include <asm/cpufeature.h>
104a0c02 AP	29	#include <asm/alternative.h>
9cce7a43	30
35a86976 CM	31	#ifdef CONFIG_ARM64_64K_PAGES
35a86976 CM	32	#define TCR_TG_FLAGS TCR_TG0_64K \| TCR_TG1_64K
44eaacf1 SP	33	#elif defined(CONFIG_ARM64_16K_PAGES)
	34	#define TCR_TG_FLAGS TCR_TG0_16K \| TCR_TG1_16K
	35	#else /* CONFIG_ARM64_4K_PAGES */
35a86976 CM	36	#define TCR_TG_FLAGS TCR_TG0_4K \| TCR_TG1_4K
	37	#endif
	38
35a86976	39	#define TCR_SMP_FLAGS TCR_SHARED
9cce7a43	40
35a86976 CM	41	/* PTWs cacheable, inner/outer WBWA */
	42	#define TCR_CACHE_FLAGS TCR_IRGN_WBWA \| TCR_ORGN_WBWA
	43
9cce7a43 CM	44	#define MAIR(attr, mt) ((attr) << ((mt) * 8))
9cce7a43 CM	45
9cce7a43 CM	46	/*
	47	* cpu_do_idle()
	48	*
	49	* Idle the processor (wait for interrupt).
	50	*/
	51	ENTRY(cpu_do_idle)
	52	dsb sy // WFI may enter a low-power mode
	53	wfi
	54	ret
	55	ENDPROC(cpu_do_idle)
	56
af3cfdbf	57	#ifdef CONFIG_CPU_PM
6732bc65 LP	58	/**
	59	* cpu_do_suspend - save CPU registers context
	60	*
	61	* x0: virtual address of context pointer
	62	*/
	63	ENTRY(cpu_do_suspend)
	64	mrs x2, tpidr_el0
	65	mrs x3, tpidrro_el0
	66	mrs x4, contextidr_el1
cabe1c81 JM	67	mrs x5, cpacr_el1
	68	mrs x6, tcr_el1
	69	mrs x7, vbar_el1
	70	mrs x8, mdscr_el1
	71	mrs x9, oslsr_el1
	72	mrs x10, sctlr_el1
6732bc65	73	stp x2, x3, [x0]
cabe1c81 JM	74	stp x4, xzr, [x0, #16]
	75	stp x5, x6, [x0, #32]
	76	stp x7, x8, [x0, #48]
	77	stp x9, x10, [x0, #64]
6732bc65 LP	78	ret
	79	ENDPROC(cpu_do_suspend)
	80
	81	/**
	82	* cpu_do_resume - restore CPU register context
	83	*
cabe1c81	84	* x0: Address of context pointer
6732bc65 LP	85	*/
6732bc65 LP	86	ENTRY(cpu_do_resume)
6732bc65 LP	87	ldp x2, x3, [x0]
6732bc65 LP	88	ldp x4, x5, [x0, #16]
cabe1c81 JM	89	ldp x6, x8, [x0, #32]
	90	ldp x9, x10, [x0, #48]
	91	ldp x11, x12, [x0, #64]
6732bc65 LP	92	msr tpidr_el0, x2
	93	msr tpidrro_el0, x3
	94	msr contextidr_el1, x4
6732bc65	95	msr cpacr_el1, x6
cabe1c81 JM	96
	97	/* Don't change t0sz here, mask those bits when restoring */
	98	mrs x5, tcr_el1
	99	bfi x8, x5, TCR_T0SZ_OFFSET, TCR_TxSZ_WIDTH
	100
6732bc65 LP	101	msr tcr_el1, x8
	102	msr vbar_el1, x9
	103	msr mdscr_el1, x10
cabe1c81	104	msr sctlr_el1, x12
6732bc65 LP	105	/*
	106	* Restore oslsr_el1 by writing oslar_el1
	107	*/
	108	ubfx x11, x11, #1, #1
	109	msr oslar_el1, x11
f436b2ac	110	reset_pmuserenr_el0 x0 // Disable PMU access from EL0
6732bc65 LP	111	isb
	112	ret
	113	ENDPROC(cpu_do_resume)
	114	#endif
	115
9cce7a43	116	/*
812944e9	117	* cpu_do_switch_mm(pgd_phys, tsk)
9cce7a43 CM	118	*
	119	* Set the translation table base pointer to be pgd_phys.
	120	*
	121	* - pgd_phys - physical address of new TTB
	122	*/
	123	ENTRY(cpu_do_switch_mm)
5aec715d	124	mmid x1, x1 // get mm->context.id
9cce7a43 CM	125	bfi x0, x1, #48, #16 // set the ASID
	126	msr ttbr0_el1, x0 // set TTBR0
	127	isb
104a0c02	128	alternative_if_not ARM64_WORKAROUND_CAVIUM_27456
9cce7a43	129	ret
104a0c02 AP	130	nop
	131	nop
	132	nop
	133	alternative_else
	134	ic iallu
	135	dsb nsh
	136	isb
	137	ret
	138	alternative_endif
9cce7a43 CM	139	ENDPROC(cpu_do_switch_mm)
9cce7a43 CM	140
50e1881d MR	141	.pushsection ".idmap.text", "ax"
	142	/*
	143	* void idmap_cpu_replace_ttbr1(phys_addr_t new_pgd)
	144	*
	145	* This is the low-level counterpart to cpu_replace_ttbr1, and should not be
	146	* called by anything else. It can only be executed from a TTBR0 mapping.
	147	*/
	148	ENTRY(idmap_cpu_replace_ttbr1)
	149	mrs x2, daif
	150	msr daifset, #0xf
	151
	152	adrp x1, empty_zero_page
	153	msr ttbr1_el1, x1
	154	isb
	155
	156	tlbi vmalle1
	157	dsb nsh
	158	isb
	159
	160	msr ttbr1_el1, x0
	161	isb
	162
	163	msr daif, x2
	164
	165	ret
	166	ENDPROC(idmap_cpu_replace_ttbr1)
	167	.popsection
	168
9cce7a43 CM	169	/*
	170	* __cpu_setup
	171	*
	172	* Initialise the processor for turning the MMU on. Return in x0 the
	173	* value of the SCTLR_EL1 register.
	174	*/
	175	ENTRY(__cpu_setup)
fa7aae8a WD	176	tlbi vmalle1 // Invalidate local TLB
fa7aae8a WD	177	dsb nsh
9cce7a43 CM	178
	179	mov x0, #3 << 20
	180	msr cpacr_el1, x0 // Enable FP/ASIMD
d8d23fa0 WD	181	mov x0, #1 << 12 // Reset mdscr_el1 and disable
d8d23fa0 WD	182	msr mdscr_el1, x0 // access to the DCC from EL0
f436b2ac	183	reset_pmuserenr_el0 x0 // Disable PMU access from EL0
9cce7a43 CM	184	/*
	185	* Memory region attributes for LPAE:
	186	*
	187	* n = AttrIndx[2:0]
	188	* n MAIR
	189	* DEVICE_nGnRnE 000 00000000
	190	* DEVICE_nGnRE 001 00000100
	191	* DEVICE_GRE 010 00001100
	192	* NORMAL_NC 011 01000100
	193	* NORMAL 100 11111111
8d446c86	194	* NORMAL_WT 101 10111011
9cce7a43 CM	195	*/
	196	ldr x5, =MAIR(0x00, MT_DEVICE_nGnRnE) \| \
	197	MAIR(0x04, MT_DEVICE_nGnRE) \| \
	198	MAIR(0x0c, MT_DEVICE_GRE) \| \
	199	MAIR(0x44, MT_NORMAL_NC) \| \
8d446c86 JZZ	200	MAIR(0xff, MT_NORMAL) \| \
8d446c86 JZZ	201	MAIR(0xbb, MT_NORMAL_WT)
9cce7a43 CM	202	msr mair_el1, x5
	203	/*
	204	* Prepare SCTLR
	205	*/
	206	adr x5, crval
	207	ldp w5, w6, [x5]
	208	mrs x0, sctlr_el1
	209	bic x0, x0, x5 // clear bits
	210	orr x0, x0, x6 // set bits
	211	/*
	212	* Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for
	213	* both user and kernel.
	214	*/
35a86976 CM	215	ldr x10, =TCR_TxSZ(VA_BITS) \| TCR_CACHE_FLAGS \| TCR_SMP_FLAGS \| \
35a86976 CM	216	TCR_TG_FLAGS \| TCR_ASID16 \| TCR_TBI0
dd006da2 AB	217	tcr_set_idmap_t0sz x10, x9
dd006da2 AB	218
87366d8c RMC	219	/*
	220	* Read the PARange bits from ID_AA64MMFR0_EL1 and set the IPS bits in
	221	* TCR_EL1.
	222	*/
	223	mrs x9, ID_AA64MMFR0_EL1
	224	bfi x10, x9, #32, #3
2f4b829c CM	225	#ifdef CONFIG_ARM64_HW_AFDBM
	226	/*
	227	* Hardware update of the Access and Dirty bits.
	228	*/
	229	mrs x9, ID_AA64MMFR1_EL1
	230	and x9, x9, #0xf
	231	cbz x9, 2f
	232	cmp x9, #2
	233	b.lt 1f
	234	orr x10, x10, #TCR_HD // hardware Dirty flag update
	235	1: orr x10, x10, #TCR_HA // hardware Access flag update
	236	2:
	237	#endif /* CONFIG_ARM64_HW_AFDBM */
9cce7a43 CM	238	msr tcr_el1, x10
	239	ret // return to head.S
	240	ENDPROC(__cpu_setup)
	241
	242	/*
9f71ac96 SP	243	* We set the desired value explicitly, including those of the
	244	* reserved bits. The values of bits EE & E0E were set early in
	245	* el2_setup, which are left untouched below.
	246	*
9cce7a43 CM	247	* n n T
	248	* U E WT T UD US IHBS
	249	* CE0 XWHW CZ ME TEEA S
	250	* .... .IEE .... NEAI TE.I ..AD DEN0 ACAM
9f71ac96 SP	251	* 0011 0... 1101 ..0. ..0. 10.. .0.. .... < hardware reserved
9f71ac96 SP	252	* .... .1.. .... 01.1 11.1 ..01 0.01 1101 < software settings
9cce7a43 CM	253	*/
	254	.type crval, #object
	255	crval:
9f71ac96 SP	256	.word 0xfcffffff // clear
9f71ac96 SP	257	.word 0x34d5d91d // set