[linux-2.6-block.git] / arch / arm64 / include / asm / barrier.h

/*
 * Based on arch/arm/include/asm/barrier.h
 *
 * Copyright (C) 2012 ARM Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */
#ifndef __ASM_BARRIER_H
#define __ASM_BARRIER_H

#ifndef __ASSEMBLY__

#define sev()		asm volatile("sev" : : : "memory")
#define wfe()		asm volatile("wfe" : : : "memory")
#define wfi()		asm volatile("wfi" : : : "memory")

#define isb()		asm volatile("isb" : : : "memory")
#define dmb(opt)	asm volatile("dmb " #opt : : : "memory")
#define dsb(opt)	asm volatile("dsb " #opt : : : "memory")

#define mb()		dsb(sy)
#define rmb()		dsb(ld)
#define wmb()		dsb(st)

#define dma_rmb()	dmb(oshld)
#define dma_wmb()	dmb(oshst)

#ifndef CONFIG_SMP
#define smp_mb()	barrier()
#define smp_rmb()	barrier()
#define smp_wmb()	barrier()

#define smp_store_release(p, v)						\
do {									\
	compiletime_assert_atomic_type(*p);				\
	barrier();							\
	ACCESS_ONCE(*p) = (v);						\
} while (0)

#define smp_load_acquire(p)						\
({									\
	typeof(*p) ___p1 = ACCESS_ONCE(*p);				\
	compiletime_assert_atomic_type(*p);				\
	barrier();							\
	___p1;								\
})

#else

#define smp_mb()	dmb(ish)
#define smp_rmb()	dmb(ishld)
#define smp_wmb()	dmb(ishst)

#define smp_store_release(p, v)						\
do {									\
	compiletime_assert_atomic_type(*p);				\
	switch (sizeof(*p)) {						\
	case 1:								\
		asm volatile ("stlrb %w1, %0"				\
				: "=Q" (*p) : "r" (v) : "memory");	\
		break;							\
	case 2:								\
		asm volatile ("stlrh %w1, %0"				\
				: "=Q" (*p) : "r" (v) : "memory");	\
		break;							\
	case 4:								\
		asm volatile ("stlr %w1, %0"				\
				: "=Q" (*p) : "r" (v) : "memory");	\
		break;							\
	case 8:								\
		asm volatile ("stlr %1, %0"				\
				: "=Q" (*p) : "r" (v) : "memory");	\
		break;							\
	}								\
} while (0)

#define smp_load_acquire(p)						\
({									\
	typeof(*p) ___p1;						\
	compiletime_assert_atomic_type(*p);				\
	switch (sizeof(*p)) {						\
	case 1:								\
		asm volatile ("ldarb %w0, %1"				\
			: "=r" (___p1) : "Q" (*p) : "memory");		\
		break;							\
	case 2:								\
		asm volatile ("ldarh %w0, %1"				\
			: "=r" (___p1) : "Q" (*p) : "memory");		\
		break;							\
	case 4:								\
		asm volatile ("ldar %w0, %1"				\
			: "=r" (___p1) : "Q" (*p) : "memory");		\
		break;							\
	case 8:								\
		asm volatile ("ldar %0, %1"				\
			: "=r" (___p1) : "Q" (*p) : "memory");		\
		break;							\
	}								\
	___p1;								\
})

#endif

#define read_barrier_depends()		do { } while(0)
#define smp_read_barrier_depends()	do { } while(0)

#define set_mb(var, value)	do { var = value; smp_mb(); } while (0)
#define nop()		asm volatile("nop");

#define smp_mb__before_atomic()	smp_mb()
#define smp_mb__after_atomic()	smp_mb()

#endif	/* __ASSEMBLY__ */

#endif	/* __ASM_BARRIER_H */
Commit	Line	Data
10b663ae CM	1	/*
	2	* Based on arch/arm/include/asm/barrier.h
	3	*
	4	* Copyright (C) 2012 ARM Ltd.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	17	*/
	18	#ifndef __ASM_BARRIER_H
	19	#define __ASM_BARRIER_H
	20
	21	#ifndef __ASSEMBLY__
	22
	23	#define sev() asm volatile("sev" : : : "memory")
	24	#define wfe() asm volatile("wfe" : : : "memory")
	25	#define wfi() asm volatile("wfi" : : : "memory")
	26
	27	#define isb() asm volatile("isb" : : : "memory")
493e6874 WD	28	#define dmb(opt) asm volatile("dmb " #opt : : : "memory")
493e6874 WD	29	#define dsb(opt) asm volatile("dsb " #opt : : : "memory")
10b663ae	30
98f7685e	31	#define mb() dsb(sy)
493e6874 WD	32	#define rmb() dsb(ld)
493e6874 WD	33	#define wmb() dsb(st)
10b663ae	34
1077fa36 AD	35	#define dma_rmb() dmb(oshld)
	36	#define dma_wmb() dmb(oshst)
	37
10b663ae CM	38	#ifndef CONFIG_SMP
	39	#define smp_mb() barrier()
	40	#define smp_rmb() barrier()
	41	#define smp_wmb() barrier()
47933ad4 PZ	42
	43	#define smp_store_release(p, v) \
	44	do { \
	45	compiletime_assert_atomic_type(*p); \
be6209a6	46	barrier(); \
47933ad4 PZ	47	ACCESS_ONCE(*p) = (v); \
	48	} while (0)
	49
	50	#define smp_load_acquire(p) \
	51	({ \
	52	typeof(p) ___p1 = ACCESS_ONCE(p); \
	53	compiletime_assert_atomic_type(*p); \
be6209a6	54	barrier(); \
47933ad4 PZ	55	___p1; \
	56	})
	57
10b663ae	58	#else
47933ad4	59
493e6874 WD	60	#define smp_mb() dmb(ish)
	61	#define smp_rmb() dmb(ishld)
	62	#define smp_wmb() dmb(ishst)
47933ad4 PZ	63
	64	#define smp_store_release(p, v) \
	65	do { \
	66	compiletime_assert_atomic_type(*p); \
	67	switch (sizeof(*p)) { \
878a84d5 AP	68	case 1: \
	69	asm volatile ("stlrb %w1, %0" \
	70	: "=Q" (*p) : "r" (v) : "memory"); \
	71	break; \
	72	case 2: \
	73	asm volatile ("stlrh %w1, %0" \
	74	: "=Q" (*p) : "r" (v) : "memory"); \
	75	break; \
47933ad4 PZ	76	case 4: \
	77	asm volatile ("stlr %w1, %0" \
	78	: "=Q" (*p) : "r" (v) : "memory"); \
	79	break; \
	80	case 8: \
	81	asm volatile ("stlr %1, %0" \
	82	: "=Q" (*p) : "r" (v) : "memory"); \
	83	break; \
	84	} \
	85	} while (0)
	86
	87	#define smp_load_acquire(p) \
	88	({ \
	89	typeof(*p) ___p1; \
	90	compiletime_assert_atomic_type(*p); \
	91	switch (sizeof(*p)) { \
878a84d5 AP	92	case 1: \
	93	asm volatile ("ldarb %w0, %1" \
	94	: "=r" (___p1) : "Q" (*p) : "memory"); \
	95	break; \
	96	case 2: \
	97	asm volatile ("ldarh %w0, %1" \
	98	: "=r" (___p1) : "Q" (*p) : "memory"); \
	99	break; \
47933ad4 PZ	100	case 4: \
	101	asm volatile ("ldar %w0, %1" \
	102	: "=r" (___p1) : "Q" (*p) : "memory"); \
	103	break; \
	104	case 8: \
	105	asm volatile ("ldar %0, %1" \
	106	: "=r" (___p1) : "Q" (*p) : "memory"); \
	107	break; \
	108	} \
	109	___p1; \
	110	})
	111
10b663ae CM	112	#endif
	113
	114	#define read_barrier_depends() do { } while(0)
	115	#define smp_read_barrier_depends() do { } while(0)
	116
	117	#define set_mb(var, value) do { var = value; smp_mb(); } while (0)
	118	#define nop() asm volatile("nop");
	119
8715466b PZ	120	#define smp_mb__before_atomic() smp_mb()
	121	#define smp_mb__after_atomic() smp_mb()
	122
10b663ae CM	123	#endif /* __ASSEMBLY__ */
	124
	125	#endif /* __ASM_BARRIER_H */