[linux-2.6-block.git] / arch / arm64 / boot / dts / socionext / uniphier-ph1-ld20.dtsi

/*
 * Device Tree Source for UniPhier PH1-LD20 SoC
 *
 * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

/memreserve/ 0x80000000 0x00000008;	/* cpu-release-addr */

/ {
	compatible = "socionext,ph1-ld20";
	#address-cells = <2>;
	#size-cells = <2>;
	interrupt-parent = <&gic>;

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};
				core1 {
					cpu = <&cpu1>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&cpu2>;
				};
				core1 {
					cpu = <&cpu3>;
				};
			};
		};

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a72", "arm,armv8";
			reg = <0 0x000>;
			enable-method = "spin-table";
			cpu-release-addr = <0 0x80000000>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a72", "arm,armv8";
			reg = <0 0x001>;
			enable-method = "spin-table";
			cpu-release-addr = <0 0x80000000>;
		};

		cpu2: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a53", "arm,armv8";
			reg = <0 0x100>;
			enable-method = "spin-table";
			cpu-release-addr = <0 0x80000000>;
		};

		cpu3: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a53", "arm,armv8";
			reg = <0 0x101>;
			enable-method = "spin-table";
			cpu-release-addr = <0 0x80000000>;
		};
	};

	clocks {
		refclk: ref {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <25000000>;
		};

		uart_clk: uart_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <58820000>;
		};

		i2c_clk: i2c_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <50000000>;
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <1 13 4>,
			     <1 14 4>,
			     <1 11 4>,
			     <1 10 4>;
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0 0 0xffffffff>;

		serial0: serial@54006800 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006800 0x40>;
			interrupts = <0 33 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart0>;
			clocks = <&uart_clk>;
		};

		serial1: serial@54006900 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006900 0x40>;
			interrupts = <0 35 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart1>;
			clocks = <&uart_clk>;
		};

		serial2: serial@54006a00 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006a00 0x40>;
			interrupts = <0 37 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart2>;
			clocks = <&uart_clk>;
		};

		serial3: serial@54006b00 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006b00 0x40>;
			interrupts = <0 177 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart3>;
			clocks = <&uart_clk>;
		};

		i2c0: i2c@58780000 {
			compatible = "socionext,uniphier-fi2c";
			status = "disabled";
			reg = <0x58780000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 41 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c0>;
			clocks = <&i2c_clk>;
			clock-frequency = <100000>;
		};

		i2c1: i2c@58781000 {
			compatible = "socionext,uniphier-fi2c";
			status = "disabled";
			reg = <0x58781000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 42 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c1>;
			clocks = <&i2c_clk>;
			clock-frequency = <100000>;
		};

		i2c2: i2c@58782000 {
			compatible = "socionext,uniphier-fi2c";
			reg = <0x58782000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 43 4>;
			clocks = <&i2c_clk>;
			clock-frequency = <400000>;
		};

		i2c3: i2c@58783000 {
			compatible = "socionext,uniphier-fi2c";
			status = "disabled";
			reg = <0x58783000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 44 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c3>;
			clocks = <&i2c_clk>;
			clock-frequency = <100000>;
		};

		i2c4: i2c@58784000 {
			compatible = "socionext,uniphier-fi2c";
			status = "disabled";
			reg = <0x58784000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 45 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c4>;
			clocks = <&i2c_clk>;
			clock-frequency = <100000>;
		};

		i2c5: i2c@58785000 {
			compatible = "socionext,uniphier-fi2c";
			reg = <0x58785000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 25 4>;
			clocks = <&i2c_clk>;
			clock-frequency = <400000>;
		};

		system_bus: system-bus@58c00000 {
			compatible = "socionext,uniphier-system-bus";
			status = "disabled";
			reg = <0x58c00000 0x400>;
			#address-cells = <2>;
			#size-cells = <1>;
		};

		smpctrl@59800000 {
			compatible = "socionext,uniphier-smpctrl";
			reg = <0x59801000 0x400>;
		};

		soc-glue@5f800000 {
			compatible = "simple-mfd", "syscon";
			reg = <0x5f800000 0x2000>;

			pinctrl: pinctrl {
				 compatible = "socionext,uniphier-ld20-pinctrl";
			};
		};

		gic: interrupt-controller@5fe00000 {
			compatible = "arm,gic-v3";
			reg = <0x5fe00000 0x10000>,	/* GICD */
			      <0x5fe80000 0x80000>;	/* GICR */
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupts = <1 9 4>;
		};
	};
};

/include/ "uniphier-pinctrl.dtsi"
Commit	Line	Data
e1a0ebc8	1	/*
65e43389	2	* Device Tree Source for UniPhier PH1-LD20 SoC
e1a0ebc8 MY	3	*
	4	* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
	5	*
	6	* This file is dual-licensed: you can use it either under the terms
	7	* of the GPL or the X11 license, at your option. Note that this dual
	8	* licensing only applies to this file, and not this project as a
	9	* whole.
	10	*
	11	* a) This file is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of the
	14	* License, or (at your option) any later version.
	15	*
	16	* This file is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* Or, alternatively,
	22	*
	23	* b) Permission is hereby granted, free of charge, to any person
	24	* obtaining a copy of this software and associated documentation
	25	* files (the "Software"), to deal in the Software without
	26	* restriction, including without limitation the rights to use,
	27	* copy, modify, merge, publish, distribute, sublicense, and/or
	28	* sell copies of the Software, and to permit persons to whom the
	29	* Software is furnished to do so, subject to the following
	30	* conditions:
	31	*
	32	* The above copyright notice and this permission notice shall be
	33	* included in all copies or substantial portions of the Software.
	34	*
	35	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	36	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	37	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	38	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	39	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	40	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	41	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	42	* OTHER DEALINGS IN THE SOFTWARE.
	43	*/
	44
ffd8a5ed MY	45	/memreserve/ 0x80000000 0x00000008; /* cpu-release-addr */
ffd8a5ed MY	46
e1a0ebc8	47	/ {
65e43389	48	compatible = "socionext,ph1-ld20";
e1a0ebc8 MY	49	#address-cells = <2>;
	50	#size-cells = <2>;
	51	interrupt-parent = <&gic>;
	52
	53	cpus {
	54	#address-cells = <2>;
	55	#size-cells = <0>;
	56
	57	cpu-map {
	58	cluster0 {
	59	core0 {
	60	cpu = <&cpu0>;
	61	};
	62	core1 {
	63	cpu = <&cpu1>;
	64	};
	65	};
	66
	67	cluster1 {
	68	core0 {
	69	cpu = <&cpu2>;
	70	};
	71	core1 {
	72	cpu = <&cpu3>;
	73	};
	74	};
	75	};
	76
	77	cpu0: cpu@0 {
	78	device_type = "cpu";
	79	compatible = "arm,cortex-a72", "arm,armv8";
	80	reg = <0 0x000>;
	81	enable-method = "spin-table";
1388ea2a	82	cpu-release-addr = <0 0x80000000>;
e1a0ebc8 MY	83	};
	84
	85	cpu1: cpu@1 {
	86	device_type = "cpu";
	87	compatible = "arm,cortex-a72", "arm,armv8";
	88	reg = <0 0x001>;
	89	enable-method = "spin-table";
1388ea2a	90	cpu-release-addr = <0 0x80000000>;
e1a0ebc8 MY	91	};
	92
	93	cpu2: cpu@100 {
	94	device_type = "cpu";
	95	compatible = "arm,cortex-a53", "arm,armv8";
	96	reg = <0 0x100>;
	97	enable-method = "spin-table";
1388ea2a	98	cpu-release-addr = <0 0x80000000>;
e1a0ebc8 MY	99	};
	100
	101	cpu3: cpu@101 {
	102	device_type = "cpu";
	103	compatible = "arm,cortex-a53", "arm,armv8";
	104	reg = <0 0x101>;
	105	enable-method = "spin-table";
1388ea2a	106	cpu-release-addr = <0 0x80000000>;
e1a0ebc8 MY	107	};
	108	};
	109
	110	clocks {
fb89cf36 MY	111	refclk: ref {
	112	compatible = "fixed-clock";
	113	#clock-cells = <0>;
	114	clock-frequency = <25000000>;
	115	};
	116
e1a0ebc8 MY	117	uart_clk: uart_clk {
	118	#clock-cells = <0>;
	119	compatible = "fixed-clock";
	120	clock-frequency = <58820000>;
	121	};
	122
	123	i2c_clk: i2c_clk {
	124	#clock-cells = <0>;
	125	compatible = "fixed-clock";
	126	clock-frequency = <50000000>;
	127	};
	128	};
	129
	130	timer {
	131	compatible = "arm,armv8-timer";
f2a89d3b MZ	132	interrupts = <1 13 4>,
	133	<1 14 4>,
	134	<1 11 4>,
	135	<1 10 4>;
e1a0ebc8 MY	136	};
	137
	138	soc {
	139	compatible = "simple-bus";
	140	#address-cells = <1>;
	141	#size-cells = <1>;
	142	ranges = <0 0 0 0xffffffff>;
	143
e1a0ebc8 MY	144	serial0: serial@54006800 {
	145	compatible = "socionext,uniphier-uart";
	146	status = "disabled";
	147	reg = <0x54006800 0x40>;
	148	interrupts = <0 33 4>;
	149	pinctrl-names = "default";
	150	pinctrl-0 = <&pinctrl_uart0>;
	151	clocks = <&uart_clk>;
	152	};
	153
	154	serial1: serial@54006900 {
	155	compatible = "socionext,uniphier-uart";
	156	status = "disabled";
	157	reg = <0x54006900 0x40>;
	158	interrupts = <0 35 4>;
	159	pinctrl-names = "default";
	160	pinctrl-0 = <&pinctrl_uart1>;
	161	clocks = <&uart_clk>;
	162	};
	163
	164	serial2: serial@54006a00 {
	165	compatible = "socionext,uniphier-uart";
	166	status = "disabled";
	167	reg = <0x54006a00 0x40>;
	168	interrupts = <0 37 4>;
	169	pinctrl-names = "default";
	170	pinctrl-0 = <&pinctrl_uart2>;
	171	clocks = <&uart_clk>;
	172	};
	173
	174	serial3: serial@54006b00 {
	175	compatible = "socionext,uniphier-uart";
	176	status = "disabled";
	177	reg = <0x54006b00 0x40>;
	178	interrupts = <0 177 4>;
	179	pinctrl-names = "default";
	180	pinctrl-0 = <&pinctrl_uart3>;
	181	clocks = <&uart_clk>;
	182	};
	183
	184	i2c0: i2c@58780000 {
	185	compatible = "socionext,uniphier-fi2c";
	186	status = "disabled";
	187	reg = <0x58780000 0x80>;
	188	#address-cells = <1>;
	189	#size-cells = <0>;
	190	interrupts = <0 41 4>;
	191	pinctrl-names = "default";
	192	pinctrl-0 = <&pinctrl_i2c0>;
	193	clocks = <&i2c_clk>;
	194	clock-frequency = <100000>;
	195	};
	196
	197	i2c1: i2c@58781000 {
	198	compatible = "socionext,uniphier-fi2c";
	199	status = "disabled";
	200	reg = <0x58781000 0x80>;
	201	#address-cells = <1>;
	202	#size-cells = <0>;
	203	interrupts = <0 42 4>;
	204	pinctrl-names = "default";
	205	pinctrl-0 = <&pinctrl_i2c1>;
	206	clocks = <&i2c_clk>;
	207	clock-frequency = <100000>;
208	};
209
210	i2c2: i2c@58782000 {
211	compatible = "socionext,uniphier-fi2c";
e1a0ebc8 MY	212	reg = <0x58782000 0x80>;
	213	#address-cells = <1>;
	214	#size-cells = <0>;
	215	interrupts = <0 43 4>;
e1a0ebc8	216	clocks = <&i2c_clk>;
56896ef5	217	clock-frequency = <400000>;
e1a0ebc8 MY	218	};
	219
	220	i2c3: i2c@58783000 {
	221	compatible = "socionext,uniphier-fi2c";
	222	status = "disabled";
	223	reg = <0x58783000 0x80>;
	224	#address-cells = <1>;
	225	#size-cells = <0>;
	226	interrupts = <0 44 4>;
	227	pinctrl-names = "default";
	228	pinctrl-0 = <&pinctrl_i2c3>;
	229	clocks = <&i2c_clk>;
	230	clock-frequency = <100000>;
	231	};
	232
	233	i2c4: i2c@58784000 {
	234	compatible = "socionext,uniphier-fi2c";
56896ef5	235	status = "disabled";
e1a0ebc8 MY	236	reg = <0x58784000 0x80>;
	237	#address-cells = <1>;
	238	#size-cells = <0>;
	239	interrupts = <0 45 4>;
56896ef5 MY	240	pinctrl-names = "default";
56896ef5 MY	241	pinctrl-0 = <&pinctrl_i2c4>;
e1a0ebc8	242	clocks = <&i2c_clk>;
56896ef5	243	clock-frequency = <100000>;
e1a0ebc8 MY	244	};
	245
	246	i2c5: i2c@58785000 {
	247	compatible = "socionext,uniphier-fi2c";
	248	reg = <0x58785000 0x80>;
	249	#address-cells = <1>;
	250	#size-cells = <0>;
	251	interrupts = <0 25 4>;
	252	clocks = <&i2c_clk>;
	253	clock-frequency = <400000>;
	254	};
	255
14bae133 MY	256	system_bus: system-bus@58c00000 {
	257	compatible = "socionext,uniphier-system-bus";
	258	status = "disabled";
	259	reg = <0x58c00000 0x400>;
	260	#address-cells = <2>;
	261	#size-cells = <1>;
	262	};
	263
	264	smpctrl@59800000 {
	265	compatible = "socionext,uniphier-smpctrl";
	266	reg = <0x59801000 0x400>;
	267	};
	268
ed6cca5f MY	269	soc-glue@5f800000 {
	270	compatible = "simple-mfd", "syscon";
	271	reg = <0x5f800000 0x2000>;
	272
	273	pinctrl: pinctrl {
	274	compatible = "socionext,uniphier-ld20-pinctrl";
	275	};
e1a0ebc8 MY	276	};
	277
	278	gic: interrupt-controller@5fe00000 {
	279	compatible = "arm,gic-v3";
	280	reg = <0x5fe00000 0x10000>, /* GICD */
	281	<0x5fe80000 0x80000>; /* GICR */
	282	interrupt-controller;
	283	#interrupt-cells = <3>;
	284	interrupts = <1 9 4>;
	285	};
	286	};
	287	};
	288
	289	/include/ "uniphier-pinctrl.dtsi"