[linux-2.6-block.git] / arch / arm64 / boot / dts / freescale / fsl-ls1043a.dtsi

/*
 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
 *
 * Copyright 2014-2015, Freescale Semiconductor
 *
 * Mingkai Hu <Mingkai.hu@freescale.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPLv2 or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This library is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This library is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

/ {
	compatible = "fsl,ls1043a";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		/*
		 * We expect the enable-method for cpu's to be "psci", but this
		 * is dependent on the SoC FW, which will fill this in.
		 *
		 * Currently supported enable-method is psci v0.2
		 */
		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0>;
			clocks = <&clockgen 1 0>;
			next-level-cache = <&l2>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x1>;
			clocks = <&clockgen 1 0>;
			next-level-cache = <&l2>;
		};

		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x2>;
			clocks = <&clockgen 1 0>;
			next-level-cache = <&l2>;
		};

		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x3>;
			clocks = <&clockgen 1 0>;
			next-level-cache = <&l2>;
		};

		l2: l2-cache {
			compatible = "cache";
		};
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x0 0x80000000 0 0x80000000>;
		      /* DRAM space 1, size: 2GiB DRAM */
	};

	sysclk: sysclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <100000000>;
		clock-output-names = "sysclk";
	};

	reboot {
		compatible ="syscon-reboot";
		regmap = <&dcfg>;
		offset = <0xb0>;
		mask = <0x02>;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <1 13 0xf08>, /* Physical Secure PPI */
			     <1 14 0xf08>, /* Physical Non-Secure PPI */
			     <1 11 0xf08>, /* Virtual PPI */
			     <1 10 0xf08>; /* Hypervisor PPI */
	};

	pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <0 106 0x4>,
			     <0 107 0x4>,
			     <0 95 0x4>,
			     <0 97 0x4>;
		interrupt-affinity = <&cpu0>,
				     <&cpu1>,
				     <&cpu2>,
				     <&cpu3>;
	};

	gic: interrupt-controller@1400000 {
		compatible = "arm,gic-400";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0x0 0x1401000 0 0x1000>, /* GICD */
		      <0x0 0x1402000 0 0x2000>, /* GICC */
		      <0x0 0x1404000 0 0x2000>, /* GICH */
		      <0x0 0x1406000 0 0x2000>; /* GICV */
		interrupts = <1 9 0xf08>;
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		clockgen: clocking@1ee1000 {
			compatible = "fsl,ls1043a-clockgen";
			reg = <0x0 0x1ee1000 0x0 0x1000>;
			#clock-cells = <2>;
			clocks = <&sysclk>;
		};

		scfg: scfg@1570000 {
			compatible = "fsl,ls1043a-scfg", "syscon";
			reg = <0x0 0x1570000 0x0 0x10000>;
			big-endian;
		};

		crypto: crypto@1700000 {
			compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
				     "fsl,sec-v4.0";
			fsl,sec-era = <3>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x00 0x1700000 0x100000>;
			reg = <0x00 0x1700000 0x0 0x100000>;
			interrupts = <0 75 0x4>;

			sec_jr0: jr@10000 {
				compatible = "fsl,sec-v5.4-job-ring",
					     "fsl,sec-v5.0-job-ring",
					     "fsl,sec-v4.0-job-ring";
				reg	   = <0x10000 0x10000>;
				interrupts = <0 71 0x4>;
			};

			sec_jr1: jr@20000 {
				compatible = "fsl,sec-v5.4-job-ring",
					     "fsl,sec-v5.0-job-ring",
					     "fsl,sec-v4.0-job-ring";
				reg	   = <0x20000 0x10000>;
				interrupts = <0 72 0x4>;
			};

			sec_jr2: jr@30000 {
				compatible = "fsl,sec-v5.4-job-ring",
					     "fsl,sec-v5.0-job-ring",
					     "fsl,sec-v4.0-job-ring";
				reg	   = <0x30000 0x10000>;
				interrupts = <0 73 0x4>;
			};

			sec_jr3: jr@40000 {
				compatible = "fsl,sec-v5.4-job-ring",
					     "fsl,sec-v5.0-job-ring",
					     "fsl,sec-v4.0-job-ring";
				reg	   = <0x40000 0x10000>;
				interrupts = <0 74 0x4>;
			};
		};

		dcfg: dcfg@1ee0000 {
			compatible = "fsl,ls1043a-dcfg", "syscon";
			reg = <0x0 0x1ee0000 0x0 0x10000>;
			big-endian;
		};

		ifc: ifc@1530000 {
			compatible = "fsl,ifc", "simple-bus";
			reg = <0x0 0x1530000 0x0 0x10000>;
			interrupts = <0 43 0x4>;
		};

		qspi: quadspi@1550000 {
			compatible = "fsl,ls1043a-qspi", "fsl,ls1021a-qspi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x1550000 0x0 0x10000>,
				<0x0 0x40000000 0x0 0x4000000>;
			reg-names = "QuadSPI", "QuadSPI-memory";
			interrupts = <0 99 0x4>;
			clock-names = "qspi_en", "qspi";
			clocks = <&clockgen 4 0>, <&clockgen 4 0>;
			big-endian;
			status = "disabled";
		};

		esdhc: esdhc@1560000 {
			compatible = "fsl,ls1043a-esdhc", "fsl,esdhc";
			reg = <0x0 0x1560000 0x0 0x10000>;
			interrupts = <0 62 0x4>;
			clock-frequency = <0>;
			voltage-ranges = <1800 1800 3300 3300>;
			sdhci,auto-cmd12;
			big-endian;
			bus-width = <4>;
		};

		dspi0: dspi@2100000 {
			compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2100000 0x0 0x10000>;
			interrupts = <0 64 0x4>;
			clock-names = "dspi";
			clocks = <&clockgen 4 0>;
			spi-num-chipselects = <5>;
			big-endian;
			status = "disabled";
		};

		dspi1: dspi@2110000 {
			compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2110000 0x0 0x10000>;
			interrupts = <0 65 0x4>;
			clock-names = "dspi";
			clocks = <&clockgen 4 0>;
			spi-num-chipselects = <5>;
			big-endian;
			status = "disabled";
		};

		i2c0: i2c@2180000 {
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2180000 0x0 0x10000>;
			interrupts = <0 56 0x4>;
			clock-names = "i2c";
			clocks = <&clockgen 4 0>;
			dmas = <&edma0 1 39>,
			       <&edma0 1 38>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		i2c1: i2c@2190000 {
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2190000 0x0 0x10000>;
			interrupts = <0 57 0x4>;
			clock-names = "i2c";
			clocks = <&clockgen 4 0>;
			status = "disabled";
		};

		i2c2: i2c@21a0000 {
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x21a0000 0x0 0x10000>;
			interrupts = <0 58 0x4>;
			clock-names = "i2c";
			clocks = <&clockgen 4 0>;
			status = "disabled";
		};

		i2c3: i2c@21b0000 {
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x21b0000 0x0 0x10000>;
			interrupts = <0 59 0x4>;
			clock-names = "i2c";
			clocks = <&clockgen 4 0>;
			status = "disabled";
		};

		duart0: serial@21c0500 {
			compatible = "fsl,ns16550", "ns16550a";
			reg = <0x00 0x21c0500 0x0 0x100>;
			interrupts = <0 54 0x4>;
			clocks = <&clockgen 4 0>;
		};

		duart1: serial@21c0600 {
			compatible = "fsl,ns16550", "ns16550a";
			reg = <0x00 0x21c0600 0x0 0x100>;
			interrupts = <0 54 0x4>;
			clocks = <&clockgen 4 0>;
		};

		duart2: serial@21d0500 {
			compatible = "fsl,ns16550", "ns16550a";
			reg = <0x0 0x21d0500 0x0 0x100>;
			interrupts = <0 55 0x4>;
			clocks = <&clockgen 4 0>;
		};

		duart3: serial@21d0600 {
			compatible = "fsl,ns16550", "ns16550a";
			reg = <0x0 0x21d0600 0x0 0x100>;
			interrupts = <0 55 0x4>;
			clocks = <&clockgen 4 0>;
		};

		gpio1: gpio@2300000 {
			compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
			reg = <0x0 0x2300000 0x0 0x10000>;
			interrupts = <0 66 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio2: gpio@2310000 {
			compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
			reg = <0x0 0x2310000 0x0 0x10000>;
			interrupts = <0 67 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio3: gpio@2320000 {
			compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
			reg = <0x0 0x2320000 0x0 0x10000>;
			interrupts = <0 68 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio4: gpio@2330000 {
			compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
			reg = <0x0 0x2330000 0x0 0x10000>;
			interrupts = <0 134 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		lpuart0: serial@2950000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x2950000 0x0 0x1000>;
			interrupts = <0 48 0x4>;
			clocks = <&clockgen 0 0>;
			clock-names = "ipg";
			status = "disabled";
		};

		lpuart1: serial@2960000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x2960000 0x0 0x1000>;
			interrupts = <0 49 0x4>;
			clocks = <&clockgen 4 0>;
			clock-names = "ipg";
			status = "disabled";
		};

		lpuart2: serial@2970000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x2970000 0x0 0x1000>;
			interrupts = <0 50 0x4>;
			clocks = <&clockgen 4 0>;
			clock-names = "ipg";
			status = "disabled";
		};

		lpuart3: serial@2980000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x2980000 0x0 0x1000>;
			interrupts = <0 51 0x4>;
			clocks = <&clockgen 4 0>;
			clock-names = "ipg";
			status = "disabled";
		};

		lpuart4: serial@2990000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x2990000 0x0 0x1000>;
			interrupts = <0 52 0x4>;
			clocks = <&clockgen 4 0>;
			clock-names = "ipg";
			status = "disabled";
		};

		lpuart5: serial@29a0000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x29a0000 0x0 0x1000>;
			interrupts = <0 53 0x4>;
			clocks = <&clockgen 4 0>;
			clock-names = "ipg";
			status = "disabled";
		};

		wdog0: wdog@2ad0000 {
			compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
			reg = <0x0 0x2ad0000 0x0 0x10000>;
			interrupts = <0 83 0x4>;
			clocks = <&clockgen 4 0>;
			clock-names = "wdog";
			big-endian;
		};

		edma0: edma@2c00000 {
			#dma-cells = <2>;
			compatible = "fsl,vf610-edma";
			reg = <0x0 0x2c00000 0x0 0x10000>,
			      <0x0 0x2c10000 0x0 0x10000>,
			      <0x0 0x2c20000 0x0 0x10000>;
			interrupts = <0 103 0x4>,
				     <0 103 0x4>;
			interrupt-names = "edma-tx", "edma-err";
			dma-channels = <32>;
			big-endian;
			clock-names = "dmamux0", "dmamux1";
			clocks = <&clockgen 4 0>,
				 <&clockgen 4 0>;
		};

		usb0: usb3@2f00000 {
			compatible = "snps,dwc3";
			reg = <0x0 0x2f00000 0x0 0x10000>;
			interrupts = <0 60 0x4>;
			dr_mode = "host";
			snps,quirk-frame-length-adjustment = <0x20>;
			snps,dis_rxdet_inp3_quirk;
		};

		usb1: usb3@3000000 {
			compatible = "snps,dwc3";
			reg = <0x0 0x3000000 0x0 0x10000>;
			interrupts = <0 61 0x4>;
			dr_mode = "host";
			snps,quirk-frame-length-adjustment = <0x20>;
			snps,dis_rxdet_inp3_quirk;
		};

		usb2: usb3@3100000 {
			compatible = "snps,dwc3";
			reg = <0x0 0x3100000 0x0 0x10000>;
			interrupts = <0 63 0x4>;
			dr_mode = "host";
			snps,quirk-frame-length-adjustment = <0x20>;
			snps,dis_rxdet_inp3_quirk;
		};

		sata: sata@3200000 {
			compatible = "fsl,ls1043a-ahci", "fsl,ls1021a-ahci";
			reg = <0x0 0x3200000 0x0 0x10000>;
			interrupts = <0 69 0x4>;
			clocks = <&clockgen 4 0>;
		};

		msi1: msi-controller1@1571000 {
			compatible = "fsl,1s1043a-msi";
			reg = <0x0 0x1571000 0x0 0x8>;
			msi-controller;
			interrupts = <0 116 0x4>;
		};

		msi2: msi-controller2@1572000 {
			compatible = "fsl,1s1043a-msi";
			reg = <0x0 0x1572000 0x0 0x8>;
			msi-controller;
			interrupts = <0 126 0x4>;
		};

		msi3: msi-controller3@1573000 {
			compatible = "fsl,1s1043a-msi";
			reg = <0x0 0x1573000 0x0 0x8>;
			msi-controller;
			interrupts = <0 160 0x4>;
		};

		pcie@3400000 {
			compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
			reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
			       0x40 0x00000000 0x0 0x00002000>; /* configuration space */
			reg-names = "regs", "config";
			interrupts = <0 118 0x4>, /* controller interrupt */
				     <0 117 0x4>; /* PME interrupt */
			interrupt-names = "intr", "pme";
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			dma-coherent;
			num-lanes = <4>;
			bus-range = <0x0 0xff>;
			ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
				  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
			msi-parent = <&msi1>;
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 7>;
			interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
					<0000 0 0 2 &gic 0 111 0x4>,
					<0000 0 0 3 &gic 0 112 0x4>,
					<0000 0 0 4 &gic 0 113 0x4>;
		};

		pcie@3500000 {
			compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
			reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
			       0x48 0x00000000 0x0 0x00002000>; /* configuration space */
			reg-names = "regs", "config";
			interrupts = <0 128 0x4>,
				     <0 127 0x4>;
			interrupt-names = "intr", "pme";
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			dma-coherent;
			num-lanes = <2>;
			bus-range = <0x0 0xff>;
			ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */
				  0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
			msi-parent = <&msi2>;
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 7>;
			interrupt-map = <0000 0 0 1 &gic 0 120  0x4>,
					<0000 0 0 2 &gic 0 121 0x4>,
					<0000 0 0 3 &gic 0 122 0x4>,
					<0000 0 0 4 &gic 0 123 0x4>;
		};

		pcie@3600000 {
			compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
			reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
			       0x50 0x00000000 0x0 0x00002000>; /* configuration space */
			reg-names = "regs", "config";
			interrupts = <0 162 0x4>,
				     <0 161 0x4>;
			interrupt-names = "intr", "pme";
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			dma-coherent;
			num-lanes = <2>;
			bus-range = <0x0 0xff>;
			ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000   /* downstream I/O */
				  0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
			msi-parent = <&msi3>;
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 7>;
			interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
					<0000 0 0 2 &gic 0 155 0x4>,
					<0000 0 0 3 &gic 0 156 0x4>,
					<0000 0 0 4 &gic 0 157 0x4>;
		};
	};

};
Commit	Line	Data
6d453cd2 MH	1	/*
	2	* Device Tree Include file for Freescale Layerscape-1043A family SoC.
	3	*
	4	* Copyright 2014-2015, Freescale Semiconductor
	5	*
	6	* Mingkai Hu <Mingkai.hu@freescale.com>
	7	*
	8	* This file is dual-licensed: you can use it either under the terms
	9	* of the GPLv2 or the X11 license, at your option. Note that this dual
	10	* licensing only applies to this file, and not this project as a
	11	* whole.
	12	*
	13	* a) This library is free software; you can redistribute it and/or
	14	* modify it under the terms of the GNU General Public License as
	15	* published by the Free Software Foundation; either version 2 of the
	16	* License, or (at your option) any later version.
	17	*
	18	* This library is distributed in the hope that it will be useful,
	19	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	20	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	21	* GNU General Public License for more details.
	22	*
	23	* Or, alternatively,
	24	*
	25	* b) Permission is hereby granted, free of charge, to any person
	26	* obtaining a copy of this software and associated documentation
	27	* files (the "Software"), to deal in the Software without
	28	* restriction, including without limitation the rights to use,
	29	* copy, modify, merge, publish, distribute, sublicense, and/or
	30	* sell copies of the Software, and to permit persons to whom the
	31	* Software is furnished to do so, subject to the following
	32	* conditions:
	33	*
	34	* The above copyright notice and this permission notice shall be
	35	* included in all copies or substantial portions of the Software.
	36	*
	37	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	38	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	39	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	40	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	41	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	42	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	43	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	44	* OTHER DEALINGS IN THE SOFTWARE.
	45	*/
	46
	47	/ {
	48	compatible = "fsl,ls1043a";
	49	interrupt-parent = <&gic>;
	50	#address-cells = <2>;
	51	#size-cells = <2>;
	52
	53	cpus {
e6d66c50	54	#address-cells = <1>;
6d453cd2 MH	55	#size-cells = <0>;
	56
	57	/*
	58	* We expect the enable-method for cpu's to be "psci", but this
	59	* is dependent on the SoC FW, which will fill this in.
	60	*
	61	* Currently supported enable-method is psci v0.2
	62	*/
	63	cpu0: cpu@0 {
	64	device_type = "cpu";
	65	compatible = "arm,cortex-a53";
e6d66c50	66	reg = <0x0>;
6d453cd2	67	clocks = <&clockgen 1 0>;
ec049f33	68	next-level-cache = <&l2>;
6d453cd2 MH	69	};
	70
	71	cpu1: cpu@1 {
	72	device_type = "cpu";
	73	compatible = "arm,cortex-a53";
e6d66c50	74	reg = <0x1>;
6d453cd2	75	clocks = <&clockgen 1 0>;
ec049f33	76	next-level-cache = <&l2>;
6d453cd2 MH	77	};
	78
	79	cpu2: cpu@2 {
	80	device_type = "cpu";
	81	compatible = "arm,cortex-a53";
e6d66c50	82	reg = <0x2>;
6d453cd2	83	clocks = <&clockgen 1 0>;
ec049f33	84	next-level-cache = <&l2>;
6d453cd2 MH	85	};
	86
	87	cpu3: cpu@3 {
	88	device_type = "cpu";
	89	compatible = "arm,cortex-a53";
e6d66c50	90	reg = <0x3>;
6d453cd2	91	clocks = <&clockgen 1 0>;
ec049f33 LY	92	next-level-cache = <&l2>;
	93	};
	94
	95	l2: l2-cache {
	96	compatible = "cache";
6d453cd2 MH	97	};
	98	};
	99
	100	memory@80000000 {
	101	device_type = "memory";
	102	reg = <0x0 0x80000000 0 0x80000000>;
	103	/* DRAM space 1, size: 2GiB DRAM */
	104	};
	105
	106	sysclk: sysclk {
	107	compatible = "fixed-clock";
	108	#clock-cells = <0>;
	109	clock-frequency = <100000000>;
	110	clock-output-names = "sysclk";
	111	};
	112
	113	reboot {
	114	compatible ="syscon-reboot";
	115	regmap = <&dcfg>;
	116	offset = <0xb0>;
	117	mask = <0x02>;
	118	};
	119
	120	timer {
	121	compatible = "arm,armv8-timer";
f2a89d3b MZ	122	interrupts = <1 13 0xf08>, /* Physical Secure PPI */
	123	<1 14 0xf08>, /* Physical Non-Secure PPI */
	124	<1 11 0xf08>, /* Virtual PPI */
	125	<1 10 0xf08>; /* Hypervisor PPI */
6d453cd2 MH	126	};
	127
	128	pmu {
	129	compatible = "arm,armv8-pmuv3";
	130	interrupts = <0 106 0x4>,
	131	<0 107 0x4>,
	132	<0 95 0x4>,
	133	<0 97 0x4>;
	134	interrupt-affinity = <&cpu0>,
	135	<&cpu1>,
	136	<&cpu2>,
	137	<&cpu3>;
	138	};
	139
	140	gic: interrupt-controller@1400000 {
	141	compatible = "arm,gic-400";
	142	#interrupt-cells = <3>;
	143	interrupt-controller;
	144	reg = <0x0 0x1401000 0 0x1000>, /* GICD */
	145	<0x0 0x1402000 0 0x2000>, /* GICC */
	146	<0x0 0x1404000 0 0x2000>, /* GICH */
	147	<0x0 0x1406000 0 0x2000>; /* GICV */
	148	interrupts = <1 9 0xf08>;
	149	};
	150
	151	soc {
	152	compatible = "simple-bus";
	153	#address-cells = <2>;
	154	#size-cells = <2>;
	155	ranges;
	156
	157	clockgen: clocking@1ee1000 {
	158	compatible = "fsl,ls1043a-clockgen";
	159	reg = <0x0 0x1ee1000 0x0 0x1000>;
	160	#clock-cells = <2>;
	161	clocks = <&sysclk>;
	162	};
	163
	164	scfg: scfg@1570000 {
	165	compatible = "fsl,ls1043a-scfg", "syscon";
	166	reg = <0x0 0x1570000 0x0 0x10000>;
	167	big-endian;
	168	};
	169
63dac35b HG	170	crypto: crypto@1700000 {
	171	compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
	172	"fsl,sec-v4.0";
	173	fsl,sec-era = <3>;
	174	#address-cells = <1>;
	175	#size-cells = <1>;
	176	ranges = <0x0 0x00 0x1700000 0x100000>;
	177	reg = <0x00 0x1700000 0x0 0x100000>;
	178	interrupts = <0 75 0x4>;
	179
	180	sec_jr0: jr@10000 {
	181	compatible = "fsl,sec-v5.4-job-ring",
	182	"fsl,sec-v5.0-job-ring",
	183	"fsl,sec-v4.0-job-ring";
	184	reg = <0x10000 0x10000>;
	185	interrupts = <0 71 0x4>;
	186	};
	187
	188	sec_jr1: jr@20000 {
	189	compatible = "fsl,sec-v5.4-job-ring",
	190	"fsl,sec-v5.0-job-ring",
	191	"fsl,sec-v4.0-job-ring";
	192	reg = <0x20000 0x10000>;
	193	interrupts = <0 72 0x4>;
	194	};
	195
	196	sec_jr2: jr@30000 {
	197	compatible = "fsl,sec-v5.4-job-ring",
	198	"fsl,sec-v5.0-job-ring",
	199	"fsl,sec-v4.0-job-ring";
	200	reg = <0x30000 0x10000>;
	201	interrupts = <0 73 0x4>;
	202	};
	203
	204	sec_jr3: jr@40000 {
	205	compatible = "fsl,sec-v5.4-job-ring",
	206	"fsl,sec-v5.0-job-ring",
	207	"fsl,sec-v4.0-job-ring";
	208	reg = <0x40000 0x10000>;
	209	interrupts = <0 74 0x4>;
	210	};
	211	};
	212
6d453cd2 MH	213	dcfg: dcfg@1ee0000 {
	214	compatible = "fsl,ls1043a-dcfg", "syscon";
	215	reg = <0x0 0x1ee0000 0x0 0x10000>;
	216	big-endian;
	217	};
	218
	219	ifc: ifc@1530000 {
	220	compatible = "fsl,ifc", "simple-bus";
	221	reg = <0x0 0x1530000 0x0 0x10000>;
	222	interrupts = <0 43 0x4>;
	223	};
	224
e26e054b YY	225	qspi: quadspi@1550000 {
	226	compatible = "fsl,ls1043a-qspi", "fsl,ls1021a-qspi";
	227	#address-cells = <1>;
	228	#size-cells = <0>;
	229	reg = <0x0 0x1550000 0x0 0x10000>,
	230	<0x0 0x40000000 0x0 0x4000000>;
	231	reg-names = "QuadSPI", "QuadSPI-memory";
	232	interrupts = <0 99 0x4>;
	233	clock-names = "qspi_en", "qspi";
	234	clocks = <&clockgen 4 0>, <&clockgen 4 0>;
	235	big-endian;
	236	status = "disabled";
	237	};
	238
6d453cd2 MH	239	esdhc: esdhc@1560000 {
	240	compatible = "fsl,ls1043a-esdhc", "fsl,esdhc";
	241	reg = <0x0 0x1560000 0x0 0x10000>;
	242	interrupts = <0 62 0x4>;
	243	clock-frequency = <0>;
	244	voltage-ranges = <1800 1800 3300 3300>;
	245	sdhci,auto-cmd12;
	246	big-endian;
	247	bus-width = <4>;
	248	};
	249
	250	dspi0: dspi@2100000 {
	251	compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
	252	#address-cells = <1>;
	253	#size-cells = <0>;
	254	reg = <0x0 0x2100000 0x0 0x10000>;
	255	interrupts = <0 64 0x4>;
	256	clock-names = "dspi";
	257	clocks = <&clockgen 4 0>;
	258	spi-num-chipselects = <5>;
	259	big-endian;
	260	status = "disabled";
	261	};
	262
	263	dspi1: dspi@2110000 {
	264	compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
	265	#address-cells = <1>;
	266	#size-cells = <0>;
	267	reg = <0x0 0x2110000 0x0 0x10000>;
	268	interrupts = <0 65 0x4>;
	269	clock-names = "dspi";
	270	clocks = <&clockgen 4 0>;
	271	spi-num-chipselects = <5>;
	272	big-endian;
	273	status = "disabled";
	274	};
	275
	276	i2c0: i2c@2180000 {
	277	compatible = "fsl,vf610-i2c";
	278	#address-cells = <1>;
	279	#size-cells = <0>;
	280	reg = <0x0 0x2180000 0x0 0x10000>;
	281	interrupts = <0 56 0x4>;
	282	clock-names = "i2c";
	283	clocks = <&clockgen 4 0>;
	284	dmas = <&edma0 1 39>,
	285	<&edma0 1 38>;
	286	dma-names = "tx", "rx";
	287	status = "disabled";
	288	};
	289
	290	i2c1: i2c@2190000 {
	291	compatible = "fsl,vf610-i2c";
	292	#address-cells = <1>;
	293	#size-cells = <0>;
	294	reg = <0x0 0x2190000 0x0 0x10000>;
	295	interrupts = <0 57 0x4>;
	296	clock-names = "i2c";
	297	clocks = <&clockgen 4 0>;
	298	status = "disabled";
	299	};
	300
	301	i2c2: i2c@21a0000 {
	302	compatible = "fsl,vf610-i2c";
303	#address-cells = <1>;
304	#size-cells = <0>;
305	reg = <0x0 0x21a0000 0x0 0x10000>;
306	interrupts = <0 58 0x4>;
307	clock-names = "i2c";
308	clocks = <&clockgen 4 0>;
309	status = "disabled";
310	};
311
312	i2c3: i2c@21b0000 {
313	compatible = "fsl,vf610-i2c";
314	#address-cells = <1>;
315	#size-cells = <0>;
316	reg = <0x0 0x21b0000 0x0 0x10000>;
317	interrupts = <0 59 0x4>;
318	clock-names = "i2c";
319	clocks = <&clockgen 4 0>;
320	status = "disabled";
321	};
322
323	duart0: serial@21c0500 {
324	compatible = "fsl,ns16550", "ns16550a";
325	reg = <0x00 0x21c0500 0x0 0x100>;
326	interrupts = <0 54 0x4>;
327	clocks = <&clockgen 4 0>;
328	};
329
330	duart1: serial@21c0600 {
331	compatible = "fsl,ns16550", "ns16550a";
332	reg = <0x00 0x21c0600 0x0 0x100>;
333	interrupts = <0 54 0x4>;
334	clocks = <&clockgen 4 0>;
335	};
336
337	duart2: serial@21d0500 {
338	compatible = "fsl,ns16550", "ns16550a";
339	reg = <0x0 0x21d0500 0x0 0x100>;
340	interrupts = <0 55 0x4>;
341	clocks = <&clockgen 4 0>;
342	};
343
344	duart3: serial@21d0600 {
345	compatible = "fsl,ns16550", "ns16550a";
346	reg = <0x0 0x21d0600 0x0 0x100>;
347	interrupts = <0 55 0x4>;
348	clocks = <&clockgen 4 0>;
349	};
350
351	gpio1: gpio@2300000 {
c21de87d	352	compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
6d453cd2 MH	353	reg = <0x0 0x2300000 0x0 0x10000>;
	354	interrupts = <0 66 0x4>;
	355	gpio-controller;
	356	#gpio-cells = <2>;
	357	interrupt-controller;
	358	#interrupt-cells = <2>;
	359	};
	360
	361	gpio2: gpio@2310000 {
c21de87d	362	compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
6d453cd2 MH	363	reg = <0x0 0x2310000 0x0 0x10000>;
	364	interrupts = <0 67 0x4>;
	365	gpio-controller;
	366	#gpio-cells = <2>;
	367	interrupt-controller;
	368	#interrupt-cells = <2>;
	369	};
	370
	371	gpio3: gpio@2320000 {
c21de87d	372	compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
6d453cd2 MH	373	reg = <0x0 0x2320000 0x0 0x10000>;
	374	interrupts = <0 68 0x4>;
	375	gpio-controller;
	376	#gpio-cells = <2>;
	377	interrupt-controller;
	378	#interrupt-cells = <2>;
	379	};
	380
	381	gpio4: gpio@2330000 {
c21de87d	382	compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
6d453cd2 MH	383	reg = <0x0 0x2330000 0x0 0x10000>;
	384	interrupts = <0 134 0x4>;
	385	gpio-controller;
	386	#gpio-cells = <2>;
	387	interrupt-controller;
	388	#interrupt-cells = <2>;
	389	};
	390
	391	lpuart0: serial@2950000 {
	392	compatible = "fsl,ls1021a-lpuart";
	393	reg = <0x0 0x2950000 0x0 0x1000>;
	394	interrupts = <0 48 0x4>;
	395	clocks = <&clockgen 0 0>;
	396	clock-names = "ipg";
	397	status = "disabled";
	398	};
	399
	400	lpuart1: serial@2960000 {
	401	compatible = "fsl,ls1021a-lpuart";
	402	reg = <0x0 0x2960000 0x0 0x1000>;
	403	interrupts = <0 49 0x4>;
	404	clocks = <&clockgen 4 0>;
	405	clock-names = "ipg";
	406	status = "disabled";
	407	};
	408
	409	lpuart2: serial@2970000 {
	410	compatible = "fsl,ls1021a-lpuart";
	411	reg = <0x0 0x2970000 0x0 0x1000>;
	412	interrupts = <0 50 0x4>;
	413	clocks = <&clockgen 4 0>;
	414	clock-names = "ipg";
	415	status = "disabled";
	416	};
	417
	418	lpuart3: serial@2980000 {
	419	compatible = "fsl,ls1021a-lpuart";
	420	reg = <0x0 0x2980000 0x0 0x1000>;
	421	interrupts = <0 51 0x4>;
	422	clocks = <&clockgen 4 0>;
	423	clock-names = "ipg";
	424	status = "disabled";
	425	};
	426
	427	lpuart4: serial@2990000 {
	428	compatible = "fsl,ls1021a-lpuart";
	429	reg = <0x0 0x2990000 0x0 0x1000>;
	430	interrupts = <0 52 0x4>;
	431	clocks = <&clockgen 4 0>;
	432	clock-names = "ipg";
	433	status = "disabled";
	434	};
	435
	436	lpuart5: serial@29a0000 {
	437	compatible = "fsl,ls1021a-lpuart";
	438	reg = <0x0 0x29a0000 0x0 0x1000>;
	439	interrupts = <0 53 0x4>;
	440	clocks = <&clockgen 4 0>;
	441	clock-names = "ipg";
	442	status = "disabled";
	443	};
	444
	445	wdog0: wdog@2ad0000 {
	446	compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
447	reg = <0x0 0x2ad0000 0x0 0x10000>;
448	interrupts = <0 83 0x4>;
449	clocks = <&clockgen 4 0>;
450	clock-names = "wdog";
451	big-endian;
452	};
453
454	edma0: edma@2c00000 {
455	#dma-cells = <2>;
456	compatible = "fsl,vf610-edma";
457	reg = <0x0 0x2c00000 0x0 0x10000>,
458	<0x0 0x2c10000 0x0 0x10000>,
459	<0x0 0x2c20000 0x0 0x10000>;
460	interrupts = <0 103 0x4>,
461	<0 103 0x4>;
462	interrupt-names = "edma-tx", "edma-err";
463	dma-channels = <32>;
464	big-endian;
465	clock-names = "dmamux0", "dmamux1";
466	clocks = <&clockgen 4 0>,
467	<&clockgen 4 0>;
468	};
469
470	usb0: usb3@2f00000 {
471	compatible = "snps,dwc3";
472	reg = <0x0 0x2f00000 0x0 0x10000>;
473	interrupts = <0 60 0x4>;
474	dr_mode = "host";
4c1d9ea7	475	snps,quirk-frame-length-adjustment = <0x20>;
bf26225f	476	snps,dis_rxdet_inp3_quirk;
6d453cd2 MH	477	};
	478
	479	usb1: usb3@3000000 {
	480	compatible = "snps,dwc3";
	481	reg = <0x0 0x3000000 0x0 0x10000>;
	482	interrupts = <0 61 0x4>;
	483	dr_mode = "host";
4c1d9ea7	484	snps,quirk-frame-length-adjustment = <0x20>;
bf26225f	485	snps,dis_rxdet_inp3_quirk;
6d453cd2 MH	486	};
	487
	488	usb2: usb3@3100000 {
	489	compatible = "snps,dwc3";
	490	reg = <0x0 0x3100000 0x0 0x10000>;
	491	interrupts = <0 63 0x4>;
	492	dr_mode = "host";
4c1d9ea7	493	snps,quirk-frame-length-adjustment = <0x20>;
bf26225f	494	snps,dis_rxdet_inp3_quirk;
6d453cd2 MH	495	};
	496
	497	sata: sata@3200000 {
	498	compatible = "fsl,ls1043a-ahci", "fsl,ls1021a-ahci";
	499	reg = <0x0 0x3200000 0x0 0x10000>;
	500	interrupts = <0 69 0x4>;
	501	clocks = <&clockgen 4 0>;
	502	};
	503
	504	msi1: msi-controller1@1571000 {
	505	compatible = "fsl,1s1043a-msi";
	506	reg = <0x0 0x1571000 0x0 0x8>;
	507	msi-controller;
	508	interrupts = <0 116 0x4>;
	509	};
	510
	511	msi2: msi-controller2@1572000 {
	512	compatible = "fsl,1s1043a-msi";
	513	reg = <0x0 0x1572000 0x0 0x8>;
	514	msi-controller;
	515	interrupts = <0 126 0x4>;
	516	};
	517
	518	msi3: msi-controller3@1573000 {
	519	compatible = "fsl,1s1043a-msi";
	520	reg = <0x0 0x1573000 0x0 0x8>;
	521	msi-controller;
	522	interrupts = <0 160 0x4>;
	523	};
	524
	525	pcie@3400000 {
	526	compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
	527	reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
	528	0x40 0x00000000 0x0 0x00002000>; /* configuration space */
	529	reg-names = "regs", "config";
	530	interrupts = <0 118 0x4>, /* controller interrupt */
	531	<0 117 0x4>; /* PME interrupt */
	532	interrupt-names = "intr", "pme";
	533	#address-cells = <3>;
	534	#size-cells = <2>;
	535	device_type = "pci";
f8ed1d9b	536	dma-coherent;
6d453cd2 MH	537	num-lanes = <4>;
	538	bus-range = <0x0 0xff>;
	539	ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
	540	0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
	541	msi-parent = <&msi1>;
	542	#interrupt-cells = <1>;
	543	interrupt-map-mask = <0 0 0 7>;
	544	interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
	545	<0000 0 0 2 &gic 0 111 0x4>,
	546	<0000 0 0 3 &gic 0 112 0x4>,
	547	<0000 0 0 4 &gic 0 113 0x4>;
	548	};
	549
	550	pcie@3500000 {
	551	compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
	552	reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
	553	0x48 0x00000000 0x0 0x00002000>; /* configuration space */
	554	reg-names = "regs", "config";
	555	interrupts = <0 128 0x4>,
	556	<0 127 0x4>;
	557	interrupt-names = "intr", "pme";
	558	#address-cells = <3>;
	559	#size-cells = <2>;
	560	device_type = "pci";
f8ed1d9b	561	dma-coherent;
6d453cd2 MH	562	num-lanes = <2>;
	563	bus-range = <0x0 0xff>;
	564	ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
	565	0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
	566	msi-parent = <&msi2>;
	567	#interrupt-cells = <1>;
	568	interrupt-map-mask = <0 0 0 7>;
	569	interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
	570	<0000 0 0 2 &gic 0 121 0x4>,
	571	<0000 0 0 3 &gic 0 122 0x4>,
	572	<0000 0 0 4 &gic 0 123 0x4>;
	573	};
	574
	575	pcie@3600000 {
	576	compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
	577	reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
	578	0x50 0x00000000 0x0 0x00002000>; /* configuration space */
	579	reg-names = "regs", "config";
	580	interrupts = <0 162 0x4>,
	581	<0 161 0x4>;
	582	interrupt-names = "intr", "pme";
	583	#address-cells = <3>;
	584	#size-cells = <2>;
	585	device_type = "pci";
f8ed1d9b	586	dma-coherent;
6d453cd2 MH	587	num-lanes = <2>;
	588	bus-range = <0x0 0xff>;
	589	ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
	590	0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
	591	msi-parent = <&msi3>;
	592	#interrupt-cells = <1>;
	593	interrupt-map-mask = <0 0 0 7>;
	594	interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
	595	<0000 0 0 2 &gic 0 155 0x4>,
	596	<0000 0 0 3 &gic 0 156 0x4>,
	597	<0000 0 0 4 &gic 0 157 0x4>;
	598	};
	599	};
	600
	601	};