Commit | Line | Data |
---|---|---|
ee877b53 VK |
1 | /* |
2 | * dts file for AppliedMicro (APM) X-Gene Storm SOC | |
3 | * | |
4 | * Copyright (C) 2013, Applied Micro Circuits Corporation | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License as | |
8 | * published by the Free Software Foundation; either version 2 of | |
9 | * the License, or (at your option) any later version. | |
10 | */ | |
11 | ||
12 | / { | |
13 | compatible = "apm,xgene-storm"; | |
14 | interrupt-parent = <&gic>; | |
15 | #address-cells = <2>; | |
16 | #size-cells = <2>; | |
17 | ||
18 | cpus { | |
19 | #address-cells = <2>; | |
20 | #size-cells = <0>; | |
21 | ||
22 | cpu@000 { | |
23 | device_type = "cpu"; | |
24 | compatible = "apm,potenza", "arm,armv8"; | |
25 | reg = <0x0 0x000>; | |
26 | enable-method = "spin-table"; | |
27 | cpu-release-addr = <0x1 0x0000fff8>; | |
8000bc3f | 28 | next-level-cache = <&xgene_L2_0>; |
ee877b53 VK |
29 | }; |
30 | cpu@001 { | |
31 | device_type = "cpu"; | |
32 | compatible = "apm,potenza", "arm,armv8"; | |
33 | reg = <0x0 0x001>; | |
34 | enable-method = "spin-table"; | |
35 | cpu-release-addr = <0x1 0x0000fff8>; | |
8000bc3f | 36 | next-level-cache = <&xgene_L2_0>; |
ee877b53 VK |
37 | }; |
38 | cpu@100 { | |
39 | device_type = "cpu"; | |
40 | compatible = "apm,potenza", "arm,armv8"; | |
41 | reg = <0x0 0x100>; | |
42 | enable-method = "spin-table"; | |
43 | cpu-release-addr = <0x1 0x0000fff8>; | |
8000bc3f | 44 | next-level-cache = <&xgene_L2_1>; |
ee877b53 VK |
45 | }; |
46 | cpu@101 { | |
47 | device_type = "cpu"; | |
48 | compatible = "apm,potenza", "arm,armv8"; | |
49 | reg = <0x0 0x101>; | |
50 | enable-method = "spin-table"; | |
51 | cpu-release-addr = <0x1 0x0000fff8>; | |
8000bc3f | 52 | next-level-cache = <&xgene_L2_1>; |
ee877b53 VK |
53 | }; |
54 | cpu@200 { | |
55 | device_type = "cpu"; | |
56 | compatible = "apm,potenza", "arm,armv8"; | |
57 | reg = <0x0 0x200>; | |
58 | enable-method = "spin-table"; | |
59 | cpu-release-addr = <0x1 0x0000fff8>; | |
8000bc3f | 60 | next-level-cache = <&xgene_L2_2>; |
ee877b53 VK |
61 | }; |
62 | cpu@201 { | |
63 | device_type = "cpu"; | |
64 | compatible = "apm,potenza", "arm,armv8"; | |
65 | reg = <0x0 0x201>; | |
66 | enable-method = "spin-table"; | |
67 | cpu-release-addr = <0x1 0x0000fff8>; | |
8000bc3f | 68 | next-level-cache = <&xgene_L2_2>; |
ee877b53 VK |
69 | }; |
70 | cpu@300 { | |
71 | device_type = "cpu"; | |
72 | compatible = "apm,potenza", "arm,armv8"; | |
73 | reg = <0x0 0x300>; | |
74 | enable-method = "spin-table"; | |
75 | cpu-release-addr = <0x1 0x0000fff8>; | |
8000bc3f | 76 | next-level-cache = <&xgene_L2_3>; |
ee877b53 VK |
77 | }; |
78 | cpu@301 { | |
79 | device_type = "cpu"; | |
80 | compatible = "apm,potenza", "arm,armv8"; | |
81 | reg = <0x0 0x301>; | |
82 | enable-method = "spin-table"; | |
83 | cpu-release-addr = <0x1 0x0000fff8>; | |
8000bc3f DD |
84 | next-level-cache = <&xgene_L2_3>; |
85 | }; | |
86 | xgene_L2_0: l2-cache-0 { | |
87 | compatible = "cache"; | |
88 | }; | |
89 | xgene_L2_1: l2-cache-1 { | |
90 | compatible = "cache"; | |
91 | }; | |
92 | xgene_L2_2: l2-cache-2 { | |
93 | compatible = "cache"; | |
94 | }; | |
95 | xgene_L2_3: l2-cache-3 { | |
96 | compatible = "cache"; | |
ee877b53 VK |
97 | }; |
98 | }; | |
99 | ||
100 | gic: interrupt-controller@78010000 { | |
101 | compatible = "arm,cortex-a15-gic"; | |
102 | #interrupt-cells = <3>; | |
103 | interrupt-controller; | |
104 | reg = <0x0 0x78010000 0x0 0x1000>, /* GIC Dist */ | |
105 | <0x0 0x78020000 0x0 0x1000>, /* GIC CPU */ | |
106 | <0x0 0x78040000 0x0 0x2000>, /* GIC VCPU Control */ | |
107 | <0x0 0x78060000 0x0 0x2000>; /* GIC VCPU */ | |
108 | interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */ | |
109 | }; | |
110 | ||
111 | timer { | |
112 | compatible = "arm,armv8-timer"; | |
113 | interrupts = <1 0 0xff01>, /* Secure Phys IRQ */ | |
114 | <1 13 0xff01>, /* Non-secure Phys IRQ */ | |
115 | <1 14 0xff01>, /* Virt IRQ */ | |
116 | <1 15 0xff01>; /* Hyp IRQ */ | |
117 | clock-frequency = <50000000>; | |
118 | }; | |
119 | ||
7434f42b FK |
120 | pmu { |
121 | compatible = "apm,potenza-pmu", "arm,armv8-pmuv3"; | |
122 | interrupts = <1 12 0xff04>; | |
123 | }; | |
124 | ||
ee877b53 VK |
125 | soc { |
126 | compatible = "simple-bus"; | |
127 | #address-cells = <2>; | |
128 | #size-cells = <2>; | |
129 | ranges; | |
74e353e1 | 130 | dma-ranges = <0x0 0x0 0x0 0x0 0x400 0x0>; |
ee877b53 | 131 | |
3eb15d84 LH |
132 | clocks { |
133 | #address-cells = <2>; | |
134 | #size-cells = <2>; | |
135 | ranges; | |
136 | refclk: refclk { | |
137 | compatible = "fixed-clock"; | |
138 | #clock-cells = <1>; | |
139 | clock-frequency = <100000000>; | |
140 | clock-output-names = "refclk"; | |
141 | }; | |
142 | ||
143 | pcppll: pcppll@17000100 { | |
144 | compatible = "apm,xgene-pcppll-clock"; | |
145 | #clock-cells = <1>; | |
146 | clocks = <&refclk 0>; | |
147 | clock-names = "pcppll"; | |
148 | reg = <0x0 0x17000100 0x0 0x1000>; | |
149 | clock-output-names = "pcppll"; | |
150 | type = <0>; | |
151 | }; | |
152 | ||
153 | socpll: socpll@17000120 { | |
154 | compatible = "apm,xgene-socpll-clock"; | |
155 | #clock-cells = <1>; | |
156 | clocks = <&refclk 0>; | |
157 | clock-names = "socpll"; | |
158 | reg = <0x0 0x17000120 0x0 0x1000>; | |
159 | clock-output-names = "socpll"; | |
160 | type = <1>; | |
161 | }; | |
162 | ||
163 | socplldiv2: socplldiv2 { | |
164 | compatible = "fixed-factor-clock"; | |
165 | #clock-cells = <1>; | |
166 | clocks = <&socpll 0>; | |
167 | clock-names = "socplldiv2"; | |
168 | clock-mult = <1>; | |
169 | clock-div = <2>; | |
170 | clock-output-names = "socplldiv2"; | |
171 | }; | |
172 | ||
b0e7a85a | 173 | ahbclk: ahbclk@17000000 { |
8f74e861 ST |
174 | compatible = "apm,xgene-device-clock"; |
175 | #clock-cells = <1>; | |
176 | clocks = <&socplldiv2 0>; | |
b0e7a85a DD |
177 | reg = <0x0 0x17000000 0x0 0x2000>; |
178 | reg-names = "div-reg"; | |
8f74e861 ST |
179 | divider-offset = <0x164>; |
180 | divider-width = <0x5>; | |
181 | divider-shift = <0x0>; | |
182 | clock-output-names = "ahbclk"; | |
183 | }; | |
184 | ||
185 | sdioclk: sdioclk@1f2ac000 { | |
186 | compatible = "apm,xgene-device-clock"; | |
187 | #clock-cells = <1>; | |
188 | clocks = <&socplldiv2 0>; | |
189 | reg = <0x0 0x1f2ac000 0x0 0x1000 | |
190 | 0x0 0x17000000 0x0 0x2000>; | |
191 | reg-names = "csr-reg", "div-reg"; | |
192 | csr-offset = <0x0>; | |
193 | csr-mask = <0x2>; | |
194 | enable-offset = <0x8>; | |
195 | enable-mask = <0x2>; | |
196 | divider-offset = <0x178>; | |
197 | divider-width = <0x8>; | |
198 | divider-shift = <0x0>; | |
199 | clock-output-names = "sdioclk"; | |
200 | }; | |
201 | ||
3eb15d84 LH |
202 | qmlclk: qmlclk { |
203 | compatible = "apm,xgene-device-clock"; | |
204 | #clock-cells = <1>; | |
205 | clocks = <&socplldiv2 0>; | |
206 | clock-names = "qmlclk"; | |
207 | reg = <0x0 0x1703C000 0x0 0x1000>; | |
208 | reg-names = "csr-reg"; | |
209 | clock-output-names = "qmlclk"; | |
210 | }; | |
211 | ||
212 | ethclk: ethclk { | |
213 | compatible = "apm,xgene-device-clock"; | |
214 | #clock-cells = <1>; | |
215 | clocks = <&socplldiv2 0>; | |
216 | clock-names = "ethclk"; | |
217 | reg = <0x0 0x17000000 0x0 0x1000>; | |
218 | reg-names = "div-reg"; | |
219 | divider-offset = <0x238>; | |
220 | divider-width = <0x9>; | |
221 | divider-shift = <0x0>; | |
222 | clock-output-names = "ethclk"; | |
223 | }; | |
224 | ||
3d390425 | 225 | menetclk: menetclk { |
3eb15d84 LH |
226 | compatible = "apm,xgene-device-clock"; |
227 | #clock-cells = <1>; | |
228 | clocks = <ðclk 0>; | |
3eb15d84 LH |
229 | reg = <0x0 0x1702C000 0x0 0x1000>; |
230 | reg-names = "csr-reg"; | |
3d390425 | 231 | clock-output-names = "menetclk"; |
3eb15d84 | 232 | }; |
71b70ee9 | 233 | |
4c2e7f09 IS |
234 | sge0clk: sge0clk@1f21c000 { |
235 | compatible = "apm,xgene-device-clock"; | |
236 | #clock-cells = <1>; | |
237 | clocks = <&socplldiv2 0>; | |
238 | reg = <0x0 0x1f21c000 0x0 0x1000>; | |
239 | reg-names = "csr-reg"; | |
240 | csr-mask = <0x3>; | |
241 | clock-output-names = "sge0clk"; | |
242 | }; | |
243 | ||
2d33394e KC |
244 | sge1clk: sge1clk@1f21c000 { |
245 | compatible = "apm,xgene-device-clock"; | |
246 | #clock-cells = <1>; | |
247 | clocks = <&socplldiv2 0>; | |
248 | reg = <0x0 0x1f21c000 0x0 0x1000>; | |
249 | reg-names = "csr-reg"; | |
250 | csr-mask = <0xc>; | |
251 | clock-output-names = "sge1clk"; | |
252 | }; | |
253 | ||
5fb32417 IS |
254 | xge0clk: xge0clk@1f61c000 { |
255 | compatible = "apm,xgene-device-clock"; | |
256 | #clock-cells = <1>; | |
257 | clocks = <&socplldiv2 0>; | |
258 | reg = <0x0 0x1f61c000 0x0 0x1000>; | |
259 | reg-names = "csr-reg"; | |
260 | csr-mask = <0x3>; | |
261 | clock-output-names = "xge0clk"; | |
262 | }; | |
263 | ||
e63c7a09 IS |
264 | xge1clk: xge1clk@1f62c000 { |
265 | compatible = "apm,xgene-device-clock"; | |
266 | status = "disabled"; | |
267 | #clock-cells = <1>; | |
268 | clocks = <&socplldiv2 0>; | |
269 | reg = <0x0 0x1f62c000 0x0 0x1000>; | |
270 | reg-names = "csr-reg"; | |
271 | csr-mask = <0x3>; | |
272 | clock-output-names = "xge1clk"; | |
273 | }; | |
274 | ||
71b70ee9 LH |
275 | sataphy1clk: sataphy1clk@1f21c000 { |
276 | compatible = "apm,xgene-device-clock"; | |
277 | #clock-cells = <1>; | |
278 | clocks = <&socplldiv2 0>; | |
279 | reg = <0x0 0x1f21c000 0x0 0x1000>; | |
280 | reg-names = "csr-reg"; | |
281 | clock-output-names = "sataphy1clk"; | |
282 | status = "disabled"; | |
283 | csr-offset = <0x4>; | |
284 | csr-mask = <0x00>; | |
285 | enable-offset = <0x0>; | |
286 | enable-mask = <0x06>; | |
287 | }; | |
288 | ||
289 | sataphy2clk: sataphy1clk@1f22c000 { | |
290 | compatible = "apm,xgene-device-clock"; | |
291 | #clock-cells = <1>; | |
292 | clocks = <&socplldiv2 0>; | |
293 | reg = <0x0 0x1f22c000 0x0 0x1000>; | |
294 | reg-names = "csr-reg"; | |
295 | clock-output-names = "sataphy2clk"; | |
296 | status = "ok"; | |
297 | csr-offset = <0x4>; | |
298 | csr-mask = <0x3a>; | |
299 | enable-offset = <0x0>; | |
300 | enable-mask = <0x06>; | |
301 | }; | |
302 | ||
303 | sataphy3clk: sataphy1clk@1f23c000 { | |
304 | compatible = "apm,xgene-device-clock"; | |
305 | #clock-cells = <1>; | |
306 | clocks = <&socplldiv2 0>; | |
307 | reg = <0x0 0x1f23c000 0x0 0x1000>; | |
308 | reg-names = "csr-reg"; | |
309 | clock-output-names = "sataphy3clk"; | |
310 | status = "ok"; | |
311 | csr-offset = <0x4>; | |
312 | csr-mask = <0x3a>; | |
313 | enable-offset = <0x0>; | |
314 | enable-mask = <0x06>; | |
315 | }; | |
db8c0286 LH |
316 | |
317 | sata01clk: sata01clk@1f21c000 { | |
318 | compatible = "apm,xgene-device-clock"; | |
319 | #clock-cells = <1>; | |
320 | clocks = <&socplldiv2 0>; | |
321 | reg = <0x0 0x1f21c000 0x0 0x1000>; | |
322 | reg-names = "csr-reg"; | |
323 | clock-output-names = "sata01clk"; | |
324 | csr-offset = <0x4>; | |
325 | csr-mask = <0x05>; | |
326 | enable-offset = <0x0>; | |
327 | enable-mask = <0x39>; | |
328 | }; | |
329 | ||
330 | sata23clk: sata23clk@1f22c000 { | |
331 | compatible = "apm,xgene-device-clock"; | |
332 | #clock-cells = <1>; | |
333 | clocks = <&socplldiv2 0>; | |
334 | reg = <0x0 0x1f22c000 0x0 0x1000>; | |
335 | reg-names = "csr-reg"; | |
336 | clock-output-names = "sata23clk"; | |
337 | csr-offset = <0x4>; | |
338 | csr-mask = <0x05>; | |
339 | enable-offset = <0x0>; | |
340 | enable-mask = <0x39>; | |
341 | }; | |
342 | ||
343 | sata45clk: sata45clk@1f23c000 { | |
344 | compatible = "apm,xgene-device-clock"; | |
345 | #clock-cells = <1>; | |
346 | clocks = <&socplldiv2 0>; | |
347 | reg = <0x0 0x1f23c000 0x0 0x1000>; | |
348 | reg-names = "csr-reg"; | |
349 | clock-output-names = "sata45clk"; | |
350 | csr-offset = <0x4>; | |
351 | csr-mask = <0x05>; | |
352 | enable-offset = <0x0>; | |
353 | enable-mask = <0x39>; | |
354 | }; | |
652ba666 LH |
355 | |
356 | rtcclk: rtcclk@17000000 { | |
357 | compatible = "apm,xgene-device-clock"; | |
358 | #clock-cells = <1>; | |
359 | clocks = <&socplldiv2 0>; | |
360 | reg = <0x0 0x17000000 0x0 0x2000>; | |
361 | reg-names = "csr-reg"; | |
362 | csr-offset = <0xc>; | |
363 | csr-mask = <0x2>; | |
364 | enable-offset = <0x10>; | |
365 | enable-mask = <0x2>; | |
366 | clock-output-names = "rtcclk"; | |
367 | }; | |
ab818739 FK |
368 | |
369 | rngpkaclk: rngpkaclk@17000000 { | |
370 | compatible = "apm,xgene-device-clock"; | |
371 | #clock-cells = <1>; | |
372 | clocks = <&socplldiv2 0>; | |
373 | reg = <0x0 0x17000000 0x0 0x2000>; | |
374 | reg-names = "csr-reg"; | |
375 | csr-offset = <0xc>; | |
376 | csr-mask = <0x10>; | |
377 | enable-offset = <0x10>; | |
378 | enable-mask = <0x10>; | |
379 | clock-output-names = "rngpkaclk"; | |
380 | }; | |
80213c03 | 381 | |
767ebaff TI |
382 | pcie0clk: pcie0clk@1f2bc000 { |
383 | status = "disabled"; | |
384 | compatible = "apm,xgene-device-clock"; | |
385 | #clock-cells = <1>; | |
386 | clocks = <&socplldiv2 0>; | |
387 | reg = <0x0 0x1f2bc000 0x0 0x1000>; | |
388 | reg-names = "csr-reg"; | |
389 | clock-output-names = "pcie0clk"; | |
390 | }; | |
391 | ||
392 | pcie1clk: pcie1clk@1f2cc000 { | |
393 | status = "disabled"; | |
394 | compatible = "apm,xgene-device-clock"; | |
395 | #clock-cells = <1>; | |
396 | clocks = <&socplldiv2 0>; | |
397 | reg = <0x0 0x1f2cc000 0x0 0x1000>; | |
398 | reg-names = "csr-reg"; | |
399 | clock-output-names = "pcie1clk"; | |
400 | }; | |
401 | ||
402 | pcie2clk: pcie2clk@1f2dc000 { | |
403 | status = "disabled"; | |
404 | compatible = "apm,xgene-device-clock"; | |
405 | #clock-cells = <1>; | |
406 | clocks = <&socplldiv2 0>; | |
407 | reg = <0x0 0x1f2dc000 0x0 0x1000>; | |
408 | reg-names = "csr-reg"; | |
409 | clock-output-names = "pcie2clk"; | |
410 | }; | |
411 | ||
412 | pcie3clk: pcie3clk@1f50c000 { | |
413 | status = "disabled"; | |
414 | compatible = "apm,xgene-device-clock"; | |
415 | #clock-cells = <1>; | |
416 | clocks = <&socplldiv2 0>; | |
417 | reg = <0x0 0x1f50c000 0x0 0x1000>; | |
418 | reg-names = "csr-reg"; | |
419 | clock-output-names = "pcie3clk"; | |
420 | }; | |
421 | ||
422 | pcie4clk: pcie4clk@1f51c000 { | |
423 | status = "disabled"; | |
424 | compatible = "apm,xgene-device-clock"; | |
425 | #clock-cells = <1>; | |
426 | clocks = <&socplldiv2 0>; | |
427 | reg = <0x0 0x1f51c000 0x0 0x1000>; | |
428 | reg-names = "csr-reg"; | |
429 | clock-output-names = "pcie4clk"; | |
430 | }; | |
74e353e1 RPS |
431 | |
432 | dmaclk: dmaclk@1f27c000 { | |
433 | compatible = "apm,xgene-device-clock"; | |
434 | #clock-cells = <1>; | |
435 | clocks = <&socplldiv2 0>; | |
436 | reg = <0x0 0x1f27c000 0x0 0x1000>; | |
437 | reg-names = "csr-reg"; | |
438 | clock-output-names = "dmaclk"; | |
439 | }; | |
62ff9683 DD |
440 | |
441 | i2cclk: i2cclk@17000000 { | |
442 | status = "disabled"; | |
443 | compatible = "apm,xgene-device-clock"; | |
444 | #clock-cells = <1>; | |
445 | clocks = <&ahbclk 0>; | |
446 | reg = <0x0 0x17000000 0x0 0x2000>; | |
447 | reg-names = "csr-reg"; | |
448 | csr-offset = <0xc>; | |
449 | csr-mask = <0x4>; | |
450 | enable-offset = <0x10>; | |
451 | enable-mask = <0x4>; | |
452 | clock-output-names = "i2cclk"; | |
453 | }; | |
767ebaff TI |
454 | }; |
455 | ||
e1e6e5c4 DD |
456 | msi: msi@79000000 { |
457 | compatible = "apm,xgene1-msi"; | |
458 | msi-controller; | |
459 | reg = <0x00 0x79000000 0x0 0x900000>; | |
460 | interrupts = < 0x0 0x10 0x4 | |
461 | 0x0 0x11 0x4 | |
462 | 0x0 0x12 0x4 | |
463 | 0x0 0x13 0x4 | |
464 | 0x0 0x14 0x4 | |
465 | 0x0 0x15 0x4 | |
466 | 0x0 0x16 0x4 | |
467 | 0x0 0x17 0x4 | |
468 | 0x0 0x18 0x4 | |
469 | 0x0 0x19 0x4 | |
470 | 0x0 0x1a 0x4 | |
471 | 0x0 0x1b 0x4 | |
472 | 0x0 0x1c 0x4 | |
473 | 0x0 0x1d 0x4 | |
474 | 0x0 0x1e 0x4 | |
475 | 0x0 0x1f 0x4>; | |
476 | }; | |
477 | ||
5c3a87e3 FK |
478 | scu: system-clk-controller@17000000 { |
479 | compatible = "apm,xgene-scu","syscon"; | |
480 | reg = <0x0 0x17000000 0x0 0x400>; | |
481 | }; | |
482 | ||
483 | reboot: reboot@17000014 { | |
484 | compatible = "syscon-reboot"; | |
485 | regmap = <&scu>; | |
486 | offset = <0x14>; | |
487 | mask = <0x1>; | |
488 | }; | |
489 | ||
8f2ae6f3 LH |
490 | csw: csw@7e200000 { |
491 | compatible = "apm,xgene-csw", "syscon"; | |
492 | reg = <0x0 0x7e200000 0x0 0x1000>; | |
493 | }; | |
494 | ||
495 | mcba: mcba@7e700000 { | |
496 | compatible = "apm,xgene-mcb", "syscon"; | |
497 | reg = <0x0 0x7e700000 0x0 0x1000>; | |
498 | }; | |
499 | ||
500 | mcbb: mcbb@7e720000 { | |
501 | compatible = "apm,xgene-mcb", "syscon"; | |
502 | reg = <0x0 0x7e720000 0x0 0x1000>; | |
503 | }; | |
504 | ||
505 | efuse: efuse@1054a000 { | |
506 | compatible = "apm,xgene-efuse", "syscon"; | |
507 | reg = <0x0 0x1054a000 0x0 0x20>; | |
508 | }; | |
509 | ||
510 | edac@78800000 { | |
511 | compatible = "apm,xgene-edac"; | |
512 | #address-cells = <2>; | |
513 | #size-cells = <2>; | |
514 | ranges; | |
515 | regmap-csw = <&csw>; | |
516 | regmap-mcba = <&mcba>; | |
517 | regmap-mcbb = <&mcbb>; | |
518 | regmap-efuse = <&efuse>; | |
519 | reg = <0x0 0x78800000 0x0 0x100>; | |
520 | interrupts = <0x0 0x20 0x4>, | |
521 | <0x0 0x21 0x4>, | |
522 | <0x0 0x27 0x4>; | |
523 | ||
524 | edacmc@7e800000 { | |
525 | compatible = "apm,xgene-edac-mc"; | |
526 | reg = <0x0 0x7e800000 0x0 0x1000>; | |
527 | memory-controller = <0>; | |
528 | }; | |
529 | ||
530 | edacmc@7e840000 { | |
531 | compatible = "apm,xgene-edac-mc"; | |
532 | reg = <0x0 0x7e840000 0x0 0x1000>; | |
533 | memory-controller = <1>; | |
534 | }; | |
535 | ||
536 | edacmc@7e880000 { | |
537 | compatible = "apm,xgene-edac-mc"; | |
538 | reg = <0x0 0x7e880000 0x0 0x1000>; | |
539 | memory-controller = <2>; | |
540 | }; | |
541 | ||
542 | edacmc@7e8c0000 { | |
543 | compatible = "apm,xgene-edac-mc"; | |
544 | reg = <0x0 0x7e8c0000 0x0 0x1000>; | |
545 | memory-controller = <3>; | |
546 | }; | |
547 | ||
548 | edacpmd@7c000000 { | |
549 | compatible = "apm,xgene-edac-pmd"; | |
550 | reg = <0x0 0x7c000000 0x0 0x200000>; | |
551 | pmd-controller = <0>; | |
552 | }; | |
553 | ||
554 | edacpmd@7c200000 { | |
555 | compatible = "apm,xgene-edac-pmd"; | |
556 | reg = <0x0 0x7c200000 0x0 0x200000>; | |
557 | pmd-controller = <1>; | |
558 | }; | |
559 | ||
560 | edacpmd@7c400000 { | |
561 | compatible = "apm,xgene-edac-pmd"; | |
562 | reg = <0x0 0x7c400000 0x0 0x200000>; | |
563 | pmd-controller = <2>; | |
564 | }; | |
565 | ||
566 | edacpmd@7c600000 { | |
567 | compatible = "apm,xgene-edac-pmd"; | |
568 | reg = <0x0 0x7c600000 0x0 0x200000>; | |
569 | pmd-controller = <3>; | |
570 | }; | |
043cba96 LH |
571 | |
572 | edacl3@7e600000 { | |
573 | compatible = "apm,xgene-edac-l3"; | |
574 | reg = <0x0 0x7e600000 0x0 0x1000>; | |
575 | }; | |
576 | ||
577 | edacsoc@7e930000 { | |
578 | compatible = "apm,xgene-edac-soc-v1"; | |
579 | reg = <0x0 0x7e930000 0x0 0x1000>; | |
580 | }; | |
8f2ae6f3 LH |
581 | }; |
582 | ||
767ebaff TI |
583 | pcie0: pcie@1f2b0000 { |
584 | status = "disabled"; | |
585 | device_type = "pci"; | |
586 | compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; | |
587 | #interrupt-cells = <1>; | |
588 | #size-cells = <2>; | |
589 | #address-cells = <3>; | |
590 | reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */ | |
591 | 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */ | |
592 | reg-names = "csr", "cfg"; | |
593 | ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */ | |
80bb3eda DD |
594 | 0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000 /* mem */ |
595 | 0x43000000 0xf0 0x00000000 0xf0 0x00000000 0x10 0x00000000>; /* mem */ | |
767ebaff TI |
596 | dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 |
597 | 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; | |
598 | interrupt-map-mask = <0x0 0x0 0x0 0x7>; | |
599 | interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1 | |
600 | 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1 | |
601 | 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1 | |
602 | 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>; | |
603 | dma-coherent; | |
604 | clocks = <&pcie0clk 0>; | |
e1e6e5c4 | 605 | msi-parent = <&msi>; |
767ebaff TI |
606 | }; |
607 | ||
608 | pcie1: pcie@1f2c0000 { | |
609 | status = "disabled"; | |
610 | device_type = "pci"; | |
611 | compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; | |
612 | #interrupt-cells = <1>; | |
613 | #size-cells = <2>; | |
614 | #address-cells = <3>; | |
615 | reg = < 0x00 0x1f2c0000 0x0 0x00010000 /* Controller registers */ | |
616 | 0xd0 0xd0000000 0x0 0x00040000>; /* PCI config space */ | |
617 | reg-names = "csr", "cfg"; | |
80bb3eda DD |
618 | ranges = <0x01000000 0x00 0x00000000 0xd0 0x10000000 0x00 0x00010000 /* io */ |
619 | 0x02000000 0x00 0x80000000 0xd1 0x80000000 0x00 0x80000000 /* mem */ | |
620 | 0x43000000 0xd8 0x00000000 0xd8 0x00000000 0x08 0x00000000>; /* mem */ | |
767ebaff TI |
621 | dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 |
622 | 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; | |
623 | interrupt-map-mask = <0x0 0x0 0x0 0x7>; | |
624 | interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x1 | |
625 | 0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x1 | |
626 | 0x0 0x0 0x0 0x3 &gic 0x0 0xca 0x1 | |
627 | 0x0 0x0 0x0 0x4 &gic 0x0 0xcb 0x1>; | |
628 | dma-coherent; | |
629 | clocks = <&pcie1clk 0>; | |
e1e6e5c4 | 630 | msi-parent = <&msi>; |
767ebaff TI |
631 | }; |
632 | ||
633 | pcie2: pcie@1f2d0000 { | |
634 | status = "disabled"; | |
635 | device_type = "pci"; | |
636 | compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; | |
637 | #interrupt-cells = <1>; | |
638 | #size-cells = <2>; | |
639 | #address-cells = <3>; | |
640 | reg = < 0x00 0x1f2d0000 0x0 0x00010000 /* Controller registers */ | |
641 | 0x90 0xd0000000 0x0 0x00040000>; /* PCI config space */ | |
642 | reg-names = "csr", "cfg"; | |
80bb3eda DD |
643 | ranges = <0x01000000 0x00 0x00000000 0x90 0x10000000 0x00 0x00010000 /* io */ |
644 | 0x02000000 0x00 0x80000000 0x91 0x80000000 0x00 0x80000000 /* mem */ | |
645 | 0x43000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>; /* mem */ | |
767ebaff TI |
646 | dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 |
647 | 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; | |
648 | interrupt-map-mask = <0x0 0x0 0x0 0x7>; | |
649 | interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x1 | |
650 | 0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x1 | |
651 | 0x0 0x0 0x0 0x3 &gic 0x0 0xd0 0x1 | |
652 | 0x0 0x0 0x0 0x4 &gic 0x0 0xd1 0x1>; | |
653 | dma-coherent; | |
654 | clocks = <&pcie2clk 0>; | |
e1e6e5c4 | 655 | msi-parent = <&msi>; |
767ebaff TI |
656 | }; |
657 | ||
658 | pcie3: pcie@1f500000 { | |
659 | status = "disabled"; | |
660 | device_type = "pci"; | |
661 | compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; | |
662 | #interrupt-cells = <1>; | |
663 | #size-cells = <2>; | |
664 | #address-cells = <3>; | |
665 | reg = < 0x00 0x1f500000 0x0 0x00010000 /* Controller registers */ | |
666 | 0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */ | |
667 | reg-names = "csr", "cfg"; | |
80bb3eda DD |
668 | ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000 /* io */ |
669 | 0x02000000 0x00 0x80000000 0xa1 0x80000000 0x00 0x80000000 /* mem */ | |
670 | 0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */ | |
767ebaff TI |
671 | dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 |
672 | 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; | |
673 | interrupt-map-mask = <0x0 0x0 0x0 0x7>; | |
674 | interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x1 | |
675 | 0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x1 | |
676 | 0x0 0x0 0x0 0x3 &gic 0x0 0xd6 0x1 | |
677 | 0x0 0x0 0x0 0x4 &gic 0x0 0xd7 0x1>; | |
678 | dma-coherent; | |
679 | clocks = <&pcie3clk 0>; | |
e1e6e5c4 | 680 | msi-parent = <&msi>; |
767ebaff TI |
681 | }; |
682 | ||
683 | pcie4: pcie@1f510000 { | |
684 | status = "disabled"; | |
685 | device_type = "pci"; | |
686 | compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; | |
687 | #interrupt-cells = <1>; | |
688 | #size-cells = <2>; | |
689 | #address-cells = <3>; | |
690 | reg = < 0x00 0x1f510000 0x0 0x00010000 /* Controller registers */ | |
691 | 0xc0 0xd0000000 0x0 0x00200000>; /* PCI config space */ | |
692 | reg-names = "csr", "cfg"; | |
80bb3eda DD |
693 | ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000 /* io */ |
694 | 0x02000000 0x00 0x80000000 0xc1 0x80000000 0x00 0x80000000 /* mem */ | |
695 | 0x43000000 0xc8 0x00000000 0xc8 0x00000000 0x08 0x00000000>; /* mem */ | |
767ebaff TI |
696 | dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 |
697 | 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; | |
698 | interrupt-map-mask = <0x0 0x0 0x0 0x7>; | |
699 | interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x1 | |
700 | 0x0 0x0 0x0 0x2 &gic 0x0 0xdb 0x1 | |
701 | 0x0 0x0 0x0 0x3 &gic 0x0 0xdc 0x1 | |
702 | 0x0 0x0 0x0 0x4 &gic 0x0 0xdd 0x1>; | |
703 | dma-coherent; | |
704 | clocks = <&pcie4clk 0>; | |
e1e6e5c4 | 705 | msi-parent = <&msi>; |
3eb15d84 LH |
706 | }; |
707 | ||
ee877b53 | 708 | serial0: serial@1c020000 { |
457ced84 | 709 | status = "disabled"; |
ee877b53 | 710 | device_type = "serial"; |
457ced84 | 711 | compatible = "ns16550a"; |
ee877b53 VK |
712 | reg = <0 0x1c020000 0x0 0x1000>; |
713 | reg-shift = <2>; | |
714 | clock-frequency = <10000000>; /* Updated by bootloader */ | |
715 | interrupt-parent = <&gic>; | |
716 | interrupts = <0x0 0x4c 0x4>; | |
717 | }; | |
71b70ee9 | 718 | |
457ced84 VK |
719 | serial1: serial@1c021000 { |
720 | status = "disabled"; | |
721 | device_type = "serial"; | |
722 | compatible = "ns16550a"; | |
723 | reg = <0 0x1c021000 0x0 0x1000>; | |
724 | reg-shift = <2>; | |
725 | clock-frequency = <10000000>; /* Updated by bootloader */ | |
726 | interrupt-parent = <&gic>; | |
727 | interrupts = <0x0 0x4d 0x4>; | |
728 | }; | |
729 | ||
730 | serial2: serial@1c022000 { | |
731 | status = "disabled"; | |
732 | device_type = "serial"; | |
733 | compatible = "ns16550a"; | |
734 | reg = <0 0x1c022000 0x0 0x1000>; | |
735 | reg-shift = <2>; | |
736 | clock-frequency = <10000000>; /* Updated by bootloader */ | |
737 | interrupt-parent = <&gic>; | |
738 | interrupts = <0x0 0x4e 0x4>; | |
739 | }; | |
740 | ||
741 | serial3: serial@1c023000 { | |
742 | status = "disabled"; | |
743 | device_type = "serial"; | |
744 | compatible = "ns16550a"; | |
745 | reg = <0 0x1c023000 0x0 0x1000>; | |
746 | reg-shift = <2>; | |
747 | clock-frequency = <10000000>; /* Updated by bootloader */ | |
748 | interrupt-parent = <&gic>; | |
749 | interrupts = <0x0 0x4f 0x4>; | |
750 | }; | |
751 | ||
8f74e861 ST |
752 | mmc0: mmc@1c000000 { |
753 | compatible = "arasan,sdhci-4.9a"; | |
754 | reg = <0x0 0x1c000000 0x0 0x100>; | |
755 | interrupts = <0x0 0x49 0x4>; | |
756 | dma-coherent; | |
757 | no-1-8-v; | |
758 | clock-names = "clk_xin", "clk_ahb"; | |
759 | clocks = <&sdioclk 0>, <&ahbclk 0>; | |
760 | }; | |
761 | ||
0a09223f DD |
762 | gfcgpio: gfcgpio0@1701c000 { |
763 | compatible = "apm,xgene-gpio"; | |
764 | reg = <0x0 0x1701c000 0x0 0x40>; | |
765 | gpio-controller; | |
766 | #gpio-cells = <2>; | |
767 | }; | |
768 | ||
e38ec5b9 DD |
769 | dwgpio: dwgpio@1c024000 { |
770 | compatible = "snps,dw-apb-gpio"; | |
771 | reg = <0x0 0x1c024000 0x0 0x1000>; | |
772 | reg-io-width = <4>; | |
773 | #address-cells = <1>; | |
774 | #size-cells = <0>; | |
775 | ||
776 | porta: gpio-controller@0 { | |
777 | compatible = "snps,dw-apb-gpio-port"; | |
778 | gpio-controller; | |
779 | snps,nr-gpios = <32>; | |
780 | reg = <0>; | |
781 | }; | |
782 | }; | |
783 | ||
62ff9683 DD |
784 | i2c0: i2c0@10512000 { |
785 | status = "disabled"; | |
786 | #address-cells = <1>; | |
787 | #size-cells = <0>; | |
788 | compatible = "snps,designware-i2c"; | |
789 | reg = <0x0 0x10512000 0x0 0x1000>; | |
790 | interrupts = <0 0x44 0x4>; | |
791 | #clock-cells = <1>; | |
792 | clocks = <&i2cclk 0>; | |
793 | bus_num = <0>; | |
794 | }; | |
795 | ||
71b70ee9 LH |
796 | phy1: phy@1f21a000 { |
797 | compatible = "apm,xgene-phy"; | |
798 | reg = <0x0 0x1f21a000 0x0 0x100>; | |
799 | #phy-cells = <1>; | |
800 | clocks = <&sataphy1clk 0>; | |
801 | status = "disabled"; | |
802 | apm,tx-boost-gain = <30 30 30 30 30 30>; | |
803 | apm,tx-eye-tuning = <2 10 10 2 10 10>; | |
804 | }; | |
805 | ||
806 | phy2: phy@1f22a000 { | |
807 | compatible = "apm,xgene-phy"; | |
808 | reg = <0x0 0x1f22a000 0x0 0x100>; | |
809 | #phy-cells = <1>; | |
810 | clocks = <&sataphy2clk 0>; | |
811 | status = "ok"; | |
812 | apm,tx-boost-gain = <30 30 30 30 30 30>; | |
813 | apm,tx-eye-tuning = <1 10 10 2 10 10>; | |
814 | }; | |
815 | ||
816 | phy3: phy@1f23a000 { | |
817 | compatible = "apm,xgene-phy"; | |
818 | reg = <0x0 0x1f23a000 0x0 0x100>; | |
819 | #phy-cells = <1>; | |
820 | clocks = <&sataphy3clk 0>; | |
821 | status = "ok"; | |
822 | apm,tx-boost-gain = <31 31 31 31 31 31>; | |
823 | apm,tx-eye-tuning = <2 10 10 2 10 10>; | |
824 | }; | |
db8c0286 LH |
825 | |
826 | sata1: sata@1a000000 { | |
827 | compatible = "apm,xgene-ahci"; | |
828 | reg = <0x0 0x1a000000 0x0 0x1000>, | |
829 | <0x0 0x1f210000 0x0 0x1000>, | |
830 | <0x0 0x1f21d000 0x0 0x1000>, | |
831 | <0x0 0x1f21e000 0x0 0x1000>, | |
832 | <0x0 0x1f217000 0x0 0x1000>; | |
833 | interrupts = <0x0 0x86 0x4>; | |
7a8d1ec1 | 834 | dma-coherent; |
db8c0286 LH |
835 | status = "disabled"; |
836 | clocks = <&sata01clk 0>; | |
837 | phys = <&phy1 0>; | |
838 | phy-names = "sata-phy"; | |
839 | }; | |
840 | ||
841 | sata2: sata@1a400000 { | |
842 | compatible = "apm,xgene-ahci"; | |
843 | reg = <0x0 0x1a400000 0x0 0x1000>, | |
844 | <0x0 0x1f220000 0x0 0x1000>, | |
845 | <0x0 0x1f22d000 0x0 0x1000>, | |
846 | <0x0 0x1f22e000 0x0 0x1000>, | |
847 | <0x0 0x1f227000 0x0 0x1000>; | |
848 | interrupts = <0x0 0x87 0x4>; | |
7a8d1ec1 | 849 | dma-coherent; |
db8c0286 LH |
850 | status = "ok"; |
851 | clocks = <&sata23clk 0>; | |
852 | phys = <&phy2 0>; | |
853 | phy-names = "sata-phy"; | |
854 | }; | |
855 | ||
856 | sata3: sata@1a800000 { | |
857 | compatible = "apm,xgene-ahci"; | |
858 | reg = <0x0 0x1a800000 0x0 0x1000>, | |
859 | <0x0 0x1f230000 0x0 0x1000>, | |
860 | <0x0 0x1f23d000 0x0 0x1000>, | |
861 | <0x0 0x1f23e000 0x0 0x1000>; | |
862 | interrupts = <0x0 0x88 0x4>; | |
7a8d1ec1 | 863 | dma-coherent; |
db8c0286 LH |
864 | status = "ok"; |
865 | clocks = <&sata45clk 0>; | |
866 | phys = <&phy3 0>; | |
867 | phy-names = "sata-phy"; | |
868 | }; | |
652ba666 | 869 | |
bd410233 DD |
870 | /* Do not change dwusb name, coded for backward compatibility */ |
871 | usb0: dwusb@19000000 { | |
872 | status = "disabled"; | |
873 | compatible = "snps,dwc3"; | |
874 | reg = <0x0 0x19000000 0x0 0x100000>; | |
875 | interrupts = <0x0 0x89 0x4>; | |
876 | dma-coherent; | |
877 | dr_mode = "host"; | |
878 | }; | |
879 | ||
880 | usb1: dwusb@19800000 { | |
881 | status = "disabled"; | |
882 | compatible = "snps,dwc3"; | |
883 | reg = <0x0 0x19800000 0x0 0x100000>; | |
884 | interrupts = <0x0 0x8a 0x4>; | |
885 | dma-coherent; | |
886 | dr_mode = "host"; | |
887 | }; | |
888 | ||
ea21feb3 V |
889 | sbgpio: sbgpio@17001000{ |
890 | compatible = "apm,xgene-gpio-sb"; | |
891 | reg = <0x0 0x17001000 0x0 0x400>; | |
892 | #gpio-cells = <2>; | |
893 | gpio-controller; | |
894 | interrupts = <0x0 0x28 0x1>, | |
895 | <0x0 0x29 0x1>, | |
896 | <0x0 0x2a 0x1>, | |
897 | <0x0 0x2b 0x1>, | |
898 | <0x0 0x2c 0x1>, | |
899 | <0x0 0x2d 0x1>; | |
900 | }; | |
901 | ||
652ba666 LH |
902 | rtc: rtc@10510000 { |
903 | compatible = "apm,xgene-rtc"; | |
904 | reg = <0x0 0x10510000 0x0 0x400>; | |
905 | interrupts = <0x0 0x46 0x4>; | |
906 | #clock-cells = <1>; | |
907 | clocks = <&rtcclk 0>; | |
908 | }; | |
3d390425 IS |
909 | |
910 | menet: ethernet@17020000 { | |
911 | compatible = "apm,xgene-enet"; | |
912 | status = "disabled"; | |
913 | reg = <0x0 0x17020000 0x0 0xd100>, | |
09c9e059 | 914 | <0x0 0X17030000 0x0 0Xc300>, |
3d390425 IS |
915 | <0x0 0X10000000 0x0 0X200>; |
916 | reg-names = "enet_csr", "ring_csr", "ring_cmd"; | |
917 | interrupts = <0x0 0x3c 0x4>; | |
918 | dma-coherent; | |
919 | clocks = <&menetclk 0>; | |
5fb32417 IS |
920 | /* mac address will be overwritten by the bootloader */ |
921 | local-mac-address = [00 00 00 00 00 00]; | |
3d390425 IS |
922 | phy-connection-type = "rgmii"; |
923 | phy-handle = <&menetphy>; | |
924 | mdio { | |
925 | compatible = "apm,xgene-mdio"; | |
926 | #address-cells = <1>; | |
927 | #size-cells = <0>; | |
928 | menetphy: menetphy@3 { | |
929 | compatible = "ethernet-phy-id001c.c915"; | |
930 | reg = <0x3>; | |
931 | }; | |
932 | ||
933 | }; | |
934 | }; | |
ab818739 | 935 | |
4c2e7f09 | 936 | sgenet0: ethernet@1f210000 { |
2a91eb72 | 937 | compatible = "apm,xgene1-sgenet"; |
4c2e7f09 | 938 | status = "disabled"; |
09c9e059 IS |
939 | reg = <0x0 0x1f210000 0x0 0xd100>, |
940 | <0x0 0x1f200000 0x0 0Xc300>, | |
941 | <0x0 0x1B000000 0x0 0X200>; | |
4c2e7f09 | 942 | reg-names = "enet_csr", "ring_csr", "ring_cmd"; |
d3134649 IS |
943 | interrupts = <0x0 0xA0 0x4>, |
944 | <0x0 0xA1 0x4>; | |
4c2e7f09 IS |
945 | dma-coherent; |
946 | clocks = <&sge0clk 0>; | |
947 | local-mac-address = [00 00 00 00 00 00]; | |
948 | phy-connection-type = "sgmii"; | |
949 | }; | |
950 | ||
2d33394e KC |
951 | sgenet1: ethernet@1f210030 { |
952 | compatible = "apm,xgene1-sgenet"; | |
953 | status = "disabled"; | |
954 | reg = <0x0 0x1f210030 0x0 0xd100>, | |
955 | <0x0 0x1f200000 0x0 0Xc300>, | |
956 | <0x0 0x1B000000 0x0 0X8000>; | |
957 | reg-names = "enet_csr", "ring_csr", "ring_cmd"; | |
d3134649 IS |
958 | interrupts = <0x0 0xAC 0x4>, |
959 | <0x0 0xAD 0x4>; | |
2d33394e KC |
960 | port-id = <1>; |
961 | dma-coherent; | |
962 | clocks = <&sge1clk 0>; | |
963 | local-mac-address = [00 00 00 00 00 00]; | |
964 | phy-connection-type = "sgmii"; | |
965 | }; | |
966 | ||
5fb32417 | 967 | xgenet: ethernet@1f610000 { |
2a91eb72 | 968 | compatible = "apm,xgene1-xgenet"; |
5fb32417 IS |
969 | status = "disabled"; |
970 | reg = <0x0 0x1f610000 0x0 0xd100>, | |
09c9e059 | 971 | <0x0 0x1f600000 0x0 0Xc300>, |
5fb32417 IS |
972 | <0x0 0x18000000 0x0 0X200>; |
973 | reg-names = "enet_csr", "ring_csr", "ring_cmd"; | |
d3134649 IS |
974 | interrupts = <0x0 0x60 0x4>, |
975 | <0x0 0x61 0x4>; | |
5fb32417 IS |
976 | dma-coherent; |
977 | clocks = <&xge0clk 0>; | |
978 | /* mac address will be overwritten by the bootloader */ | |
979 | local-mac-address = [00 00 00 00 00 00]; | |
980 | phy-connection-type = "xgmii"; | |
981 | }; | |
982 | ||
e63c7a09 IS |
983 | xgenet1: ethernet@1f620000 { |
984 | compatible = "apm,xgene1-xgenet"; | |
985 | status = "disabled"; | |
986 | reg = <0x0 0x1f620000 0x0 0xd100>, | |
987 | <0x0 0x1f600000 0x0 0Xc300>, | |
988 | <0x0 0x18000000 0x0 0X8000>; | |
989 | reg-names = "enet_csr", "ring_csr", "ring_cmd"; | |
990 | interrupts = <0x0 0x6C 0x4>, | |
991 | <0x0 0x6D 0x4>; | |
992 | port-id = <1>; | |
993 | dma-coherent; | |
994 | clocks = <&xge1clk 0>; | |
995 | /* mac address will be overwritten by the bootloader */ | |
996 | local-mac-address = [00 00 00 00 00 00]; | |
997 | phy-connection-type = "xgmii"; | |
998 | }; | |
999 | ||
ab818739 FK |
1000 | rng: rng@10520000 { |
1001 | compatible = "apm,xgene-rng"; | |
1002 | reg = <0x0 0x10520000 0x0 0x100>; | |
1003 | interrupts = <0x0 0x41 0x4>; | |
1004 | clocks = <&rngpkaclk 0>; | |
1005 | }; | |
74e353e1 RPS |
1006 | |
1007 | dma: dma@1f270000 { | |
1008 | compatible = "apm,xgene-storm-dma"; | |
1009 | device_type = "dma"; | |
1010 | reg = <0x0 0x1f270000 0x0 0x10000>, | |
1011 | <0x0 0x1f200000 0x0 0x10000>, | |
cda8e937 | 1012 | <0x0 0x1b000000 0x0 0x400000>, |
74e353e1 RPS |
1013 | <0x0 0x1054a000 0x0 0x100>; |
1014 | interrupts = <0x0 0x82 0x4>, | |
1015 | <0x0 0xb8 0x4>, | |
1016 | <0x0 0xb9 0x4>, | |
1017 | <0x0 0xba 0x4>, | |
1018 | <0x0 0xbb 0x4>; | |
1019 | dma-coherent; | |
1020 | clocks = <&dmaclk 0>; | |
1021 | }; | |
ee877b53 VK |
1022 | }; |
1023 | }; |