projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| ffae4e01 SK |
1 | /* |
| 2 | * Copyright (C) 2009 ST-Ericsson. | |
| 3 | * | |
| 4 | * U8500 hardware definitions | |
| 5 | * | |
| 6 | * This file is licensed under the terms of the GNU General Public | |
| 7 | * License version 2. This program is licensed "as is" without any | |
| 8 | * warranty of any kind, whether express or implied. | |
| 9 | */ | |
| 10 | #ifndef __MACH_HARDWARE_H | |
| 11 | #define __MACH_HARDWARE_H | |
| 12 | ||
| 13 | /* macros to get at IO space when running virtually | |
| 14 | * We dont map all the peripherals, let ioremap do | |
| 15 | * this for us. We map only very basic peripherals here. | |
| 16 | */ | |
| 17 | #define U8500_IO_VIRTUAL 0xf0000000 | |
| 18 | #define U8500_IO_PHYSICAL 0xa0000000 | |
| 19 | ||
| 20 | /* this macro is used in assembly, so no cast */ | |
| 21 | #define IO_ADDRESS(x) \ | |
| 22 | (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + U8500_IO_VIRTUAL) | |
| 23 | ||
| 24 | /* typesafe io address */ | |
| 25 | #define __io_address(n) __io(IO_ADDRESS(n)) | |
| 94bdc0e2 RV |
26 | /* used by some plat-nomadik code */ |
| 27 | #define io_p2v(n) __io_address(n) | |
| ffae4e01 | 28 | |
| c9c09572 RV |
29 | #include <mach/db8500-regs.h> |
| 30 | #include <mach/db5500-regs.h> | |
| 31 | ||
| 32 | #ifdef CONFIG_UX500_SOC_DB8500 | |
| 33 | #define UX500(periph) U8500_##periph##_BASE | |
| 34 | #elif defined(CONFIG_UX500_SOC_DB5500) | |
| 35 | #define UX500(periph) U5500_##periph##_BASE | |
| 36 | #endif | |
| 37 | ||
| 38 | #define UX500_BACKUPRAM0_BASE UX500(BACKUPRAM0) | |
| 39 | #define UX500_BACKUPRAM1_BASE UX500(BACKUPRAM1) | |
| 40 | #define UX500_B2R2_BASE UX500(B2R2) | |
| 41 | ||
| 42 | #define UX500_CLKRST1_BASE UX500(CLKRST1) | |
| 43 | #define UX500_CLKRST2_BASE UX500(CLKRST2) | |
| 44 | #define UX500_CLKRST3_BASE UX500(CLKRST3) | |
| 45 | #define UX500_CLKRST5_BASE UX500(CLKRST5) | |
| 46 | #define UX500_CLKRST6_BASE UX500(CLKRST6) | |
| 47 | ||
| 48 | #define UX500_DMA_BASE UX500(DMA) | |
| 49 | #define UX500_FSMC_BASE UX500(FSMC) | |
| 50 | ||
| 51 | #define UX500_GIC_CPU_BASE UX500(GIC_CPU) | |
| 52 | #define UX500_GIC_DIST_BASE UX500(GIC_DIST) | |
| 53 | ||
| 54 | #define UX500_I2C1_BASE UX500(I2C1) | |
| 55 | #define UX500_I2C2_BASE UX500(I2C2) | |
| 56 | #define UX500_I2C3_BASE UX500(I2C3) | |
| 57 | ||
| 58 | #define UX500_L2CC_BASE UX500(L2CC) | |
| 59 | #define UX500_MCDE_BASE UX500(MCDE) | |
| 60 | #define UX500_MTU0_BASE UX500(MTU0) | |
| 61 | #define UX500_MTU1_BASE UX500(MTU1) | |
| 62 | #define UX500_PRCMU_BASE UX500(PRCMU) | |
| 63 | ||
| 64 | #define UX500_RNG_BASE UX500(RNG) | |
| 65 | #define UX500_RTC_BASE UX500(RTC) | |
| 66 | ||
| 67 | #define UX500_SCU_BASE UX500(SCU) | |
| 68 | ||
| 69 | #define UX500_SDI0_BASE UX500(SDI0) | |
| 70 | #define UX500_SDI1_BASE UX500(SDI1) | |
| 71 | #define UX500_SDI2_BASE UX500(SDI2) | |
| 72 | #define UX500_SDI3_BASE UX500(SDI3) | |
| 73 | #define UX500_SDI4_BASE UX500(SDI4) | |
| 74 | ||
| 75 | #define UX500_SPI0_BASE UX500(SPI0) | |
| 76 | #define UX500_SPI1_BASE UX500(SPI1) | |
| 77 | #define UX500_SPI2_BASE UX500(SPI2) | |
| 78 | #define UX500_SPI3_BASE UX500(SPI3) | |
| 79 | ||
| 80 | #define UX500_SIA_BASE UX500(SIA) | |
| 81 | #define UX500_SVA_BASE UX500(SVA) | |
| 82 | ||
| 83 | #define UX500_TWD_BASE UX500(TWD) | |
| 84 | ||
| 85 | #define UX500_UART0_BASE UX500(UART0) | |
| 86 | #define UX500_UART1_BASE UX500(UART1) | |
| 87 | #define UX500_UART2_BASE UX500(UART2) | |
| 88 | ||
| 89 | #define UX500_USBOTG_BASE UX500(USBOTG) | |
| 94bdc0e2 | 90 | |
| ffae4e01 SK |
91 | /* ST-Ericsson modified pl022 id */ |
| 92 | #define SSP_PER_ID 0x01080022 | |
| 93 | ||
| 75a36ee0 RV |
94 | #ifndef __ASSEMBLY__ |
| 95 | ||
| 96 | #include <asm/cputype.h> | |
| 97 | ||
| f38406bb RV |
98 | static inline bool cpu_is_u8500(void) |
| 99 | { | |
| 100 | #ifdef CONFIG_UX500_SOC_DB8500 | |
| 101 | return 1; | |
| 102 | #else | |
| 103 | return 0; | |
| 104 | #endif | |
| 105 | } | |
| 106 | ||
| 75a36ee0 RV |
107 | static inline bool cpu_is_u8500ed(void) |
| 108 | { | |
| f38406bb | 109 | return cpu_is_u8500() && (read_cpuid_id() & 15) == 0; |
| 75a36ee0 RV |
110 | } |
| 111 | ||
| 112 | static inline bool cpu_is_u8500v1(void) | |
| 113 | { | |
| f38406bb | 114 | return cpu_is_u8500() && (read_cpuid_id() & 15) == 1; |
| 75a36ee0 RV |
115 | } |
| 116 | ||
| 591d8dd7 RV |
117 | static inline bool cpu_is_u5500(void) |
| 118 | { | |
| 119 | #ifdef CONFIG_UX500_SOC_DB5500 | |
| 120 | return 1; | |
| 121 | #else | |
| 122 | return 0; | |
| 123 | #endif | |
| 124 | } | |
| 125 | ||
| 75a36ee0 RV |
126 | #endif |
| 127 | ||
| ffae4e01 | 128 | #endif /* __MACH_HARDWARE_H */ |