[linux-2.6-block.git] / arch / arm / mach-s3c64xx / gpiolib.c

/* arch/arm/plat-s3c64xx/gpiolib.c
 *
 * Copyright 2008 Openmoko, Inc.
 * Copyright 2008 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *      http://armlinux.simtec.co.uk/
 *
 * S3C64XX - GPIOlib support 
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/irq.h>
#include <linux/io.h>

#include <mach/map.h>
#include <mach/gpio.h>

#include <plat/gpio-core.h>
#include <plat/gpio-cfg.h>
#include <plat/gpio-cfg-helpers.h>
#include <mach/regs-gpio.h>

/* GPIO bank summary:
 *
 * Bank	GPIOs	Style	SlpCon	ExtInt Group
 * A	8	4Bit	Yes	1
 * B	7	4Bit	Yes	1
 * C	8	4Bit	Yes	2
 * D	5	4Bit	Yes	3
 * E	5	4Bit	Yes	None
 * F	16	2Bit	Yes	4 [1]
 * G	7	4Bit	Yes	5
 * H	10	4Bit[2]	Yes	6
 * I	16	2Bit	Yes	None
 * J	12	2Bit	Yes	None
 * K	16	4Bit[2]	No	None
 * L	15	4Bit[2] No	None
 * M	6	4Bit	No	IRQ_EINT
 * N	16	2Bit	No	IRQ_EINT
 * O	16	2Bit	Yes	7
 * P	15	2Bit	Yes	8
 * Q	9	2Bit	Yes	9
 *
 * [1] BANKF pins 14,15 do not form part of the external interrupt sources
 * [2] BANK has two control registers, GPxCON0 and GPxCON1
 */

static struct s3c_gpio_cfg gpio_4bit_cfg_noint = {
	.set_config	= s3c_gpio_setcfg_s3c64xx_4bit,
	.get_config	= s3c_gpio_getcfg_s3c64xx_4bit,
	.set_pull	= s3c_gpio_setpull_updown,
	.get_pull	= s3c_gpio_getpull_updown,
};

static struct s3c_gpio_cfg gpio_4bit_cfg_eint0111 = {
	.cfg_eint	= 7,
	.set_config	= s3c_gpio_setcfg_s3c64xx_4bit,
	.get_config	= s3c_gpio_getcfg_s3c64xx_4bit,
	.set_pull	= s3c_gpio_setpull_updown,
	.get_pull	= s3c_gpio_getpull_updown,
};

static struct s3c_gpio_cfg gpio_4bit_cfg_eint0011 = {
	.cfg_eint	= 3,
	.get_config	= s3c_gpio_getcfg_s3c64xx_4bit,
	.set_config	= s3c_gpio_setcfg_s3c64xx_4bit,
	.set_pull	= s3c_gpio_setpull_updown,
	.get_pull	= s3c_gpio_getpull_updown,
};

int s3c64xx_gpio2int_gpm(struct gpio_chip *chip, unsigned pin)
{
	return pin < 5 ? IRQ_EINT(23) + pin : -ENXIO;
}

static struct s3c_gpio_chip gpio_4bit[] = {
	{
		.base	= S3C64XX_GPA_BASE,
		.config	= &gpio_4bit_cfg_eint0111,
		.chip	= {
			.base	= S3C64XX_GPA(0),
			.ngpio	= S3C64XX_GPIO_A_NR,
			.label	= "GPA",
		},
	}, {
		.base	= S3C64XX_GPB_BASE,
		.config	= &gpio_4bit_cfg_eint0111,
		.chip	= {
			.base	= S3C64XX_GPB(0),
			.ngpio	= S3C64XX_GPIO_B_NR,
			.label	= "GPB",
		},
	}, {
		.base	= S3C64XX_GPC_BASE,
		.config	= &gpio_4bit_cfg_eint0111,
		.chip	= {
			.base	= S3C64XX_GPC(0),
			.ngpio	= S3C64XX_GPIO_C_NR,
			.label	= "GPC",
		},
	}, {
		.base	= S3C64XX_GPD_BASE,
		.config	= &gpio_4bit_cfg_eint0111,
		.chip	= {
			.base	= S3C64XX_GPD(0),
			.ngpio	= S3C64XX_GPIO_D_NR,
			.label	= "GPD",
		},
	}, {
		.base	= S3C64XX_GPE_BASE,
		.config	= &gpio_4bit_cfg_noint,
		.chip	= {
			.base	= S3C64XX_GPE(0),
			.ngpio	= S3C64XX_GPIO_E_NR,
			.label	= "GPE",
		},
	}, {
		.base	= S3C64XX_GPG_BASE,
		.config	= &gpio_4bit_cfg_eint0111,
		.chip	= {
			.base	= S3C64XX_GPG(0),
			.ngpio	= S3C64XX_GPIO_G_NR,
			.label	= "GPG",
		},
	}, {
		.base	= S3C64XX_GPM_BASE,
		.config	= &gpio_4bit_cfg_eint0011,
		.chip	= {
			.base	= S3C64XX_GPM(0),
			.ngpio	= S3C64XX_GPIO_M_NR,
			.label	= "GPM",
			.to_irq = s3c64xx_gpio2int_gpm,
		},
	},
};

int s3c64xx_gpio2int_gpl(struct gpio_chip *chip, unsigned pin)
{
	return pin >= 8 ? IRQ_EINT(16) + pin - 8 : -ENXIO;
}

static struct s3c_gpio_chip gpio_4bit2[] = {
	{
		.base	= S3C64XX_GPH_BASE + 0x4,
		.config	= &gpio_4bit_cfg_eint0111,
		.chip	= {
			.base	= S3C64XX_GPH(0),
			.ngpio	= S3C64XX_GPIO_H_NR,
			.label	= "GPH",
		},
	}, {
		.base	= S3C64XX_GPK_BASE + 0x4,
		.config	= &gpio_4bit_cfg_noint,
		.chip	= {
			.base	= S3C64XX_GPK(0),
			.ngpio	= S3C64XX_GPIO_K_NR,
			.label	= "GPK",
		},
	}, {
		.base	= S3C64XX_GPL_BASE + 0x4,
		.config	= &gpio_4bit_cfg_eint0011,
		.chip	= {
			.base	= S3C64XX_GPL(0),
			.ngpio	= S3C64XX_GPIO_L_NR,
			.label	= "GPL",
			.to_irq = s3c64xx_gpio2int_gpl,
		},
	},
};

static struct s3c_gpio_cfg gpio_2bit_cfg_noint = {
	.set_config	= s3c_gpio_setcfg_s3c24xx,
	.get_config	= s3c_gpio_getcfg_s3c24xx,
	.set_pull	= s3c_gpio_setpull_updown,
	.get_pull	= s3c_gpio_getpull_updown,
};

static struct s3c_gpio_cfg gpio_2bit_cfg_eint10 = {
	.cfg_eint	= 2,
	.set_config	= s3c_gpio_setcfg_s3c24xx,
	.get_config	= s3c_gpio_getcfg_s3c24xx,
	.set_pull	= s3c_gpio_setpull_updown,
	.get_pull	= s3c_gpio_getpull_updown,
};

static struct s3c_gpio_cfg gpio_2bit_cfg_eint11 = {
	.cfg_eint	= 3,
	.set_config	= s3c_gpio_setcfg_s3c24xx,
	.get_config	= s3c_gpio_getcfg_s3c24xx,
	.set_pull	= s3c_gpio_setpull_updown,
	.get_pull	= s3c_gpio_getpull_updown,
};

int s3c64xx_gpio2int_gpn(struct gpio_chip *chip, unsigned pin)
{
	return IRQ_EINT(0) + pin;
}

static struct s3c_gpio_chip gpio_2bit[] = {
	{
		.base	= S3C64XX_GPF_BASE,
		.config	= &gpio_2bit_cfg_eint11,
		.chip	= {
			.base	= S3C64XX_GPF(0),
			.ngpio	= S3C64XX_GPIO_F_NR,
			.label	= "GPF",
		},
	}, {
		.base	= S3C64XX_GPI_BASE,
		.config	= &gpio_2bit_cfg_noint,
		.chip	= {
			.base	= S3C64XX_GPI(0),
			.ngpio	= S3C64XX_GPIO_I_NR,
			.label	= "GPI",
		},
	}, {
		.base	= S3C64XX_GPJ_BASE,
		.config	= &gpio_2bit_cfg_noint,
		.chip	= {
			.base	= S3C64XX_GPJ(0),
			.ngpio	= S3C64XX_GPIO_J_NR,
			.label	= "GPJ",
		},
	}, {
		.base	= S3C64XX_GPN_BASE,
		.config	= &gpio_2bit_cfg_eint10,
		.chip	= {
			.base	= S3C64XX_GPN(0),
			.ngpio	= S3C64XX_GPIO_N_NR,
			.label	= "GPN",
			.to_irq = s3c64xx_gpio2int_gpn,
		},
	}, {
		.base	= S3C64XX_GPO_BASE,
		.config	= &gpio_2bit_cfg_eint11,
		.chip	= {
			.base	= S3C64XX_GPO(0),
			.ngpio	= S3C64XX_GPIO_O_NR,
			.label	= "GPO",
		},
	}, {
		.base	= S3C64XX_GPP_BASE,
		.config	= &gpio_2bit_cfg_eint11,
		.chip	= {
			.base	= S3C64XX_GPP(0),
			.ngpio	= S3C64XX_GPIO_P_NR,
			.label	= "GPP",
		},
	}, {
		.base	= S3C64XX_GPQ_BASE,
		.config	= &gpio_2bit_cfg_eint11,
		.chip	= {
			.base	= S3C64XX_GPQ(0),
			.ngpio	= S3C64XX_GPIO_Q_NR,
			.label	= "GPQ",
		},
	},
};

static __init void s3c64xx_gpiolib_add_2bit(struct s3c_gpio_chip *chip)
{
	chip->pm = __gpio_pm(&s3c_gpio_pm_2bit);
}

static __init void s3c64xx_gpiolib_add(struct s3c_gpio_chip *chips,
				       int nr_chips,
				       void (*fn)(struct s3c_gpio_chip *))
{
	for (; nr_chips > 0; nr_chips--, chips++) {
		if (fn)
			(fn)(chips);
		s3c_gpiolib_add(chips);
	}
}

static __init int s3c64xx_gpiolib_init(void)
{
	s3c64xx_gpiolib_add(gpio_4bit, ARRAY_SIZE(gpio_4bit),
			    samsung_gpiolib_add_4bit);

	s3c64xx_gpiolib_add(gpio_4bit2, ARRAY_SIZE(gpio_4bit2),
			    samsung_gpiolib_add_4bit2);

	s3c64xx_gpiolib_add(gpio_2bit, ARRAY_SIZE(gpio_2bit),
			    s3c64xx_gpiolib_add_2bit);

	return 0;
}

core_initcall(s3c64xx_gpiolib_init);
Commit	Line	Data
89d043c3 BD	1	/* arch/arm/plat-s3c64xx/gpiolib.c
	2	*
	3	* Copyright 2008 Openmoko, Inc.
	4	* Copyright 2008 Simtec Electronics
	5	* Ben Dooks <ben@simtec.co.uk>
	6	* http://armlinux.simtec.co.uk/
	7	*
	8	* S3C64XX - GPIOlib support
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*/
	14
	15	#include <linux/kernel.h>
	16	#include <linux/irq.h>
	17	#include <linux/io.h>
	18
	19	#include <mach/map.h>
	20	#include <mach/gpio.h>
	21
e856bb1f	22	#include <plat/gpio-core.h>
21b23664 BD	23	#include <plat/gpio-cfg.h>
21b23664 BD	24	#include <plat/gpio-cfg-helpers.h>
3501c9ae	25	#include <mach/regs-gpio.h>
89d043c3 BD	26
	27	/* GPIO bank summary:
	28	*
	29	* Bank GPIOs Style SlpCon ExtInt Group
	30	* A 8 4Bit Yes 1
	31	* B 7 4Bit Yes 1
	32	* C 8 4Bit Yes 2
	33	* D 5 4Bit Yes 3
	34	* E 5 4Bit Yes None
	35	* F 16 2Bit Yes 4 [1]
	36	* G 7 4Bit Yes 5
	37	* H 10 4Bit[2] Yes 6
	38	* I 16 2Bit Yes None
	39	* J 12 2Bit Yes None
	40	* K 16 4Bit[2] No None
	41	* L 15 4Bit[2] No None
	42	* M 6 4Bit No IRQ_EINT
	43	* N 16 2Bit No IRQ_EINT
	44	* O 16 2Bit Yes 7
	45	* P 15 2Bit Yes 8
	46	* Q 9 2Bit Yes 9
	47	*
	48	* [1] BANKF pins 14,15 do not form part of the external interrupt sources
	49	* [2] BANK has two control registers, GPxCON0 and GPxCON1
	50	*/
	51
21b23664 BD	52	static struct s3c_gpio_cfg gpio_4bit_cfg_noint = {
21b23664 BD	53	.set_config = s3c_gpio_setcfg_s3c64xx_4bit,
97a33999	54	.get_config = s3c_gpio_getcfg_s3c64xx_4bit,
21b23664 BD	55	.set_pull = s3c_gpio_setpull_updown,
	56	.get_pull = s3c_gpio_getpull_updown,
	57	};
	58
	59	static struct s3c_gpio_cfg gpio_4bit_cfg_eint0111 = {
	60	.cfg_eint = 7,
	61	.set_config = s3c_gpio_setcfg_s3c64xx_4bit,
97a33999	62	.get_config = s3c_gpio_getcfg_s3c64xx_4bit,
21b23664 BD	63	.set_pull = s3c_gpio_setpull_updown,
	64	.get_pull = s3c_gpio_getpull_updown,
	65	};
	66
	67	static struct s3c_gpio_cfg gpio_4bit_cfg_eint0011 = {
	68	.cfg_eint = 3,
97a33999	69	.get_config = s3c_gpio_getcfg_s3c64xx_4bit,
21b23664 BD	70	.set_config = s3c_gpio_setcfg_s3c64xx_4bit,
	71	.set_pull = s3c_gpio_setpull_updown,
	72	.get_pull = s3c_gpio_getpull_updown,
	73	};
	74
6a88e983 MC	75	int s3c64xx_gpio2int_gpm(struct gpio_chip *chip, unsigned pin)
	76	{
	77	return pin < 5 ? IRQ_EINT(23) + pin : -ENXIO;
	78	}
	79
89d043c3 BD	80	static struct s3c_gpio_chip gpio_4bit[] = {
	81	{
	82	.base = S3C64XX_GPA_BASE,
21b23664	83	.config = &gpio_4bit_cfg_eint0111,
89d043c3 BD	84	.chip = {
	85	.base = S3C64XX_GPA(0),
	86	.ngpio = S3C64XX_GPIO_A_NR,
	87	.label = "GPA",
	88	},
	89	}, {
	90	.base = S3C64XX_GPB_BASE,
21b23664	91	.config = &gpio_4bit_cfg_eint0111,
89d043c3 BD	92	.chip = {
	93	.base = S3C64XX_GPB(0),
	94	.ngpio = S3C64XX_GPIO_B_NR,
	95	.label = "GPB",
	96	},
	97	}, {
	98	.base = S3C64XX_GPC_BASE,
21b23664	99	.config = &gpio_4bit_cfg_eint0111,
89d043c3 BD	100	.chip = {
	101	.base = S3C64XX_GPC(0),
	102	.ngpio = S3C64XX_GPIO_C_NR,
	103	.label = "GPC",
	104	},
	105	}, {
	106	.base = S3C64XX_GPD_BASE,
21b23664	107	.config = &gpio_4bit_cfg_eint0111,
89d043c3 BD	108	.chip = {
	109	.base = S3C64XX_GPD(0),
	110	.ngpio = S3C64XX_GPIO_D_NR,
	111	.label = "GPD",
	112	},
	113	}, {
	114	.base = S3C64XX_GPE_BASE,
21b23664	115	.config = &gpio_4bit_cfg_noint,
89d043c3 BD	116	.chip = {
	117	.base = S3C64XX_GPE(0),
	118	.ngpio = S3C64XX_GPIO_E_NR,
	119	.label = "GPE",
	120	},
	121	}, {
	122	.base = S3C64XX_GPG_BASE,
21b23664	123	.config = &gpio_4bit_cfg_eint0111,
89d043c3 BD	124	.chip = {
	125	.base = S3C64XX_GPG(0),
	126	.ngpio = S3C64XX_GPIO_G_NR,
	127	.label = "GPG",
	128	},
	129	}, {
	130	.base = S3C64XX_GPM_BASE,
21b23664	131	.config = &gpio_4bit_cfg_eint0011,
89d043c3 BD	132	.chip = {
	133	.base = S3C64XX_GPM(0),
	134	.ngpio = S3C64XX_GPIO_M_NR,
	135	.label = "GPM",
6a88e983	136	.to_irq = s3c64xx_gpio2int_gpm,
89d043c3 BD	137	},
	138	},
	139	};
	140
6a88e983 MC	141	int s3c64xx_gpio2int_gpl(struct gpio_chip *chip, unsigned pin)
	142	{
	143	return pin >= 8 ? IRQ_EINT(16) + pin - 8 : -ENXIO;
	144	}
	145
89d043c3 BD	146	static struct s3c_gpio_chip gpio_4bit2[] = {
	147	{
	148	.base = S3C64XX_GPH_BASE + 0x4,
21b23664	149	.config = &gpio_4bit_cfg_eint0111,
89d043c3 BD	150	.chip = {
	151	.base = S3C64XX_GPH(0),
	152	.ngpio = S3C64XX_GPIO_H_NR,
	153	.label = "GPH",
	154	},
	155	}, {
	156	.base = S3C64XX_GPK_BASE + 0x4,
21b23664	157	.config = &gpio_4bit_cfg_noint,
89d043c3 BD	158	.chip = {
	159	.base = S3C64XX_GPK(0),
	160	.ngpio = S3C64XX_GPIO_K_NR,
	161	.label = "GPK",
	162	},
	163	}, {
	164	.base = S3C64XX_GPL_BASE + 0x4,
21b23664	165	.config = &gpio_4bit_cfg_eint0011,
89d043c3 BD	166	.chip = {
	167	.base = S3C64XX_GPL(0),
	168	.ngpio = S3C64XX_GPIO_L_NR,
	169	.label = "GPL",
6a88e983	170	.to_irq = s3c64xx_gpio2int_gpl,
89d043c3 BD	171	},
	172	},
	173	};
	174
21b23664 BD	175	static struct s3c_gpio_cfg gpio_2bit_cfg_noint = {
21b23664 BD	176	.set_config = s3c_gpio_setcfg_s3c24xx,
97a33999	177	.get_config = s3c_gpio_getcfg_s3c24xx,
21b23664 BD	178	.set_pull = s3c_gpio_setpull_updown,
	179	.get_pull = s3c_gpio_getpull_updown,
	180	};
	181
	182	static struct s3c_gpio_cfg gpio_2bit_cfg_eint10 = {
	183	.cfg_eint = 2,
	184	.set_config = s3c_gpio_setcfg_s3c24xx,
97a33999	185	.get_config = s3c_gpio_getcfg_s3c24xx,
21b23664 BD	186	.set_pull = s3c_gpio_setpull_updown,
	187	.get_pull = s3c_gpio_getpull_updown,
	188	};
	189
	190	static struct s3c_gpio_cfg gpio_2bit_cfg_eint11 = {
	191	.cfg_eint = 3,
	192	.set_config = s3c_gpio_setcfg_s3c24xx,
97a33999	193	.get_config = s3c_gpio_getcfg_s3c24xx,
21b23664 BD	194	.set_pull = s3c_gpio_setpull_updown,
	195	.get_pull = s3c_gpio_getpull_updown,
	196	};
	197
0b495737 MS	198	int s3c64xx_gpio2int_gpn(struct gpio_chip *chip, unsigned pin)
	199	{
	200	return IRQ_EINT(0) + pin;
	201	}
	202
89d043c3 BD	203	static struct s3c_gpio_chip gpio_2bit[] = {
	204	{
	205	.base = S3C64XX_GPF_BASE,
21b23664	206	.config = &gpio_2bit_cfg_eint11,
89d043c3 BD	207	.chip = {
	208	.base = S3C64XX_GPF(0),
	209	.ngpio = S3C64XX_GPIO_F_NR,
	210	.label = "GPF",
	211	},
	212	}, {
	213	.base = S3C64XX_GPI_BASE,
21b23664	214	.config = &gpio_2bit_cfg_noint,
89d043c3 BD	215	.chip = {
	216	.base = S3C64XX_GPI(0),
	217	.ngpio = S3C64XX_GPIO_I_NR,
	218	.label = "GPI",
	219	},
	220	}, {
	221	.base = S3C64XX_GPJ_BASE,
21b23664	222	.config = &gpio_2bit_cfg_noint,
89d043c3 BD	223	.chip = {
	224	.base = S3C64XX_GPJ(0),
	225	.ngpio = S3C64XX_GPIO_J_NR,
	226	.label = "GPJ",
	227	},
	228	}, {
	229	.base = S3C64XX_GPN_BASE,
21b23664	230	.config = &gpio_2bit_cfg_eint10,
89d043c3 BD	231	.chip = {
	232	.base = S3C64XX_GPN(0),
	233	.ngpio = S3C64XX_GPIO_N_NR,
	234	.label = "GPN",
0b495737	235	.to_irq = s3c64xx_gpio2int_gpn,
89d043c3 BD	236	},
	237	}, {
	238	.base = S3C64XX_GPO_BASE,
21b23664	239	.config = &gpio_2bit_cfg_eint11,
89d043c3 BD	240	.chip = {
	241	.base = S3C64XX_GPO(0),
	242	.ngpio = S3C64XX_GPIO_O_NR,
	243	.label = "GPO",
	244	},
	245	}, {
	246	.base = S3C64XX_GPP_BASE,
21b23664	247	.config = &gpio_2bit_cfg_eint11,
89d043c3 BD	248	.chip = {
	249	.base = S3C64XX_GPP(0),
	250	.ngpio = S3C64XX_GPIO_P_NR,
	251	.label = "GPP",
	252	},
	253	}, {
	254	.base = S3C64XX_GPQ_BASE,
21b23664	255	.config = &gpio_2bit_cfg_eint11,
89d043c3 BD	256	.chip = {
	257	.base = S3C64XX_GPQ(0),
	258	.ngpio = S3C64XX_GPIO_Q_NR,
	259	.label = "GPQ",
	260	},
	261	},
	262	};
	263
d87964c4 BD	264	static __init void s3c64xx_gpiolib_add_2bit(struct s3c_gpio_chip *chip)
	265	{
	266	chip->pm = __gpio_pm(&s3c_gpio_pm_2bit);
89d043c3 BD	267	}
	268
	269	static __init void s3c64xx_gpiolib_add(struct s3c_gpio_chip *chips,
	270	int nr_chips,
	271	void (fn)(struct s3c_gpio_chip ))
	272	{
	273	for (; nr_chips > 0; nr_chips--, chips++) {
	274	if (fn)
	275	(fn)(chips);
	276	s3c_gpiolib_add(chips);
	277	}
	278	}
	279
	280	static __init int s3c64xx_gpiolib_init(void)
	281	{
	282	s3c64xx_gpiolib_add(gpio_4bit, ARRAY_SIZE(gpio_4bit),
1f323cfd	283	samsung_gpiolib_add_4bit);
89d043c3 BD	284
89d043c3 BD	285	s3c64xx_gpiolib_add(gpio_4bit2, ARRAY_SIZE(gpio_4bit2),
1f323cfd	286	samsung_gpiolib_add_4bit2);
89d043c3	287
d87964c4 BD	288	s3c64xx_gpiolib_add(gpio_2bit, ARRAY_SIZE(gpio_2bit),
d87964c4 BD	289	s3c64xx_gpiolib_add_2bit);
89d043c3 BD	290
	291	return 0;
	292	}
	293
24d40767	294	core_initcall(s3c64xx_gpiolib_init);