[linux-2.6-block.git] / arch / arm / mach-s3c2440 / mach-anubis.c

/* linux/arch/arm/mach-s3c2440/mach-anubis.c
 *
 * Copyright (c) 2003-2005,2008 Simtec Electronics
 *	http://armlinux.simtec.co.uk/
 *	Ben Dooks <ben@simtec.co.uk>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/gpio.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <linux/ata_platform.h>
#include <linux/i2c.h>
#include <linux/io.h>
#include <linux/sm501.h>
#include <linux/sm501-regs.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>

#include <mach/anubis-map.h>
#include <mach/anubis-irq.h>
#include <mach/anubis-cpld.h>

#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach-types.h>

#include <plat/regs-serial.h>
#include <mach/regs-gpio.h>
#include <mach/regs-mem.h>
#include <mach/regs-lcd.h>
#include <plat/nand.h>
#include <plat/iic.h>

#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/partitions.h>

#include <net/ax88796.h>

#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#include <plat/audio-simtec.h>

#define COPYRIGHT ", (c) 2005-2009 Simtec Electronics"

static struct map_desc anubis_iodesc[] __initdata = {
  /* ISA IO areas */

  {
	.virtual	= (u32)S3C24XX_VA_ISA_BYTE,
	.pfn		= __phys_to_pfn(0x0),
	.length		= SZ_4M,
	.type		= MT_DEVICE,
  }, {
	.virtual	= (u32)S3C24XX_VA_ISA_WORD,
	.pfn		= __phys_to_pfn(0x0),
	.length 	= SZ_4M,
	.type		= MT_DEVICE,
  },

  /* we could possibly compress the next set down into a set of smaller tables
   * pagetables, but that would mean using an L2 section, and it still means
   * we cannot actually feed the same register to an LDR due to 16K spacing
   */

  /* CPLD control registers */

  {
	.virtual	= (u32)ANUBIS_VA_CTRL1,
	.pfn		= __phys_to_pfn(ANUBIS_PA_CTRL1),
	.length		= SZ_4K,
	.type		= MT_DEVICE,
  }, {
	.virtual	= (u32)ANUBIS_VA_IDREG,
	.pfn		= __phys_to_pfn(ANUBIS_PA_IDREG),
	.length		= SZ_4K,
	.type		= MT_DEVICE,
  },
};

#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE

static struct s3c24xx_uart_clksrc anubis_serial_clocks[] = {
	[0] = {
		.name		= "uclk",
		.divisor	= 1,
		.min_baud	= 0,
		.max_baud	= 0,
	},
	[1] = {
		.name		= "pclk",
		.divisor	= 1,
		.min_baud	= 0,
		.max_baud	= 0,
	}
};


static struct s3c2410_uartcfg anubis_uartcfgs[] __initdata = {
	[0] = {
		.hwport	     = 0,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
		.clocks	     = anubis_serial_clocks,
		.clocks_size = ARRAY_SIZE(anubis_serial_clocks),
	},
	[1] = {
		.hwport	     = 2,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
		.clocks	     = anubis_serial_clocks,
		.clocks_size = ARRAY_SIZE(anubis_serial_clocks),
	},
};

/* NAND Flash on Anubis board */

static int external_map[]   = { 2 };
static int chip0_map[]      = { 0 };
static int chip1_map[]      = { 1 };

static struct mtd_partition anubis_default_nand_part[] = {
	[0] = {
		.name	= "Boot Agent",
		.size	= SZ_16K,
		.offset	= 0,
	},
	[1] = {
		.name	= "/boot",
		.size	= SZ_4M - SZ_16K,
		.offset	= SZ_16K,
	},
	[2] = {
		.name	= "user1",
		.offset	= SZ_4M,
		.size	= SZ_32M - SZ_4M,
	},
	[3] = {
		.name	= "user2",
		.offset	= SZ_32M,
		.size	= MTDPART_SIZ_FULL,
	}
};

static struct mtd_partition anubis_default_nand_part_large[] = {
	[0] = {
		.name	= "Boot Agent",
		.size	= SZ_128K,
		.offset	= 0,
	},
	[1] = {
		.name	= "/boot",
		.size	= SZ_4M - SZ_128K,
		.offset	= SZ_128K,
	},
	[2] = {
		.name	= "user1",
		.offset	= SZ_4M,
		.size	= SZ_32M - SZ_4M,
	},
	[3] = {
		.name	= "user2",
		.offset	= SZ_32M,
		.size	= MTDPART_SIZ_FULL,
	}
};

/* the Anubis has 3 selectable slots for nand-flash, the two
 * on-board chip areas, as well as the external slot.
 *
 * Note, there is no current hot-plug support for the External
 * socket.
*/

static struct s3c2410_nand_set anubis_nand_sets[] = {
	[1] = {
		.name		= "External",
		.nr_chips	= 1,
		.nr_map		= external_map,
		.nr_partitions	= ARRAY_SIZE(anubis_default_nand_part),
		.partitions	= anubis_default_nand_part,
	},
	[0] = {
		.name		= "chip0",
		.nr_chips	= 1,
		.nr_map		= chip0_map,
		.nr_partitions	= ARRAY_SIZE(anubis_default_nand_part),
		.partitions	= anubis_default_nand_part,
	},
	[2] = {
		.name		= "chip1",
		.nr_chips	= 1,
		.nr_map		= chip1_map,
		.nr_partitions	= ARRAY_SIZE(anubis_default_nand_part),
		.partitions	= anubis_default_nand_part,
	},
};

static void anubis_nand_select(struct s3c2410_nand_set *set, int slot)
{
	unsigned int tmp;

	slot = set->nr_map[slot] & 3;

	pr_debug("anubis_nand: selecting slot %d (set %p,%p)\n",
		 slot, set, set->nr_map);

	tmp = __raw_readb(ANUBIS_VA_CTRL1);
	tmp &= ~ANUBIS_CTRL1_NANDSEL;
	tmp |= slot;

	pr_debug("anubis_nand: ctrl1 now %02x\n", tmp);

	__raw_writeb(tmp, ANUBIS_VA_CTRL1);
}

static struct s3c2410_platform_nand anubis_nand_info = {
	.tacls		= 25,
	.twrph0		= 55,
	.twrph1		= 40,
	.nr_sets	= ARRAY_SIZE(anubis_nand_sets),
	.sets		= anubis_nand_sets,
	.select_chip	= anubis_nand_select,
};

/* IDE channels */

static struct pata_platform_info anubis_ide_platdata = {
	.ioport_shift	= 5,
};

static struct resource anubis_ide0_resource[] = {
	{
		.start	= S3C2410_CS3,
		.end	= S3C2410_CS3 + (8*32) - 1,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= S3C2410_CS3 + (1<<26) + (6*32),
		.end	= S3C2410_CS3 + (1<<26) + (7*32) - 1,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_IDE0,
		.end	= IRQ_IDE0,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device anubis_device_ide0 = {
	.name		= "pata_platform",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(anubis_ide0_resource),
	.resource	= anubis_ide0_resource,
	.dev	= {
		.platform_data = &anubis_ide_platdata,
		.coherent_dma_mask = ~0,
	},
};

static struct resource anubis_ide1_resource[] = {
	{
		.start	= S3C2410_CS4,
		.end	= S3C2410_CS4 + (8*32) - 1,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= S3C2410_CS4 + (1<<26) + (6*32),
		.end	= S3C2410_CS4 + (1<<26) + (7*32) - 1,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_IDE0,
		.end	= IRQ_IDE0,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device anubis_device_ide1 = {
	.name		= "pata_platform",
	.id		= 1,
	.num_resources	= ARRAY_SIZE(anubis_ide1_resource),
	.resource	= anubis_ide1_resource,
	.dev	= {
		.platform_data = &anubis_ide_platdata,
		.coherent_dma_mask = ~0,
	},
};

/* Asix AX88796 10/100 ethernet controller */

static struct ax_plat_data anubis_asix_platdata = {
	.flags		= AXFLG_MAC_FROMDEV,
	.wordlength	= 2,
	.dcr_val	= 0x48,
	.rcr_val	= 0x40,
};

static struct resource anubis_asix_resource[] = {
	[0] = {
		.start = S3C2410_CS5,
		.end   = S3C2410_CS5 + (0x20 * 0x20) -1,
		.flags = IORESOURCE_MEM
	},
	[1] = {
		.start = IRQ_ASIX,
		.end   = IRQ_ASIX,
		.flags = IORESOURCE_IRQ
	}
};

static struct platform_device anubis_device_asix = {
	.name		= "ax88796",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(anubis_asix_resource),
	.resource	= anubis_asix_resource,
	.dev		= {
		.platform_data = &anubis_asix_platdata,
	}
};

/* SM501 */

static struct resource anubis_sm501_resource[] = {
	[0] = {
		.start	= S3C2410_CS2,
		.end	= S3C2410_CS2 + SZ_8M,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= S3C2410_CS2 + SZ_64M - SZ_2M,
		.end	= S3C2410_CS2 + SZ_64M - 1,
		.flags	= IORESOURCE_MEM,
	},
	[2] = {
		.start	= IRQ_EINT0,
		.end	= IRQ_EINT0,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct sm501_initdata anubis_sm501_initdata = {
	.gpio_high	= {
		.set	= 0x3F000000,		/* 24bit panel */
		.mask	= 0x0,
	},
	.misc_timing	= {
		.set	= 0x010100,		/* SDRAM timing */
		.mask	= 0x1F1F00,
	},
	.misc_control	= {
		.set	= SM501_MISC_PNL_24BIT,
		.mask	= 0,
	},

	.devices	= SM501_USE_GPIO,

	/* set the SDRAM and bus clocks */
	.mclk		= 72 * MHZ,
	.m1xclk		= 144 * MHZ,
};

static struct sm501_platdata_gpio_i2c anubis_sm501_gpio_i2c[] = {
	[0] = {
		.bus_num	= 1,
		.pin_scl	= 44,
		.pin_sda	= 45,
	},
	[1] = {
		.bus_num	= 2,
		.pin_scl	= 40,
		.pin_sda	= 41,
	},
};

static struct sm501_platdata anubis_sm501_platdata = {
	.init		= &anubis_sm501_initdata,
	.gpio_base	= -1,
	.gpio_i2c	= anubis_sm501_gpio_i2c,
	.gpio_i2c_nr	= ARRAY_SIZE(anubis_sm501_gpio_i2c),
};

static struct platform_device anubis_device_sm501 = {
	.name		= "sm501",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(anubis_sm501_resource),
	.resource	= anubis_sm501_resource,
	.dev		= {
		.platform_data = &anubis_sm501_platdata,
	},
};

/* Standard Anubis devices */

static struct platform_device *anubis_devices[] __initdata = {
	&s3c_device_usb,
	&s3c_device_wdt,
	&s3c_device_adc,
	&s3c_device_i2c0,
 	&s3c_device_rtc,
	&s3c_device_nand,
	&anubis_device_ide0,
	&anubis_device_ide1,
	&anubis_device_asix,
	&anubis_device_sm501,
};

static struct clk *anubis_clocks[] __initdata = {
	&s3c24xx_dclk0,
	&s3c24xx_dclk1,
	&s3c24xx_clkout0,
	&s3c24xx_clkout1,
	&s3c24xx_uclk,
};

/* I2C devices. */

static struct i2c_board_info anubis_i2c_devs[] __initdata = {
	{
		I2C_BOARD_INFO("tps65011", 0x48),
		.irq	= IRQ_EINT20,
	}
};

/* Audio setup */
static struct s3c24xx_audio_simtec_pdata __initdata anubis_audio = {
	.have_mic	= 1,
	.have_lout	= 1,
	.output_cdclk	= 1,
	.use_mpllin	= 1,
	.amp_gpio	= S3C2410_GPB(2),
	.amp_gain[0]	= S3C2410_GPD(10),
	.amp_gain[1]	= S3C2410_GPD(11),
};

static void __init anubis_map_io(void)
{
	/* initialise the clocks */

	s3c24xx_dclk0.parent = &clk_upll;
	s3c24xx_dclk0.rate   = 12*1000*1000;

	s3c24xx_dclk1.parent = &clk_upll;
	s3c24xx_dclk1.rate   = 24*1000*1000;

	s3c24xx_clkout0.parent  = &s3c24xx_dclk0;
	s3c24xx_clkout1.parent  = &s3c24xx_dclk1;

	s3c24xx_uclk.parent  = &s3c24xx_clkout1;

	s3c24xx_register_clocks(anubis_clocks, ARRAY_SIZE(anubis_clocks));

	s3c_device_nand.dev.platform_data = &anubis_nand_info;

	s3c24xx_init_io(anubis_iodesc, ARRAY_SIZE(anubis_iodesc));
	s3c24xx_init_clocks(0);
	s3c24xx_init_uarts(anubis_uartcfgs, ARRAY_SIZE(anubis_uartcfgs));

	/* check for the newer revision boards with large page nand */

	if ((__raw_readb(ANUBIS_VA_IDREG) & ANUBIS_IDREG_REVMASK) >= 4) {
		printk(KERN_INFO "ANUBIS-B detected (revision %d)\n",
		       __raw_readb(ANUBIS_VA_IDREG) & ANUBIS_IDREG_REVMASK);
		anubis_nand_sets[0].partitions = anubis_default_nand_part_large;
		anubis_nand_sets[0].nr_partitions = ARRAY_SIZE(anubis_default_nand_part_large);
	} else {
		/* ensure that the GPIO is setup */
		s3c2410_gpio_setpin(S3C2410_GPA(0), 1);
	}
}

static void __init anubis_init(void)
{
	s3c_i2c0_set_platdata(NULL);
	simtec_audio_add(NULL, false, &anubis_audio);
	platform_add_devices(anubis_devices, ARRAY_SIZE(anubis_devices));

	i2c_register_board_info(0, anubis_i2c_devs,
				ARRAY_SIZE(anubis_i2c_devs));
}


MACHINE_START(ANUBIS, "Simtec-Anubis")
	/* Maintainer: Ben Dooks <ben@simtec.co.uk> */
	.phys_io	= S3C2410_PA_UART,
	.io_pg_offst	= (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
	.boot_params	= S3C2410_SDRAM_PA + 0x100,
	.map_io		= anubis_map_io,
	.init_machine	= anubis_init,
	.init_irq	= s3c24xx_init_irq,
	.timer		= &s3c24xx_timer,
MACHINE_END
Commit	Line	Data
a21765a7	1	/* linux/arch/arm/mach-s3c2440/mach-anubis.c
7efb833d	2	*
7a28db61	3	* Copyright (c) 2003-2005,2008 Simtec Electronics
7efb833d BD	4	* http://armlinux.simtec.co.uk/
	5	* Ben Dooks <ben@simtec.co.uk>
	6	*
7efb833d BD	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
7efb833d BD	10	*/
	11
	12	#include <linux/kernel.h>
	13	#include <linux/types.h>
	14	#include <linux/interrupt.h>
	15	#include <linux/list.h>
	16	#include <linux/timer.h>
	17	#include <linux/init.h>
ec976d6e	18	#include <linux/gpio.h>
b6d1f542	19	#include <linux/serial_core.h>
d052d1be	20	#include <linux/platform_device.h>
b9db83af	21	#include <linux/ata_platform.h>
7a28db61	22	#include <linux/i2c.h>
fced80c7	23	#include <linux/io.h>
8a9ccb7f BD	24	#include <linux/sm501.h>
	25	#include <linux/sm501-regs.h>
	26
7efb833d BD	27	#include <asm/mach/arch.h>
	28	#include <asm/mach/map.h>
	29	#include <asm/mach/irq.h>
	30
a09e64fb RK	31	#include <mach/anubis-map.h>
	32	#include <mach/anubis-irq.h>
	33	#include <mach/anubis-cpld.h>
7efb833d	34
a09e64fb	35	#include <mach/hardware.h>
7efb833d BD	36	#include <asm/irq.h>
	37	#include <asm/mach-types.h>
	38
a2b7ba9c	39	#include <plat/regs-serial.h>
a09e64fb RK	40	#include <mach/regs-gpio.h>
	41	#include <mach/regs-mem.h>
	42	#include <mach/regs-lcd.h>
7926b5a3	43	#include <plat/nand.h>
3e1b776c	44	#include <plat/iic.h>
7efb833d BD	45
	46	#include <linux/mtd/mtd.h>
	47	#include <linux/mtd/nand.h>
	48	#include <linux/mtd/nand_ecc.h>
	49	#include <linux/mtd/partitions.h>
	50
eac1d8da BD	51	#include <net/ax88796.h>
eac1d8da BD	52
d5120ae7	53	#include <plat/clock.h>
a2b7ba9c BD	54	#include <plat/devs.h>
a2b7ba9c BD	55	#include <plat/cpu.h>
4d3a3469	56	#include <plat/audio-simtec.h>
7efb833d	57
4d3a3469	58	#define COPYRIGHT ", (c) 2005-2009 Simtec Electronics"
7efb833d BD	59
	60	static struct map_desc anubis_iodesc[] __initdata = {
	61	/* ISA IO areas */
	62
8dd52311 BD	63	{
	64	.virtual = (u32)S3C24XX_VA_ISA_BYTE,
	65	.pfn = __phys_to_pfn(0x0),
	66	.length = SZ_4M,
705630db	67	.type = MT_DEVICE,
8dd52311 BD	68	}, {
	69	.virtual = (u32)S3C24XX_VA_ISA_WORD,
	70	.pfn = __phys_to_pfn(0x0),
705630db BD	71	.length = SZ_4M,
705630db BD	72	.type = MT_DEVICE,
8dd52311	73	},
7efb833d BD	74
	75	/* we could possibly compress the next set down into a set of smaller tables
	76	* pagetables, but that would mean using an L2 section, and it still means
	77	* we cannot actually feed the same register to an LDR due to 16K spacing
	78	*/
	79
	80	/* CPLD control registers */
	81
8dd52311 BD	82	{
	83	.virtual = (u32)ANUBIS_VA_CTRL1,
	84	.pfn = __phys_to_pfn(ANUBIS_PA_CTRL1),
	85	.length = SZ_4K,
705630db	86	.type = MT_DEVICE,
8dd52311	87	}, {
6c1640d5 BD	88	.virtual = (u32)ANUBIS_VA_IDREG,
6c1640d5 BD	89	.pfn = __phys_to_pfn(ANUBIS_PA_IDREG),
8dd52311	90	.length = SZ_4K,
705630db	91	.type = MT_DEVICE,
8dd52311	92	},
7efb833d BD	93	};
	94
	95	#define UCON S3C2410_UCON_DEFAULT \| S3C2410_UCON_UCLK
	96	#define ULCON S3C2410_LCON_CS8 \| S3C2410_LCON_PNONE \| S3C2410_LCON_STOPB
	97	#define UFCON S3C2410_UFCON_RXTRIG8 \| S3C2410_UFCON_FIFOMODE
	98
	99	static struct s3c24xx_uart_clksrc anubis_serial_clocks[] = {
	100	[0] = {
	101	.name = "uclk",
	102	.divisor = 1,
	103	.min_baud = 0,
	104	.max_baud = 0,
	105	},
	106	[1] = {
	107	.name = "pclk",
	108	.divisor = 1,
	109	.min_baud = 0,
705630db	110	.max_baud = 0,
7efb833d BD	111	}
	112	};
	113
	114
66a9b49a	115	static struct s3c2410_uartcfg anubis_uartcfgs[] __initdata = {
7efb833d BD	116	[0] = {
	117	.hwport = 0,
	118	.flags = 0,
	119	.ucon = UCON,
	120	.ulcon = ULCON,
	121	.ufcon = UFCON,
	122	.clocks = anubis_serial_clocks,
705630db	123	.clocks_size = ARRAY_SIZE(anubis_serial_clocks),
7efb833d BD	124	},
	125	[1] = {
	126	.hwport = 2,
	127	.flags = 0,
	128	.ucon = UCON,
	129	.ulcon = ULCON,
	130	.ufcon = UFCON,
	131	.clocks = anubis_serial_clocks,
705630db	132	.clocks_size = ARRAY_SIZE(anubis_serial_clocks),
7efb833d BD	133	},
	134	};
	135
	136	/* NAND Flash on Anubis board */
	137
	138	static int external_map[] = { 2 };
	139	static int chip0_map[] = { 0 };
	140	static int chip1_map[] = { 1 };
	141
9f693d7b	142	static struct mtd_partition anubis_default_nand_part[] = {
7efb833d BD	143	[0] = {
	144	.name = "Boot Agent",
	145	.size = SZ_16K,
705630db	146	.offset = 0,
7efb833d BD	147	},
	148	[1] = {
	149	.name = "/boot",
	150	.size = SZ_4M - SZ_16K,
	151	.offset = SZ_16K,
	152	},
	153	[2] = {
	154	.name = "user1",
	155	.offset = SZ_4M,
	156	.size = SZ_32M - SZ_4M,
	157	},
	158	[3] = {
	159	.name = "user2",
	160	.offset = SZ_32M,
	161	.size = MTDPART_SIZ_FULL,
	162	}
	163	};
	164
ad3613f4 BD	165	static struct mtd_partition anubis_default_nand_part_large[] = {
	166	[0] = {
	167	.name = "Boot Agent",
	168	.size = SZ_128K,
	169	.offset = 0,
	170	},
	171	[1] = {
	172	.name = "/boot",
	173	.size = SZ_4M - SZ_128K,
	174	.offset = SZ_128K,
	175	},
	176	[2] = {
	177	.name = "user1",
	178	.offset = SZ_4M,
	179	.size = SZ_32M - SZ_4M,
	180	},
	181	[3] = {
	182	.name = "user2",
	183	.offset = SZ_32M,
	184	.size = MTDPART_SIZ_FULL,
	185	}
	186	};
	187
7efb833d BD	188	/* the Anubis has 3 selectable slots for nand-flash, the two
	189	* on-board chip areas, as well as the external slot.
	190	*
	191	* Note, there is no current hot-plug support for the External
	192	* socket.
	193	*/
	194
	195	static struct s3c2410_nand_set anubis_nand_sets[] = {
	196	[1] = {
	197	.name = "External",
	198	.nr_chips = 1,
	199	.nr_map = external_map,
	200	.nr_partitions = ARRAY_SIZE(anubis_default_nand_part),
705630db	201	.partitions = anubis_default_nand_part,
7efb833d BD	202	},
	203	[0] = {
	204	.name = "chip0",
	205	.nr_chips = 1,
	206	.nr_map = chip0_map,
	207	.nr_partitions = ARRAY_SIZE(anubis_default_nand_part),
705630db	208	.partitions = anubis_default_nand_part,
7efb833d BD	209	},
	210	[2] = {
	211	.name = "chip1",
	212	.nr_chips = 1,
	213	.nr_map = chip1_map,
	214	.nr_partitions = ARRAY_SIZE(anubis_default_nand_part),
705630db	215	.partitions = anubis_default_nand_part,
7efb833d BD	216	},
	217	};
	218
	219	static void anubis_nand_select(struct s3c2410_nand_set *set, int slot)
	220	{
	221	unsigned int tmp;
	222
	223	slot = set->nr_map[slot] & 3;
	224
	225	pr_debug("anubis_nand: selecting slot %d (set %p,%p)\n",
	226	slot, set, set->nr_map);
	227
	228	tmp = __raw_readb(ANUBIS_VA_CTRL1);
	229	tmp &= ~ANUBIS_CTRL1_NANDSEL;
	230	tmp \|= slot;
	231
	232	pr_debug("anubis_nand: ctrl1 now %02x\n", tmp);
	233
	234	__raw_writeb(tmp, ANUBIS_VA_CTRL1);
	235	}
	236
	237	static struct s3c2410_platform_nand anubis_nand_info = {
	238	.tacls = 25,
661e6acf BD	239	.twrph0 = 55,
661e6acf BD	240	.twrph1 = 40,
7efb833d BD	241	.nr_sets = ARRAY_SIZE(anubis_nand_sets),
	242	.sets = anubis_nand_sets,
	243	.select_chip = anubis_nand_select,
	244	};
	245
bf1c56a3 BD	246	/* IDE channels */
bf1c56a3 BD	247
019dbaa1	248	static struct pata_platform_info anubis_ide_platdata = {
b9db83af BD	249	.ioport_shift = 5,
	250	};
	251
bf1c56a3 BD	252	static struct resource anubis_ide0_resource[] = {
	253	{
	254	.start = S3C2410_CS3,
	255	.end = S3C2410_CS3 + (8*32) - 1,
	256	.flags = IORESOURCE_MEM,
	257	}, {
b9db83af BD	258	.start = S3C2410_CS3 + (1<<26) + (6*32),
b9db83af BD	259	.end = S3C2410_CS3 + (1<<26) + (7*32) - 1,
bf1c56a3 BD	260	.flags = IORESOURCE_MEM,
	261	}, {
	262	.start = IRQ_IDE0,
	263	.end = IRQ_IDE0,
	264	.flags = IORESOURCE_IRQ,
	265	},
	266	};
	267
	268	static struct platform_device anubis_device_ide0 = {
b9db83af	269	.name = "pata_platform",
bf1c56a3 BD	270	.id = 0,
	271	.num_resources = ARRAY_SIZE(anubis_ide0_resource),
	272	.resource = anubis_ide0_resource,
b9db83af BD	273	.dev = {
	274	.platform_data = &anubis_ide_platdata,
	275	.coherent_dma_mask = ~0,
	276	},
bf1c56a3 BD	277	};
	278
	279	static struct resource anubis_ide1_resource[] = {
	280	{
	281	.start = S3C2410_CS4,
	282	.end = S3C2410_CS4 + (8*32) - 1,
	283	.flags = IORESOURCE_MEM,
	284	}, {
b9db83af BD	285	.start = S3C2410_CS4 + (1<<26) + (6*32),
b9db83af BD	286	.end = S3C2410_CS4 + (1<<26) + (7*32) - 1,
bf1c56a3 BD	287	.flags = IORESOURCE_MEM,
	288	}, {
	289	.start = IRQ_IDE0,
	290	.end = IRQ_IDE0,
	291	.flags = IORESOURCE_IRQ,
	292	},
	293	};
	294
bf1c56a3	295	static struct platform_device anubis_device_ide1 = {
b9db83af	296	.name = "pata_platform",
bf1c56a3 BD	297	.id = 1,
	298	.num_resources = ARRAY_SIZE(anubis_ide1_resource),
	299	.resource = anubis_ide1_resource,
b9db83af BD	300	.dev = {
	301	.platform_data = &anubis_ide_platdata,
	302	.coherent_dma_mask = ~0,
	303	},
bf1c56a3	304	};
7efb833d	305
eac1d8da BD	306	/* Asix AX88796 10/100 ethernet controller */
	307
	308	static struct ax_plat_data anubis_asix_platdata = {
	309	.flags = AXFLG_MAC_FROMDEV,
	310	.wordlength = 2,
	311	.dcr_val = 0x48,
	312	.rcr_val = 0x40,
	313	};
	314
	315	static struct resource anubis_asix_resource[] = {
	316	[0] = {
	317	.start = S3C2410_CS5,
	318	.end = S3C2410_CS5 + (0x20 * 0x20) -1,
	319	.flags = IORESOURCE_MEM
	320	},
	321	[1] = {
	322	.start = IRQ_ASIX,
	323	.end = IRQ_ASIX,
	324	.flags = IORESOURCE_IRQ
	325	}
	326	};
	327
	328	static struct platform_device anubis_device_asix = {
	329	.name = "ax88796",
	330	.id = 0,
	331	.num_resources = ARRAY_SIZE(anubis_asix_resource),
	332	.resource = anubis_asix_resource,
	333	.dev = {
	334	.platform_data = &anubis_asix_platdata,
	335	}
	336	};
	337
8a9ccb7f BD	338	/* SM501 */
	339
	340	static struct resource anubis_sm501_resource[] = {
	341	[0] = {
	342	.start = S3C2410_CS2,
	343	.end = S3C2410_CS2 + SZ_8M,
	344	.flags = IORESOURCE_MEM,
	345	},
	346	[1] = {
	347	.start = S3C2410_CS2 + SZ_64M - SZ_2M,
	348	.end = S3C2410_CS2 + SZ_64M - 1,
	349	.flags = IORESOURCE_MEM,
	350	},
	351	[2] = {
	352	.start = IRQ_EINT0,
	353	.end = IRQ_EINT0,
	354	.flags = IORESOURCE_IRQ,
	355	},
	356	};
	357
	358	static struct sm501_initdata anubis_sm501_initdata = {
	359	.gpio_high = {
	360	.set = 0x3F000000, /* 24bit panel */
	361	.mask = 0x0,
	362	},
	363	.misc_timing = {
	364	.set = 0x010100, /* SDRAM timing */
	365	.mask = 0x1F1F00,
	366	},
	367	.misc_control = {
	368	.set = SM501_MISC_PNL_24BIT,
	369	.mask = 0,
	370	},
	371
6290ce30 BD	372	.devices = SM501_USE_GPIO,
6290ce30 BD	373
8a9ccb7f BD	374	/* set the SDRAM and bus clocks */
	375	.mclk = 72 * MHZ,
	376	.m1xclk = 144 * MHZ,
	377	};
	378
	379	static struct sm501_platdata_gpio_i2c anubis_sm501_gpio_i2c[] = {
	380	[0] = {
6290ce30	381	.bus_num = 1,
8a9ccb7f BD	382	.pin_scl = 44,
	383	.pin_sda = 45,
	384	},
	385	[1] = {
6290ce30	386	.bus_num = 2,
8a9ccb7f BD	387	.pin_scl = 40,
	388	.pin_sda = 41,
	389	},
	390	};
	391
	392	static struct sm501_platdata anubis_sm501_platdata = {
	393	.init = &anubis_sm501_initdata,
6290ce30	394	.gpio_base = -1,
8a9ccb7f BD	395	.gpio_i2c = anubis_sm501_gpio_i2c,
	396	.gpio_i2c_nr = ARRAY_SIZE(anubis_sm501_gpio_i2c),
	397	};
	398
	399	static struct platform_device anubis_device_sm501 = {
	400	.name = "sm501",
	401	.id = 0,
	402	.num_resources = ARRAY_SIZE(anubis_sm501_resource),
	403	.resource = anubis_sm501_resource,
	404	.dev = {
	405	.platform_data = &anubis_sm501_platdata,
	406	},
	407	};
	408
7efb833d BD	409	/* Standard Anubis devices */
	410
	411	static struct platform_device *anubis_devices[] __initdata = {
	412	&s3c_device_usb,
	413	&s3c_device_wdt,
	414	&s3c_device_adc,
3e1b776c	415	&s3c_device_i2c0,
7efb833d BD	416	&s3c_device_rtc,
7efb833d BD	417	&s3c_device_nand,
bf1c56a3 BD	418	&anubis_device_ide0,
bf1c56a3 BD	419	&anubis_device_ide1,
eac1d8da	420	&anubis_device_asix,
8a9ccb7f	421	&anubis_device_sm501,
7efb833d BD	422	};
7efb833d BD	423
2bc7509f	424	static struct clk *anubis_clocks[] __initdata = {
7efb833d BD	425	&s3c24xx_dclk0,
	426	&s3c24xx_dclk1,
	427	&s3c24xx_clkout0,
	428	&s3c24xx_clkout1,
	429	&s3c24xx_uclk,
	430	};
	431
7a28db61 BD	432	/* I2C devices. */
	433
	434	static struct i2c_board_info anubis_i2c_devs[] __initdata = {
	435	{
	436	I2C_BOARD_INFO("tps65011", 0x48),
	437	.irq = IRQ_EINT20,
	438	}
	439	};
	440
4d3a3469 BD	441	/* Audio setup */
	442	static struct s3c24xx_audio_simtec_pdata __initdata anubis_audio = {
	443	.have_mic = 1,
	444	.have_lout = 1,
	445	.output_cdclk = 1,
	446	.use_mpllin = 1,
	447	.amp_gpio = S3C2410_GPB(2),
	448	.amp_gain[0] = S3C2410_GPD(10),
	449	.amp_gain[1] = S3C2410_GPD(11),
	450	};
	451
5fe10ab1	452	static void __init anubis_map_io(void)
7efb833d BD	453	{
	454	/* initialise the clocks */
	455
d96a9804	456	s3c24xx_dclk0.parent = &clk_upll;
7efb833d BD	457	s3c24xx_dclk0.rate = 1210001000;
7efb833d BD	458
d96a9804	459	s3c24xx_dclk1.parent = &clk_upll;
7efb833d BD	460	s3c24xx_dclk1.rate = 2410001000;
	461
	462	s3c24xx_clkout0.parent = &s3c24xx_dclk0;
	463	s3c24xx_clkout1.parent = &s3c24xx_dclk1;
	464
	465	s3c24xx_uclk.parent = &s3c24xx_clkout1;
	466
ce89c206 BD	467	s3c24xx_register_clocks(anubis_clocks, ARRAY_SIZE(anubis_clocks));
ce89c206 BD	468
7efb833d BD	469	s3c_device_nand.dev.platform_data = &anubis_nand_info;
	470
	471	s3c24xx_init_io(anubis_iodesc, ARRAY_SIZE(anubis_iodesc));
	472	s3c24xx_init_clocks(0);
	473	s3c24xx_init_uarts(anubis_uartcfgs, ARRAY_SIZE(anubis_uartcfgs));
7efb833d	474
ad3613f4 BD	475	/* check for the newer revision boards with large page nand */
	476
	477	if ((__raw_readb(ANUBIS_VA_IDREG) & ANUBIS_IDREG_REVMASK) >= 4) {
	478	printk(KERN_INFO "ANUBIS-B detected (revision %d)\n",
	479	__raw_readb(ANUBIS_VA_IDREG) & ANUBIS_IDREG_REVMASK);
	480	anubis_nand_sets[0].partitions = anubis_default_nand_part_large;
	481	anubis_nand_sets[0].nr_partitions = ARRAY_SIZE(anubis_default_nand_part_large);
	482	} else {
	483	/* ensure that the GPIO is setup */
070276d5	484	s3c2410_gpio_setpin(S3C2410_GPA(0), 1);
ad3613f4	485	}
7efb833d BD	486	}
7efb833d BD	487
57e5171c BD	488	static void __init anubis_init(void)
57e5171c BD	489	{
3e1b776c	490	s3c_i2c0_set_platdata(NULL);
4d3a3469	491	simtec_audio_add(NULL, false, &anubis_audio);
57e5171c	492	platform_add_devices(anubis_devices, ARRAY_SIZE(anubis_devices));
7a28db61 BD	493
	494	i2c_register_board_info(0, anubis_i2c_devs,
	495	ARRAY_SIZE(anubis_i2c_devs));
57e5171c BD	496	}
	497
	498
7efb833d BD	499	MACHINE_START(ANUBIS, "Simtec-Anubis")
7efb833d BD	500	/* Maintainer: Ben Dooks <ben@simtec.co.uk> */
7efb833d BD	501	.phys_io = S3C2410_PA_UART,
	502	.io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
	503	.boot_params = S3C2410_SDRAM_PA + 0x100,
	504	.map_io = anubis_map_io,
57e5171c	505	.init_machine = anubis_init,
7efb833d BD	506	.init_irq = s3c24xx_init_irq,
	507	.timer = &s3c24xx_timer,
	508	MACHINE_END