[linux-2.6-block.git] / arch / arm / mach-s3c2410 / mach-bast.c

/* linux/arch/arm/mach-s3c2410/mach-bast.c
 *
 * Copyright (c) 2003-2005,2008 Simtec Electronics
 *   Ben Dooks <ben@simtec.co.uk>
 *
 * http://www.simtec.co.uk/products/EB2410ITX/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/gpio.h>
#include <linux/sysdev.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <linux/dm9000.h>
#include <linux/ata_platform.h>
#include <linux/i2c.h>
#include <linux/io.h>

#include <net/ax88796.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>

#include <mach/bast-map.h>
#include <mach/bast-irq.h>
#include <mach/bast-cpld.h>

#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach-types.h>

//#include <asm/debug-ll.h>
#include <plat/regs-serial.h>
#include <mach/regs-gpio.h>
#include <mach/regs-mem.h>
#include <mach/regs-lcd.h>

#include <plat/hwmon.h>
#include <plat/nand.h>
#include <plat/iic.h>
#include <mach/fb.h>

#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/partitions.h>

#include <linux/serial_8250.h>

#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#include <plat/cpu-freq.h>
#include <plat/audio-simtec.h>

#include "usb-simtec.h"
#include "nor-simtec.h"

#define COPYRIGHT ", (c) 2004-2005 Simtec Electronics"

/* macros for virtual address mods for the io space entries */
#define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5)
#define VA_C4(item) ((unsigned long)(item) + BAST_VAM_CS4)
#define VA_C3(item) ((unsigned long)(item) + BAST_VAM_CS3)
#define VA_C2(item) ((unsigned long)(item) + BAST_VAM_CS2)

/* macros to modify the physical addresses for io space */

#define PA_CS2(item) (__phys_to_pfn((item) + S3C2410_CS2))
#define PA_CS3(item) (__phys_to_pfn((item) + S3C2410_CS3))
#define PA_CS4(item) (__phys_to_pfn((item) + S3C2410_CS4))
#define PA_CS5(item) (__phys_to_pfn((item) + S3C2410_CS5))

static struct map_desc bast_iodesc[] __initdata = {
  /* ISA IO areas */
  {
	  .virtual	= (u32)S3C24XX_VA_ISA_BYTE,
	  .pfn		= PA_CS2(BAST_PA_ISAIO),
	  .length	= SZ_16M,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)S3C24XX_VA_ISA_WORD,
	  .pfn		= PA_CS3(BAST_PA_ISAIO),
	  .length	= SZ_16M,
	  .type		= MT_DEVICE,
  },
  /* bast CPLD control registers, and external interrupt controls */
  {
	  .virtual	= (u32)BAST_VA_CTRL1,
	  .pfn		= __phys_to_pfn(BAST_PA_CTRL1),
	  .length	= SZ_1M,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)BAST_VA_CTRL2,
	  .pfn		= __phys_to_pfn(BAST_PA_CTRL2),
	  .length	= SZ_1M,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)BAST_VA_CTRL3,
	  .pfn		= __phys_to_pfn(BAST_PA_CTRL3),
	  .length	= SZ_1M,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)BAST_VA_CTRL4,
	  .pfn		= __phys_to_pfn(BAST_PA_CTRL4),
	  .length	= SZ_1M,
	  .type		= MT_DEVICE,
  },
  /* PC104 IRQ mux */
  {
	  .virtual	= (u32)BAST_VA_PC104_IRQREQ,
	  .pfn		= __phys_to_pfn(BAST_PA_PC104_IRQREQ),
	  .length	= SZ_1M,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)BAST_VA_PC104_IRQRAW,
	  .pfn		= __phys_to_pfn(BAST_PA_PC104_IRQRAW),
	  .length	= SZ_1M,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)BAST_VA_PC104_IRQMASK,
	  .pfn		= __phys_to_pfn(BAST_PA_PC104_IRQMASK),
	  .length	= SZ_1M,
	  .type		= MT_DEVICE,
  },

  /* peripheral space... one for each of fast/slow/byte/16bit */
  /* note, ide is only decoded in word space, even though some registers
   * are only 8bit */

  /* slow, byte */
  { VA_C2(BAST_VA_ISAIO),   PA_CS2(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
  { VA_C2(BAST_VA_ISAMEM),  PA_CS2(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
  { VA_C2(BAST_VA_SUPERIO), PA_CS2(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },

  /* slow, word */
  { VA_C3(BAST_VA_ISAIO),   PA_CS3(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
  { VA_C3(BAST_VA_ISAMEM),  PA_CS3(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
  { VA_C3(BAST_VA_SUPERIO), PA_CS3(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },

  /* fast, byte */
  { VA_C4(BAST_VA_ISAIO),   PA_CS4(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
  { VA_C4(BAST_VA_ISAMEM),  PA_CS4(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
  { VA_C4(BAST_VA_SUPERIO), PA_CS4(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },

  /* fast, word */
  { VA_C5(BAST_VA_ISAIO),   PA_CS5(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
  { VA_C5(BAST_VA_ISAMEM),  PA_CS5(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
  { VA_C5(BAST_VA_SUPERIO), PA_CS5(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
};

#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE

static struct s3c24xx_uart_clksrc bast_serial_clocks[] = {
	[0] = {
		.name		= "uclk",
		.divisor	= 1,
		.min_baud	= 0,
		.max_baud	= 0,
	},
	[1] = {
		.name		= "pclk",
		.divisor	= 1,
		.min_baud	= 0,
		.max_baud	= 0,
	}
};


static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
	[0] = {
		.hwport	     = 0,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
		.clocks	     = bast_serial_clocks,
		.clocks_size = ARRAY_SIZE(bast_serial_clocks),
	},
	[1] = {
		.hwport	     = 1,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
		.clocks	     = bast_serial_clocks,
		.clocks_size = ARRAY_SIZE(bast_serial_clocks),
	},
	/* port 2 is not actually used */
	[2] = {
		.hwport	     = 2,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
		.clocks	     = bast_serial_clocks,
		.clocks_size = ARRAY_SIZE(bast_serial_clocks),
	}
};

/* NAND Flash on BAST board */

#ifdef CONFIG_PM
static int bast_pm_suspend(struct sys_device *sd, pm_message_t state)
{
	/* ensure that an nRESET is not generated on resume. */
	s3c2410_gpio_setpin(S3C2410_GPA(21), 1);
	s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPIO_OUTPUT);

	return 0;
}

static int bast_pm_resume(struct sys_device *sd)
{
	s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
	return 0;
}

#else
#define bast_pm_suspend NULL
#define bast_pm_resume NULL
#endif

static struct sysdev_class bast_pm_sysclass = {
	.name		= "mach-bast",
	.suspend	= bast_pm_suspend,
	.resume		= bast_pm_resume,
};

static struct sys_device bast_pm_sysdev = {
	.cls		= &bast_pm_sysclass,
};

static int smartmedia_map[] = { 0 };
static int chip0_map[] = { 1 };
static int chip1_map[] = { 2 };
static int chip2_map[] = { 3 };

static struct mtd_partition bast_default_nand_part[] = {
	[0] = {
		.name	= "Boot Agent",
		.size	= SZ_16K,
		.offset	= 0,
	},
	[1] = {
		.name	= "/boot",
		.size	= SZ_4M - SZ_16K,
		.offset	= SZ_16K,
	},
	[2] = {
		.name	= "user",
		.offset	= SZ_4M,
		.size	= MTDPART_SIZ_FULL,
	}
};

/* the bast has 4 selectable slots for nand-flash, the three
 * on-board chip areas, as well as the external SmartMedia
 * slot.
 *
 * Note, there is no current hot-plug support for the SmartMedia
 * socket.
*/

static struct s3c2410_nand_set bast_nand_sets[] = {
	[0] = {
		.name		= "SmartMedia",
		.nr_chips	= 1,
		.nr_map		= smartmedia_map,
		.nr_partitions	= ARRAY_SIZE(bast_default_nand_part),
		.partitions	= bast_default_nand_part,
	},
	[1] = {
		.name		= "chip0",
		.nr_chips	= 1,
		.nr_map		= chip0_map,
		.nr_partitions	= ARRAY_SIZE(bast_default_nand_part),
		.partitions	= bast_default_nand_part,
	},
	[2] = {
		.name		= "chip1",
		.nr_chips	= 1,
		.nr_map		= chip1_map,
		.nr_partitions	= ARRAY_SIZE(bast_default_nand_part),
		.partitions	= bast_default_nand_part,
	},
	[3] = {
		.name		= "chip2",
		.nr_chips	= 1,
		.nr_map		= chip2_map,
		.nr_partitions	= ARRAY_SIZE(bast_default_nand_part),
		.partitions	= bast_default_nand_part,
	}
};

static void bast_nand_select(struct s3c2410_nand_set *set, int slot)
{
	unsigned int tmp;

	slot = set->nr_map[slot] & 3;

	pr_debug("bast_nand: selecting slot %d (set %p,%p)\n",
		 slot, set, set->nr_map);

	tmp = __raw_readb(BAST_VA_CTRL2);
	tmp &= BAST_CPLD_CTLR2_IDERST;
	tmp |= slot;
	tmp |= BAST_CPLD_CTRL2_WNAND;

	pr_debug("bast_nand: ctrl2 now %02x\n", tmp);

	__raw_writeb(tmp, BAST_VA_CTRL2);
}

static struct s3c2410_platform_nand bast_nand_info = {
	.tacls		= 30,
	.twrph0		= 60,
	.twrph1		= 60,
	.nr_sets	= ARRAY_SIZE(bast_nand_sets),
	.sets		= bast_nand_sets,
	.select_chip	= bast_nand_select,
};

/* DM9000 */

static struct resource bast_dm9k_resource[] = {
	[0] = {
		.start = S3C2410_CS5 + BAST_PA_DM9000,
		.end   = S3C2410_CS5 + BAST_PA_DM9000 + 3,
		.flags = IORESOURCE_MEM,
	},
	[1] = {
		.start = S3C2410_CS5 + BAST_PA_DM9000 + 0x40,
		.end   = S3C2410_CS5 + BAST_PA_DM9000 + 0x40 + 0x3f,
		.flags = IORESOURCE_MEM,
	},
	[2] = {
		.start = IRQ_DM9000,
		.end   = IRQ_DM9000,
		.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
	}

};

/* for the moment we limit ourselves to 16bit IO until some
 * better IO routines can be written and tested
*/

static struct dm9000_plat_data bast_dm9k_platdata = {
	.flags		= DM9000_PLATF_16BITONLY,
};

static struct platform_device bast_device_dm9k = {
	.name		= "dm9000",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(bast_dm9k_resource),
	.resource	= bast_dm9k_resource,
	.dev		= {
		.platform_data = &bast_dm9k_platdata,
	}
};

/* serial devices */

#define SERIAL_BASE  (S3C2410_CS2 + BAST_PA_SUPERIO)
#define SERIAL_FLAGS (UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_SHARE_IRQ)
#define SERIAL_CLK   (1843200)

static struct plat_serial8250_port bast_sio_data[] = {
	[0] = {
		.mapbase	= SERIAL_BASE + 0x2f8,
		.irq		= IRQ_PCSERIAL1,
		.flags		= SERIAL_FLAGS,
		.iotype		= UPIO_MEM,
		.regshift	= 0,
		.uartclk	= SERIAL_CLK,
	},
	[1] = {
		.mapbase	= SERIAL_BASE + 0x3f8,
		.irq		= IRQ_PCSERIAL2,
		.flags		= SERIAL_FLAGS,
		.iotype		= UPIO_MEM,
		.regshift	= 0,
		.uartclk	= SERIAL_CLK,
	},
	{ }
};

static struct platform_device bast_sio = {
	.name			= "serial8250",
	.id			= PLAT8250_DEV_PLATFORM,
	.dev			= {
		.platform_data	= &bast_sio_data,
	},
};

/* we have devices on the bus which cannot work much over the
 * standard 100KHz i2c bus frequency
*/

static struct s3c2410_platform_i2c __initdata bast_i2c_info = {
	.flags		= 0,
	.slave_addr	= 0x10,
	.frequency	= 100*1000,
};

/* Asix AX88796 10/100 ethernet controller */

static struct ax_plat_data bast_asix_platdata = {
	.flags		= AXFLG_MAC_FROMDEV,
	.wordlength	= 2,
	.dcr_val	= 0x48,
	.rcr_val	= 0x40,
};

static struct resource bast_asix_resource[] = {
	[0] = {
		.start = S3C2410_CS5 + BAST_PA_ASIXNET,
		.end   = S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20) - 1,
		.flags = IORESOURCE_MEM,
	},
	[1] = {
		.start = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20),
		.end   = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20),
		.flags = IORESOURCE_MEM,
	},
	[2] = {
		.start = IRQ_ASIX,
		.end   = IRQ_ASIX,
		.flags = IORESOURCE_IRQ
	}
};

static struct platform_device bast_device_asix = {
	.name		= "ax88796",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(bast_asix_resource),
	.resource	= bast_asix_resource,
	.dev		= {
		.platform_data = &bast_asix_platdata
	}
};

/* Asix AX88796 10/100 ethernet controller parallel port */

static struct resource bast_asixpp_resource[] = {
	[0] = {
		.start = S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20),
		.end   = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1b * 0x20) - 1,
		.flags = IORESOURCE_MEM,
	}
};

static struct platform_device bast_device_axpp = {
	.name		= "ax88796-pp",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(bast_asixpp_resource),
	.resource	= bast_asixpp_resource,
};

/* LCD/VGA controller */

static struct s3c2410fb_display __initdata bast_lcd_info[] = {
	{
		.type		= S3C2410_LCDCON1_TFT,
		.width		= 640,
		.height		= 480,

		.pixclock	= 33333,
		.xres		= 640,
		.yres		= 480,
		.bpp		= 4,
		.left_margin	= 40,
		.right_margin	= 20,
		.hsync_len	= 88,
		.upper_margin	= 30,
		.lower_margin	= 32,
		.vsync_len	= 3,

		.lcdcon5	= 0x00014b02,
	},
	{
		.type		= S3C2410_LCDCON1_TFT,
		.width		= 640,
		.height		= 480,

		.pixclock	= 33333,
		.xres		= 640,
		.yres		= 480,
		.bpp		= 8,
		.left_margin	= 40,
		.right_margin	= 20,
		.hsync_len	= 88,
		.upper_margin	= 30,
		.lower_margin	= 32,
		.vsync_len	= 3,

		.lcdcon5	= 0x00014b02,
	},
	{
		.type		= S3C2410_LCDCON1_TFT,
		.width		= 640,
		.height		= 480,

		.pixclock	= 33333,
		.xres		= 640,
		.yres		= 480,
		.bpp		= 16,
		.left_margin	= 40,
		.right_margin	= 20,
		.hsync_len	= 88,
		.upper_margin	= 30,
		.lower_margin	= 32,
		.vsync_len	= 3,

		.lcdcon5	= 0x00014b02,
	},
};

/* LCD/VGA controller */

static struct s3c2410fb_mach_info __initdata bast_fb_info = {

	.displays = bast_lcd_info,
	.num_displays = ARRAY_SIZE(bast_lcd_info),
	.default_display = 1,
};

/* I2C devices fitted. */

static struct i2c_board_info bast_i2c_devs[] __initdata = {
	{
		I2C_BOARD_INFO("tlv320aic23", 0x1a),
	}, {
		I2C_BOARD_INFO("simtec-pmu", 0x6b),
	}, {
		I2C_BOARD_INFO("ch7013", 0x75),
	},
};

static struct s3c_hwmon_pdata bast_hwmon_info = {
	/* LCD contrast (0-6.6V) */
	.in[0] = &(struct s3c_hwmon_chcfg) {
		.name		= "lcd-contrast",
		.mult		= 3300,
		.div		= 512,
	},
	/* LED current feedback */
	.in[1] = &(struct s3c_hwmon_chcfg) {
		.name		= "led-feedback",
		.mult		= 3300,
		.div		= 1024,
	},
	/* LCD feedback (0-6.6V) */
	.in[2] = &(struct s3c_hwmon_chcfg) {
		.name		= "lcd-feedback",
		.mult		= 3300,
		.div		= 512,
	},
	/* Vcore (1.8-2.0V), Vref 3.3V  */
	.in[3] = &(struct s3c_hwmon_chcfg) {
		.name		= "vcore",
		.mult		= 3300,
		.div		= 1024,
	},
};

/* Standard BAST devices */
// cat /sys/devices/platform/s3c24xx-adc/s3c-hwmon/in_0

static struct platform_device *bast_devices[] __initdata = {
	&s3c_device_usb,
	&s3c_device_lcd,
	&s3c_device_wdt,
	&s3c_device_i2c0,
 	&s3c_device_rtc,
	&s3c_device_nand,
	&s3c_device_adc,
	&s3c_device_hwmon,
	&bast_device_dm9k,
	&bast_device_asix,
	&bast_device_axpp,
	&bast_sio,
};

static struct clk *bast_clocks[] __initdata = {
	&s3c24xx_dclk0,
	&s3c24xx_dclk1,
	&s3c24xx_clkout0,
	&s3c24xx_clkout1,
	&s3c24xx_uclk,
};

static struct s3c_cpufreq_board __initdata bast_cpufreq = {
	.refresh	= 7800, /* 7.8usec */
	.auto_io	= 1,
	.need_io	= 1,
};

static struct s3c24xx_audio_simtec_pdata __initdata bast_audio = {
	.have_mic	= 1,
	.have_lout	= 1,
};

static void __init bast_map_io(void)
{
	/* initialise the clocks */

	s3c24xx_dclk0.parent = &clk_upll;
	s3c24xx_dclk0.rate   = 12*1000*1000;

	s3c24xx_dclk1.parent = &clk_upll;
	s3c24xx_dclk1.rate   = 24*1000*1000;

	s3c24xx_clkout0.parent  = &s3c24xx_dclk0;
	s3c24xx_clkout1.parent  = &s3c24xx_dclk1;

	s3c24xx_uclk.parent  = &s3c24xx_clkout1;

	s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks));

	s3c_device_nand.dev.platform_data = &bast_nand_info;
	s3c_device_hwmon.dev.platform_data = &bast_hwmon_info;

	s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
	s3c24xx_init_clocks(0);
	s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
}

static void __init bast_init(void)
{
	sysdev_class_register(&bast_pm_sysclass);
	sysdev_register(&bast_pm_sysdev);

	s3c_i2c0_set_platdata(&bast_i2c_info);
	s3c24xx_fb_set_platdata(&bast_fb_info);
	platform_add_devices(bast_devices, ARRAY_SIZE(bast_devices));

	i2c_register_board_info(0, bast_i2c_devs,
				ARRAY_SIZE(bast_i2c_devs));

	usb_simtec_init();
	nor_simtec_init();
	simtec_audio_add(NULL, true, &bast_audio);

	s3c_cpufreq_setboard(&bast_cpufreq);
}

MACHINE_START(BAST, "Simtec-BAST")
	/* Maintainer: Ben Dooks <ben@simtec.co.uk> */
	.phys_io	= S3C2410_PA_UART,
	.io_pg_offst	= (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
	.boot_params	= S3C2410_SDRAM_PA + 0x100,
	.map_io		= bast_map_io,
	.init_irq	= s3c24xx_init_irq,
	.init_machine	= bast_init,
	.timer		= &s3c24xx_timer,
MACHINE_END
Commit	Line	Data
1da177e4 LT	1	/* linux/arch/arm/mach-s3c2410/mach-bast.c
1da177e4 LT	2	*
042cf0f2	3	* Copyright (c) 2003-2005,2008 Simtec Electronics
1da177e4 LT	4	* Ben Dooks <ben@simtec.co.uk>
	5	*
	6	* http://www.simtec.co.uk/products/EB2410ITX/
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
1da177e4 LT	11	*/
	12
	13	#include <linux/kernel.h>
	14	#include <linux/types.h>
	15	#include <linux/interrupt.h>
	16	#include <linux/list.h>
	17	#include <linux/timer.h>
	18	#include <linux/init.h>
ec976d6e	19	#include <linux/gpio.h>
6ddc4b07	20	#include <linux/sysdev.h>
b6d1f542	21	#include <linux/serial_core.h>
d052d1be	22	#include <linux/platform_device.h>
d97a666f	23	#include <linux/dm9000.h>
b7a12d19	24	#include <linux/ata_platform.h>
042cf0f2	25	#include <linux/i2c.h>
fced80c7	26	#include <linux/io.h>
1da177e4	27
5ce4b1fe BD	28	#include <net/ax88796.h>
5ce4b1fe BD	29
1da177e4 LT	30	#include <asm/mach/arch.h>
	31	#include <asm/mach/map.h>
	32	#include <asm/mach/irq.h>
	33
a09e64fb RK	34	#include <mach/bast-map.h>
	35	#include <mach/bast-irq.h>
	36	#include <mach/bast-cpld.h>
1da177e4	37
a09e64fb	38	#include <mach/hardware.h>
1da177e4 LT	39	#include <asm/irq.h>
	40	#include <asm/mach-types.h>
	41
	42	//#include <asm/debug-ll.h>
a2b7ba9c	43	#include <plat/regs-serial.h>
a09e64fb RK	44	#include <mach/regs-gpio.h>
	45	#include <mach/regs-mem.h>
	46	#include <mach/regs-lcd.h>
58c8d570	47
885f9ebe	48	#include <plat/hwmon.h>
7926b5a3	49	#include <plat/nand.h>
9498cb79	50	#include <plat/iic.h>
a09e64fb	51	#include <mach/fb.h>
1da177e4 LT	52
	53	#include <linux/mtd/mtd.h>
	54	#include <linux/mtd/nand.h>
	55	#include <linux/mtd/nand_ecc.h>
	56	#include <linux/mtd/partitions.h>
	57
65cc3370 BD	58	#include <linux/serial_8250.h>
65cc3370 BD	59
d5120ae7	60	#include <plat/clock.h>
a2b7ba9c BD	61	#include <plat/devs.h>
a2b7ba9c BD	62	#include <plat/cpu.h>
ca0b4901	63	#include <plat/cpu-freq.h>
4d3a3469	64	#include <plat/audio-simtec.h>
9d529c6e	65
1da177e4	66	#include "usb-simtec.h"
9d529c6e	67	#include "nor-simtec.h"
1da177e4 LT	68
	69	#define COPYRIGHT ", (c) 2004-2005 Simtec Electronics"
	70
	71	/* macros for virtual address mods for the io space entries */
	72	#define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5)
	73	#define VA_C4(item) ((unsigned long)(item) + BAST_VAM_CS4)
	74	#define VA_C3(item) ((unsigned long)(item) + BAST_VAM_CS3)
	75	#define VA_C2(item) ((unsigned long)(item) + BAST_VAM_CS2)
	76
	77	/* macros to modify the physical addresses for io space */
	78
1d23b65d BD	79	#define PA_CS2(item) (__phys_to_pfn((item) + S3C2410_CS2))
	80	#define PA_CS3(item) (__phys_to_pfn((item) + S3C2410_CS3))
	81	#define PA_CS4(item) (__phys_to_pfn((item) + S3C2410_CS4))
	82	#define PA_CS5(item) (__phys_to_pfn((item) + S3C2410_CS5))
1da177e4 LT	83
	84	static struct map_desc bast_iodesc[] __initdata = {
	85	/* ISA IO areas */
1d23b65d BD	86	{
	87	.virtual = (u32)S3C24XX_VA_ISA_BYTE,
	88	.pfn = PA_CS2(BAST_PA_ISAIO),
	89	.length = SZ_16M,
	90	.type = MT_DEVICE,
	91	}, {
	92	.virtual = (u32)S3C24XX_VA_ISA_WORD,
	93	.pfn = PA_CS3(BAST_PA_ISAIO),
	94	.length = SZ_16M,
	95	.type = MT_DEVICE,
	96	},
1da177e4	97	/* bast CPLD control registers, and external interrupt controls */
1d23b65d BD	98	{
	99	.virtual = (u32)BAST_VA_CTRL1,
	100	.pfn = __phys_to_pfn(BAST_PA_CTRL1),
	101	.length = SZ_1M,
	102	.type = MT_DEVICE,
	103	}, {
	104	.virtual = (u32)BAST_VA_CTRL2,
	105	.pfn = __phys_to_pfn(BAST_PA_CTRL2),
	106	.length = SZ_1M,
	107	.type = MT_DEVICE,
	108	}, {
	109	.virtual = (u32)BAST_VA_CTRL3,
	110	.pfn = __phys_to_pfn(BAST_PA_CTRL3),
	111	.length = SZ_1M,
	112	.type = MT_DEVICE,
	113	}, {
	114	.virtual = (u32)BAST_VA_CTRL4,
	115	.pfn = __phys_to_pfn(BAST_PA_CTRL4),
	116	.length = SZ_1M,
	117	.type = MT_DEVICE,
	118	},
1da177e4	119	/* PC104 IRQ mux */
1d23b65d BD	120	{
	121	.virtual = (u32)BAST_VA_PC104_IRQREQ,
	122	.pfn = __phys_to_pfn(BAST_PA_PC104_IRQREQ),
	123	.length = SZ_1M,
	124	.type = MT_DEVICE,
	125	}, {
	126	.virtual = (u32)BAST_VA_PC104_IRQRAW,
	127	.pfn = __phys_to_pfn(BAST_PA_PC104_IRQRAW),
	128	.length = SZ_1M,
	129	.type = MT_DEVICE,
	130	}, {
	131	.virtual = (u32)BAST_VA_PC104_IRQMASK,
	132	.pfn = __phys_to_pfn(BAST_PA_PC104_IRQMASK),
	133	.length = SZ_1M,
	134	.type = MT_DEVICE,
	135	},
1da177e4 LT	136
	137	/* peripheral space... one for each of fast/slow/byte/16bit */
	138	/* note, ide is only decoded in word space, even though some registers
	139	* are only 8bit */
	140
	141	/* slow, byte */
	142	{ VA_C2(BAST_VA_ISAIO), PA_CS2(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
	143	{ VA_C2(BAST_VA_ISAMEM), PA_CS2(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
1da177e4	144	{ VA_C2(BAST_VA_SUPERIO), PA_CS2(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
1da177e4 LT	145
	146	/* slow, word */
	147	{ VA_C3(BAST_VA_ISAIO), PA_CS3(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
	148	{ VA_C3(BAST_VA_ISAMEM), PA_CS3(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
1da177e4	149	{ VA_C3(BAST_VA_SUPERIO), PA_CS3(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
1da177e4 LT	150
	151	/* fast, byte */
	152	{ VA_C4(BAST_VA_ISAIO), PA_CS4(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
	153	{ VA_C4(BAST_VA_ISAMEM), PA_CS4(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
1da177e4	154	{ VA_C4(BAST_VA_SUPERIO), PA_CS4(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
1da177e4 LT	155
	156	/* fast, word */
	157	{ VA_C5(BAST_VA_ISAIO), PA_CS5(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
	158	{ VA_C5(BAST_VA_ISAMEM), PA_CS5(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
1da177e4	159	{ VA_C5(BAST_VA_SUPERIO), PA_CS5(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
1da177e4 LT	160	};
	161
	162	#define UCON S3C2410_UCON_DEFAULT \| S3C2410_UCON_UCLK
	163	#define ULCON S3C2410_LCON_CS8 \| S3C2410_LCON_PNONE \| S3C2410_LCON_STOPB
	164	#define UFCON S3C2410_UFCON_RXTRIG8 \| S3C2410_UFCON_FIFOMODE
	165
	166	static struct s3c24xx_uart_clksrc bast_serial_clocks[] = {
	167	[0] = {
	168	.name = "uclk",
	169	.divisor = 1,
	170	.min_baud = 0,
	171	.max_baud = 0,
	172	},
	173	[1] = {
	174	.name = "pclk",
	175	.divisor = 1,
	176	.min_baud = 0,
b526bf23	177	.max_baud = 0,
1da177e4 LT	178	}
	179	};
	180
	181
66a9b49a	182	static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
1da177e4 LT	183	[0] = {
	184	.hwport = 0,
	185	.flags = 0,
	186	.ucon = UCON,
	187	.ulcon = ULCON,
	188	.ufcon = UFCON,
	189	.clocks = bast_serial_clocks,
b526bf23	190	.clocks_size = ARRAY_SIZE(bast_serial_clocks),
1da177e4 LT	191	},
	192	[1] = {
	193	.hwport = 1,
	194	.flags = 0,
	195	.ucon = UCON,
	196	.ulcon = ULCON,
	197	.ufcon = UFCON,
	198	.clocks = bast_serial_clocks,
b526bf23	199	.clocks_size = ARRAY_SIZE(bast_serial_clocks),
1da177e4 LT	200	},
	201	/* port 2 is not actually used */
	202	[2] = {
	203	.hwport = 2,
	204	.flags = 0,
	205	.ucon = UCON,
	206	.ulcon = ULCON,
	207	.ufcon = UFCON,
	208	.clocks = bast_serial_clocks,
b526bf23	209	.clocks_size = ARRAY_SIZE(bast_serial_clocks),
1da177e4 LT	210	}
	211	};
	212
1da177e4 LT	213	/* NAND Flash on BAST board */
1da177e4 LT	214
6ddc4b07 BD	215	#ifdef CONFIG_PM
	216	static int bast_pm_suspend(struct sys_device *sd, pm_message_t state)
	217	{
	218	/* ensure that an nRESET is not generated on resume. */
070276d5 BD	219	s3c2410_gpio_setpin(S3C2410_GPA(21), 1);
070276d5 BD	220	s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPIO_OUTPUT);
6ddc4b07 BD	221
	222	return 0;
	223	}
	224
	225	static int bast_pm_resume(struct sys_device *sd)
	226	{
070276d5	227	s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
6ddc4b07 BD	228	return 0;
	229	}
	230
	231	#else
	232	#define bast_pm_suspend NULL
	233	#define bast_pm_resume NULL
	234	#endif
	235
	236	static struct sysdev_class bast_pm_sysclass = {
140749e2	237	.name = "mach-bast",
6ddc4b07 BD	238	.suspend = bast_pm_suspend,
	239	.resume = bast_pm_resume,
	240	};
	241
	242	static struct sys_device bast_pm_sysdev = {
	243	.cls = &bast_pm_sysclass,
	244	};
1da177e4 LT	245
	246	static int smartmedia_map[] = { 0 };
	247	static int chip0_map[] = { 1 };
	248	static int chip1_map[] = { 2 };
	249	static int chip2_map[] = { 3 };
	250
9f693d7b	251	static struct mtd_partition bast_default_nand_part[] = {
1da177e4 LT	252	[0] = {
	253	.name = "Boot Agent",
	254	.size = SZ_16K,
b526bf23	255	.offset = 0,
1da177e4 LT	256	},
	257	[1] = {
	258	.name = "/boot",
	259	.size = SZ_4M - SZ_16K,
	260	.offset = SZ_16K,
	261	},
	262	[2] = {
	263	.name = "user",
	264	.offset = SZ_4M,
	265	.size = MTDPART_SIZ_FULL,
	266	}
	267	};
	268
	269	/* the bast has 4 selectable slots for nand-flash, the three
	270	* on-board chip areas, as well as the external SmartMedia
	271	* slot.
	272	*
	273	* Note, there is no current hot-plug support for the SmartMedia
	274	* socket.
	275	*/
	276
	277	static struct s3c2410_nand_set bast_nand_sets[] = {
	278	[0] = {
	279	.name = "SmartMedia",
	280	.nr_chips = 1,
	281	.nr_map = smartmedia_map,
	282	.nr_partitions = ARRAY_SIZE(bast_default_nand_part),
b526bf23	283	.partitions = bast_default_nand_part,
1da177e4 LT	284	},
	285	[1] = {
	286	.name = "chip0",
	287	.nr_chips = 1,
	288	.nr_map = chip0_map,
	289	.nr_partitions = ARRAY_SIZE(bast_default_nand_part),
b526bf23	290	.partitions = bast_default_nand_part,
1da177e4 LT	291	},
	292	[2] = {
	293	.name = "chip1",
	294	.nr_chips = 1,
	295	.nr_map = chip1_map,
	296	.nr_partitions = ARRAY_SIZE(bast_default_nand_part),
b526bf23	297	.partitions = bast_default_nand_part,
1da177e4 LT	298	},
	299	[3] = {
	300	.name = "chip2",
	301	.nr_chips = 1,
	302	.nr_map = chip2_map,
	303	.nr_partitions = ARRAY_SIZE(bast_default_nand_part),
b526bf23	304	.partitions = bast_default_nand_part,
1da177e4 LT	305	}
	306	};
	307
	308	static void bast_nand_select(struct s3c2410_nand_set *set, int slot)
	309	{
	310	unsigned int tmp;
	311
	312	slot = set->nr_map[slot] & 3;
	313
	314	pr_debug("bast_nand: selecting slot %d (set %p,%p)\n",
	315	slot, set, set->nr_map);
	316
	317	tmp = __raw_readb(BAST_VA_CTRL2);
	318	tmp &= BAST_CPLD_CTLR2_IDERST;
	319	tmp \|= slot;
	320	tmp \|= BAST_CPLD_CTRL2_WNAND;
	321
	322	pr_debug("bast_nand: ctrl2 now %02x\n", tmp);
	323
	324	__raw_writeb(tmp, BAST_VA_CTRL2);
	325	}
	326
	327	static struct s3c2410_platform_nand bast_nand_info = {
b048dbf4 BD	328	.tacls = 30,
	329	.twrph0 = 60,
	330	.twrph1 = 60,
1da177e4 LT	331	.nr_sets = ARRAY_SIZE(bast_nand_sets),
	332	.sets = bast_nand_sets,
	333	.select_chip = bast_nand_select,
	334	};
	335
d97a666f BD	336	/* DM9000 */
	337
	338	static struct resource bast_dm9k_resource[] = {
	339	[0] = {
	340	.start = S3C2410_CS5 + BAST_PA_DM9000,
	341	.end = S3C2410_CS5 + BAST_PA_DM9000 + 3,
b526bf23	342	.flags = IORESOURCE_MEM,
d97a666f BD	343	},
	344	[1] = {
	345	.start = S3C2410_CS5 + BAST_PA_DM9000 + 0x40,
	346	.end = S3C2410_CS5 + BAST_PA_DM9000 + 0x40 + 0x3f,
b526bf23	347	.flags = IORESOURCE_MEM,
d97a666f BD	348	},
	349	[2] = {
	350	.start = IRQ_DM9000,
	351	.end = IRQ_DM9000,
9cf345e3	352	.flags = IORESOURCE_IRQ \| IORESOURCE_IRQ_HIGHLEVEL,
d97a666f BD	353	}
	354
	355	};
	356
	357	/* for the moment we limit ourselves to 16bit IO until some
	358	* better IO routines can be written and tested
	359	*/
	360
9f693d7b	361	static struct dm9000_plat_data bast_dm9k_platdata = {
b526bf23	362	.flags = DM9000_PLATF_16BITONLY,
d97a666f BD	363	};
	364
	365	static struct platform_device bast_device_dm9k = {
	366	.name = "dm9000",
	367	.id = 0,
	368	.num_resources = ARRAY_SIZE(bast_dm9k_resource),
	369	.resource = bast_dm9k_resource,
	370	.dev = {
	371	.platform_data = &bast_dm9k_platdata,
	372	}
	373	};
	374
65cc3370 BD	375	/* serial devices */
	376
	377	#define SERIAL_BASE (S3C2410_CS2 + BAST_PA_SUPERIO)
	378	#define SERIAL_FLAGS (UPF_BOOT_AUTOCONF \| UPF_IOREMAP \| UPF_SHARE_IRQ)
	379	#define SERIAL_CLK (1843200)
	380
	381	static struct plat_serial8250_port bast_sio_data[] = {
	382	[0] = {
	383	.mapbase = SERIAL_BASE + 0x2f8,
	384	.irq = IRQ_PCSERIAL1,
	385	.flags = SERIAL_FLAGS,
	386	.iotype = UPIO_MEM,
	387	.regshift = 0,
	388	.uartclk = SERIAL_CLK,
	389	},
	390	[1] = {
	391	.mapbase = SERIAL_BASE + 0x3f8,
	392	.irq = IRQ_PCSERIAL2,
	393	.flags = SERIAL_FLAGS,
	394	.iotype = UPIO_MEM,
	395	.regshift = 0,
	396	.uartclk = SERIAL_CLK,
	397	},
	398	{ }
	399	};
	400
	401	static struct platform_device bast_sio = {
	402	.name = "serial8250",
6df29deb	403	.id = PLAT8250_DEV_PLATFORM,
65cc3370 BD	404	.dev = {
	405	.platform_data = &bast_sio_data,
	406	},
	407	};
1da177e4	408
1fcf8448 BD	409	/* we have devices on the bus which cannot work much over the
	410	* standard 100KHz i2c bus frequency
	411	*/
	412
3e1b776c	413	static struct s3c2410_platform_i2c __initdata bast_i2c_info = {
1fcf8448 BD	414	.flags = 0,
1fcf8448 BD	415	.slave_addr = 0x10,
c564e6ae	416	.frequency = 100*1000,
1fcf8448 BD	417	};
1fcf8448 BD	418
5ce4b1fe BD	419	/* Asix AX88796 10/100 ethernet controller */
	420
	421	static struct ax_plat_data bast_asix_platdata = {
	422	.flags = AXFLG_MAC_FROMDEV,
	423	.wordlength = 2,
	424	.dcr_val = 0x48,
	425	.rcr_val = 0x40,
	426	};
	427
	428	static struct resource bast_asix_resource[] = {
	429	[0] = {
	430	.start = S3C2410_CS5 + BAST_PA_ASIXNET,
	431	.end = S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20) - 1,
	432	.flags = IORESOURCE_MEM,
	433	},
	434	[1] = {
	435	.start = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20),
	436	.end = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20),
	437	.flags = IORESOURCE_MEM,
	438	},
	439	[2] = {
	440	.start = IRQ_ASIX,
	441	.end = IRQ_ASIX,
	442	.flags = IORESOURCE_IRQ
	443	}
	444	};
	445
	446	static struct platform_device bast_device_asix = {
	447	.name = "ax88796",
	448	.id = 0,
	449	.num_resources = ARRAY_SIZE(bast_asix_resource),
	450	.resource = bast_asix_resource,
	451	.dev = {
	452	.platform_data = &bast_asix_platdata
	453	}
	454	};
	455
	456	/* Asix AX88796 10/100 ethernet controller parallel port */
	457
	458	static struct resource bast_asixpp_resource[] = {
	459	[0] = {
	460	.start = S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20),
	461	.end = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1b * 0x20) - 1,
	462	.flags = IORESOURCE_MEM,
	463	}
	464	};
	465
	466	static struct platform_device bast_device_axpp = {
	467	.name = "ax88796-pp",
	468	.id = 0,
	469	.num_resources = ARRAY_SIZE(bast_asixpp_resource),
	470	.resource = bast_asixpp_resource,
	471	};
	472
	473	/* LCD/VGA controller */
58c8d570	474
09fe75f6 KH	475	static struct s3c2410fb_display __initdata bast_lcd_info[] = {
09fe75f6 KH	476	{
1f411537	477	.type = S3C2410_LCDCON1_TFT,
09fe75f6 KH	478	.width = 640,
09fe75f6 KH	479	.height = 480,
5f20f69b	480
69816699	481	.pixclock = 33333,
09fe75f6 KH	482	.xres = 640,
	483	.yres = 480,
	484	.bpp = 4,
1f411537 KH	485	.left_margin = 40,
1f411537 KH	486	.right_margin = 20,
93d11f5a	487	.hsync_len = 88,
5f20f69b KH	488	.upper_margin = 30,
5f20f69b KH	489	.lower_margin = 32,
93d11f5a	490	.vsync_len = 3,
09fe75f6	491
f28ef573	492	.lcdcon5 = 0x00014b02,
58c8d570	493	},
09fe75f6	494	{
1f411537	495	.type = S3C2410_LCDCON1_TFT,
09fe75f6 KH	496	.width = 640,
	497	.height = 480,
	498
69816699	499	.pixclock = 33333,
09fe75f6 KH	500	.xres = 640,
	501	.yres = 480,
	502	.bpp = 8,
1f411537 KH	503	.left_margin = 40,
1f411537 KH	504	.right_margin = 20,
93d11f5a	505	.hsync_len = 88,
5f20f69b KH	506	.upper_margin = 30,
5f20f69b KH	507	.lower_margin = 32,
93d11f5a	508	.vsync_len = 3,
09fe75f6	509
f28ef573	510	.lcdcon5 = 0x00014b02,
09fe75f6 KH	511	},
09fe75f6 KH	512	{
1f411537	513	.type = S3C2410_LCDCON1_TFT,
09fe75f6 KH	514	.width = 640,
	515	.height = 480,
	516
69816699	517	.pixclock = 33333,
09fe75f6 KH	518	.xres = 640,
	519	.yres = 480,
	520	.bpp = 16,
1f411537 KH	521	.left_margin = 40,
1f411537 KH	522	.right_margin = 20,
93d11f5a	523	.hsync_len = 88,
5f20f69b KH	524	.upper_margin = 30,
5f20f69b KH	525	.lower_margin = 32,
93d11f5a	526	.vsync_len = 3,
09fe75f6	527
f28ef573	528	.lcdcon5 = 0x00014b02,
09fe75f6 KH	529	},
09fe75f6 KH	530	};
58c8d570	531
09fe75f6 KH	532	/* LCD/VGA controller */
	533
	534	static struct s3c2410fb_mach_info __initdata bast_fb_info = {
	535
	536	.displays = bast_lcd_info,
	537	.num_displays = ARRAY_SIZE(bast_lcd_info),
9cbae12c	538	.default_display = 1,
58c8d570 BD	539	};
58c8d570 BD	540
042cf0f2 BD	541	/* I2C devices fitted. */
	542
	543	static struct i2c_board_info bast_i2c_devs[] __initdata = {
	544	{
	545	I2C_BOARD_INFO("tlv320aic23", 0x1a),
	546	}, {
	547	I2C_BOARD_INFO("simtec-pmu", 0x6b),
	548	}, {
	549	I2C_BOARD_INFO("ch7013", 0x75),
	550	},
	551	};
b7a12d19	552
885f9ebe BD	553	static struct s3c_hwmon_pdata bast_hwmon_info = {
	554	/* LCD contrast (0-6.6V) */
	555	.in[0] = &(struct s3c_hwmon_chcfg) {
	556	.name = "lcd-contrast",
	557	.mult = 3300,
	558	.div = 512,
	559	},
	560	/* LED current feedback */
	561	.in[1] = &(struct s3c_hwmon_chcfg) {
	562	.name = "led-feedback",
	563	.mult = 3300,
	564	.div = 1024,
	565	},
	566	/* LCD feedback (0-6.6V) */
	567	.in[2] = &(struct s3c_hwmon_chcfg) {
	568	.name = "lcd-feedback",
	569	.mult = 3300,
	570	.div = 512,
	571	},
	572	/* Vcore (1.8-2.0V), Vref 3.3V */
	573	.in[3] = &(struct s3c_hwmon_chcfg) {
	574	.name = "vcore",
	575	.mult = 3300,
	576	.div = 1024,
	577	},
	578	};
	579
1da177e4	580	/* Standard BAST devices */
885f9ebe	581	// cat /sys/devices/platform/s3c24xx-adc/s3c-hwmon/in_0
1da177e4 LT	582
	583	static struct platform_device *bast_devices[] __initdata = {
	584	&s3c_device_usb,
	585	&s3c_device_lcd,
	586	&s3c_device_wdt,
3e1b776c	587	&s3c_device_i2c0,
1da177e4 LT	588	&s3c_device_rtc,
1da177e4 LT	589	&s3c_device_nand,
885f9ebe BD	590	&s3c_device_adc,
885f9ebe BD	591	&s3c_device_hwmon,
d97a666f	592	&bast_device_dm9k,
5ce4b1fe BD	593	&bast_device_asix,
5ce4b1fe BD	594	&bast_device_axpp,
65cc3370	595	&bast_sio,
1da177e4 LT	596	};
1da177e4 LT	597
2bc7509f	598	static struct clk *bast_clocks[] __initdata = {
1da177e4 LT	599	&s3c24xx_dclk0,
	600	&s3c24xx_dclk1,
	601	&s3c24xx_clkout0,
	602	&s3c24xx_clkout1,
	603	&s3c24xx_uclk,
	604	};
	605
ca0b4901 BD	606	static struct s3c_cpufreq_board __initdata bast_cpufreq = {
	607	.refresh = 7800, /* 7.8usec */
	608	.auto_io = 1,
	609	.need_io = 1,
	610	};
	611
4d3a3469 BD	612	static struct s3c24xx_audio_simtec_pdata __initdata bast_audio = {
	613	.have_mic = 1,
	614	.have_lout = 1,
	615	};
	616
5fe10ab1	617	static void __init bast_map_io(void)
1da177e4 LT	618	{
	619	/* initialise the clocks */
	620
d96a9804	621	s3c24xx_dclk0.parent = &clk_upll;
1da177e4 LT	622	s3c24xx_dclk0.rate = 1210001000;
1da177e4 LT	623
d96a9804	624	s3c24xx_dclk1.parent = &clk_upll;
1da177e4 LT	625	s3c24xx_dclk1.rate = 2410001000;
	626
	627	s3c24xx_clkout0.parent = &s3c24xx_dclk0;
	628	s3c24xx_clkout1.parent = &s3c24xx_dclk1;
	629
	630	s3c24xx_uclk.parent = &s3c24xx_clkout1;
	631
ce89c206 BD	632	s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks));
ce89c206 BD	633
1da177e4	634	s3c_device_nand.dev.platform_data = &bast_nand_info;
885f9ebe	635	s3c_device_hwmon.dev.platform_data = &bast_hwmon_info;
3e1b776c	636
1da177e4 LT	637	s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
	638	s3c24xx_init_clocks(0);
	639	s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
1da177e4 LT	640	}
1da177e4 LT	641
58c8d570 BD	642	static void __init bast_init(void)
58c8d570 BD	643	{
6ddc4b07 BD	644	sysdev_class_register(&bast_pm_sysclass);
	645	sysdev_register(&bast_pm_sysdev);
	646
a8af6de0	647	s3c_i2c0_set_platdata(&bast_i2c_info);
09fe75f6	648	s3c24xx_fb_set_platdata(&bast_fb_info);
57e5171c	649	platform_add_devices(bast_devices, ARRAY_SIZE(bast_devices));
9d529c6e	650
042cf0f2 BD	651	i2c_register_board_info(0, bast_i2c_devs,
	652	ARRAY_SIZE(bast_i2c_devs));
	653
7a05a2cb	654	usb_simtec_init();
9d529c6e	655	nor_simtec_init();
4d3a3469	656	simtec_audio_add(NULL, true, &bast_audio);
ca0b4901 BD	657
ca0b4901 BD	658	s3c_cpufreq_setboard(&bast_cpufreq);
58c8d570	659	}
1da177e4 LT	660
1da177e4 LT	661	MACHINE_START(BAST, "Simtec-BAST")
e9dea0c6	662	/* Maintainer: Ben Dooks <ben@simtec.co.uk> */
e9dea0c6 RK	663	.phys_io = S3C2410_PA_UART,
	664	.io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
	665	.boot_params = S3C2410_SDRAM_PA + 0x100,
f705b1ae BD	666	.map_io = bast_map_io,
f705b1ae BD	667	.init_irq = s3c24xx_init_irq,
58c8d570	668	.init_machine = bast_init,
1da177e4 LT	669	.timer = &s3c24xx_timer,
1da177e4 LT	670	MACHINE_END