[linux-2.6-block.git] / arch / arm / mach-omap2 / pm34xx.c

/*
 * OMAP3 Power Management Routines
 *
 * Copyright (C) 2006-2008 Nokia Corporation
 * Tony Lindgren <tony@atomide.com>
 * Jouni Hogander
 *
 * Copyright (C) 2007 Texas Instruments, Inc.
 * Rajendra Nayak <rnayak@ti.com>
 *
 * Copyright (C) 2005 Texas Instruments, Inc.
 * Richard Woodruff <r-woodruff2@ti.com>
 *
 * Based on pm.c for omap1
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/pm.h>
#include <linux/suspend.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/list.h>
#include <linux/err.h>
#include <linux/gpio.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/omap-dma.h>
#include <linux/omap-gpmc.h>
#include <linux/platform_data/gpio-omap.h>

#include <trace/events/power.h>

#include <asm/fncpy.h>
#include <asm/suspend.h>
#include <asm/system_misc.h>

#include "clockdomain.h"
#include "powerdomain.h"
#include "soc.h"
#include "common.h"
#include "cm3xxx.h"
#include "cm-regbits-34xx.h"
#include "prm-regbits-34xx.h"
#include "prm3xxx.h"
#include "pm.h"
#include "sdrc.h"
#include "sram.h"
#include "control.h"
#include "vc.h"

/* pm34xx errata defined in pm.h */
u16 pm34xx_errata;

struct power_state {
	struct powerdomain *pwrdm;
	u32 next_state;
#ifdef CONFIG_SUSPEND
	u32 saved_state;
#endif
	struct list_head node;
};

static LIST_HEAD(pwrst_list);

static int (*_omap_save_secure_sram)(u32 *addr);
void (*omap3_do_wfi_sram)(void);

static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
static struct powerdomain *core_pwrdm, *per_pwrdm;

static void omap3_core_save_context(void)
{
	omap3_ctrl_save_padconf();

	/*
	 * Force write last pad into memory, as this can fail in some
	 * cases according to errata 1.157, 1.185
	 */
	omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
		OMAP343X_CONTROL_MEM_WKUP + 0x2a0);

	/* Save the Interrupt controller context */
	omap_intc_save_context();
	/* Save the GPMC context */
	omap3_gpmc_save_context();
	/* Save the system control module context, padconf already save above*/
	omap3_control_save_context();
	omap_dma_global_context_save();
}

static void omap3_core_restore_context(void)
{
	/* Restore the control module context, padconf restored by h/w */
	omap3_control_restore_context();
	/* Restore the GPMC context */
	omap3_gpmc_restore_context();
	/* Restore the interrupt controller context */
	omap_intc_restore_context();
	omap_dma_global_context_restore();
}

/*
 * FIXME: This function should be called before entering off-mode after
 * OMAP3 secure services have been accessed. Currently it is only called
 * once during boot sequence, but this works as we are not using secure
 * services.
 */
static void omap3_save_secure_ram_context(void)
{
	u32 ret;
	int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);

	if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
		/*
		 * MPU next state must be set to POWER_ON temporarily,
		 * otherwise the WFI executed inside the ROM code
		 * will hang the system.
		 */
		pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
		ret = _omap_save_secure_sram((u32 *)(unsigned long)
				__pa(omap3_secure_ram_storage));
		pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state);
		/* Following is for error tracking, it should not happen */
		if (ret) {
			pr_err("save_secure_sram() returns %08x\n", ret);
			while (1)
				;
		}
	}
}

static irqreturn_t _prcm_int_handle_io(int irq, void *unused)
{
	int c;

	c = omap_prm_clear_mod_irqs(WKUP_MOD, 1, OMAP3430_ST_IO_MASK |
				    OMAP3430_ST_IO_CHAIN_MASK);

	return c ? IRQ_HANDLED : IRQ_NONE;
}

static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused)
{
	int c;

	/*
	 * Clear all except ST_IO and ST_IO_CHAIN for wkup module,
	 * these are handled in a separate handler to avoid acking
	 * IO events before parsing in mux code
	 */
	c = omap_prm_clear_mod_irqs(WKUP_MOD, 1, ~(OMAP3430_ST_IO_MASK |
						   OMAP3430_ST_IO_CHAIN_MASK));
	c += omap_prm_clear_mod_irqs(CORE_MOD, 1, ~0);
	c += omap_prm_clear_mod_irqs(OMAP3430_PER_MOD, 1, ~0);
	if (omap_rev() > OMAP3430_REV_ES1_0) {
		c += omap_prm_clear_mod_irqs(CORE_MOD, 3, ~0);
		c += omap_prm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, ~0);
	}

	return c ? IRQ_HANDLED : IRQ_NONE;
}

static void omap34xx_save_context(u32 *save)
{
	u32 val;

	/* Read Auxiliary Control Register */
	asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val));
	*save++ = 1;
	*save++ = val;

	/* Read L2 AUX ctrl register */
	asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
	*save++ = 1;
	*save++ = val;
}

static int omap34xx_do_sram_idle(unsigned long save_state)
{
	omap34xx_cpu_suspend(save_state);
	return 0;
}

void omap_sram_idle(void)
{
	/* Variable to tell what needs to be saved and restored
	 * in omap_sram_idle*/
	/* save_state = 0 => Nothing to save and restored */
	/* save_state = 1 => Only L1 and logic lost */
	/* save_state = 2 => Only L2 lost */
	/* save_state = 3 => L1, L2 and logic lost */
	int save_state = 0;
	int mpu_next_state = PWRDM_POWER_ON;
	int per_next_state = PWRDM_POWER_ON;
	int core_next_state = PWRDM_POWER_ON;
	int per_going_off;
	u32 sdrc_pwr = 0;

	mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
	switch (mpu_next_state) {
	case PWRDM_POWER_ON:
	case PWRDM_POWER_RET:
		/* No need to save context */
		save_state = 0;
		break;
	case PWRDM_POWER_OFF:
		save_state = 3;
		break;
	default:
		/* Invalid state */
		pr_err("Invalid mpu state in sram_idle\n");
		return;
	}

	/* NEON control */
	if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
		pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);

	/* Enable IO-PAD and IO-CHAIN wakeups */
	per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
	core_next_state = pwrdm_read_next_pwrst(core_pwrdm);

	pwrdm_pre_transition(NULL);

	/* PER */
	if (per_next_state < PWRDM_POWER_ON) {
		per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
		omap2_gpio_prepare_for_idle(per_going_off);
	}

	/* CORE */
	if (core_next_state < PWRDM_POWER_ON) {
		if (core_next_state == PWRDM_POWER_OFF) {
			omap3_core_save_context();
			omap3_cm_save_context();
		}
	}

	/* Configure PMIC signaling for I2C4 or sys_off_mode */
	omap3_vc_set_pmic_signaling(core_next_state);

	omap3_intc_prepare_idle();

	/*
	 * On EMU/HS devices ROM code restores a SRDC value
	 * from scratchpad which has automatic self refresh on timeout
	 * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.
	 * Hence store/restore the SDRC_POWER register here.
	 */
	if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
	    (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
	     omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
	    core_next_state == PWRDM_POWER_OFF)
		sdrc_pwr = sdrc_read_reg(SDRC_POWER);

	/*
	 * omap3_arm_context is the location where some ARM context
	 * get saved. The rest is placed on the stack, and restored
	 * from there before resuming.
	 */
	if (save_state)
		omap34xx_save_context(omap3_arm_context);
	if (save_state == 1 || save_state == 3)
		cpu_suspend(save_state, omap34xx_do_sram_idle);
	else
		omap34xx_do_sram_idle(save_state);

	/* Restore normal SDRC POWER settings */
	if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
	    (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
	     omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
	    core_next_state == PWRDM_POWER_OFF)
		sdrc_write_reg(sdrc_pwr, SDRC_POWER);

	/* CORE */
	if (core_next_state < PWRDM_POWER_ON &&
	    pwrdm_read_prev_pwrst(core_pwrdm) == PWRDM_POWER_OFF) {
		omap3_core_restore_context();
		omap3_cm_restore_context();
		omap3_sram_restore_context();
		omap2_sms_restore_context();
	} else {
		/*
		 * In off-mode resume path above, omap3_core_restore_context
		 * also handles the INTC autoidle restore done here so limit
		 * this to non-off mode resume paths so we don't do it twice.
		 */
		omap3_intc_resume_idle();
	}

	pwrdm_post_transition(NULL);

	/* PER */
	if (per_next_state < PWRDM_POWER_ON)
		omap2_gpio_resume_after_idle();
}

static void omap3_pm_idle(void)
{
	if (omap_irq_pending())
		return;

	trace_cpu_idle_rcuidle(1, smp_processor_id());

	omap_sram_idle();

	trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
}

#ifdef CONFIG_SUSPEND
static int omap3_pm_suspend(void)
{
	struct power_state *pwrst;
	int state, ret = 0;

	/* Read current next_pwrsts */
	list_for_each_entry(pwrst, &pwrst_list, node)
		pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
	/* Set ones wanted by suspend */
	list_for_each_entry(pwrst, &pwrst_list, node) {
		if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
			goto restore;
		if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
			goto restore;
	}

	omap3_intc_suspend();

	omap_sram_idle();

restore:
	/* Restore next_pwrsts */
	list_for_each_entry(pwrst, &pwrst_list, node) {
		state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
		if (state > pwrst->next_state) {
			pr_info("Powerdomain (%s) didn't enter target state %d\n",
				pwrst->pwrdm->name, pwrst->next_state);
			ret = -1;
		}
		omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
	}
	if (ret)
		pr_err("Could not enter target state in pm_suspend\n");
	else
		pr_info("Successfully put all powerdomains to target state\n");

	return ret;
}
#else
#define omap3_pm_suspend NULL
#endif /* CONFIG_SUSPEND */

static void __init prcm_setup_regs(void)
{
	omap3_ctrl_init();

	omap3_prm_init_pm(cpu_is_omap3630(), omap3_has_iva());
}

void omap3_pm_off_mode_enable(int enable)
{
	struct power_state *pwrst;
	u32 state;

	if (enable)
		state = PWRDM_POWER_OFF;
	else
		state = PWRDM_POWER_RET;

	list_for_each_entry(pwrst, &pwrst_list, node) {
		if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
				pwrst->pwrdm == core_pwrdm &&
				state == PWRDM_POWER_OFF) {
			pwrst->next_state = PWRDM_POWER_RET;
			pr_warn("%s: Core OFF disabled due to errata i583\n",
				__func__);
		} else {
			pwrst->next_state = state;
		}
		omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
	}
}

int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
{
	struct power_state *pwrst;

	list_for_each_entry(pwrst, &pwrst_list, node) {
		if (pwrst->pwrdm == pwrdm)
			return pwrst->next_state;
	}
	return -EINVAL;
}

int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
{
	struct power_state *pwrst;

	list_for_each_entry(pwrst, &pwrst_list, node) {
		if (pwrst->pwrdm == pwrdm) {
			pwrst->next_state = state;
			return 0;
		}
	}
	return -EINVAL;
}

static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
{
	struct power_state *pwrst;

	if (!pwrdm->pwrsts)
		return 0;

	pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
	if (!pwrst)
		return -ENOMEM;
	pwrst->pwrdm = pwrdm;
	pwrst->next_state = PWRDM_POWER_RET;
	list_add(&pwrst->node, &pwrst_list);

	if (pwrdm_has_hdwr_sar(pwrdm))
		pwrdm_enable_hdwr_sar(pwrdm);

	return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
}

/*
 * Push functions to SRAM
 *
 * The minimum set of functions is pushed to SRAM for execution:
 * - omap3_do_wfi for erratum i581 WA,
 * - save_secure_ram_context for security extensions.
 */
void omap_push_sram_idle(void)
{
	omap3_do_wfi_sram = omap_sram_push(omap3_do_wfi, omap3_do_wfi_sz);

	if (omap_type() != OMAP2_DEVICE_TYPE_GP)
		_omap_save_secure_sram = omap_sram_push(save_secure_ram_context,
				save_secure_ram_context_sz);
}

static void __init pm_errata_configure(void)
{
	if (cpu_is_omap3630()) {
		pm34xx_errata |= PM_RTA_ERRATUM_i608;
		/* Enable the l2 cache toggling in sleep logic */
		enable_omap3630_toggle_l2_on_restore();
		if (omap_rev() < OMAP3630_REV_ES1_2)
			pm34xx_errata |= (PM_SDRC_WAKEUP_ERRATUM_i583 |
					  PM_PER_MEMORIES_ERRATUM_i582);
	} else if (cpu_is_omap34xx()) {
		pm34xx_errata |= PM_PER_MEMORIES_ERRATUM_i582;
	}
}

int __init omap3_pm_init(void)
{
	struct power_state *pwrst, *tmp;
	struct clockdomain *neon_clkdm, *mpu_clkdm, *per_clkdm, *wkup_clkdm;
	int ret;

	if (!omap3_has_io_chain_ctrl())
		pr_warn("PM: no software I/O chain control; some wakeups may be lost\n");

	pm_errata_configure();

	/* XXX prcm_setup_regs needs to be before enabling hw
	 * supervised mode for powerdomains */
	prcm_setup_regs();

	ret = request_irq(omap_prcm_event_to_irq("wkup"),
		_prcm_int_handle_wakeup, IRQF_NO_SUSPEND, "pm_wkup", NULL);

	if (ret) {
		pr_err("pm: Failed to request pm_wkup irq\n");
		goto err1;
	}

	/* IO interrupt is shared with mux code */
	ret = request_irq(omap_prcm_event_to_irq("io"),
		_prcm_int_handle_io, IRQF_SHARED | IRQF_NO_SUSPEND, "pm_io",
		omap3_pm_init);
	enable_irq(omap_prcm_event_to_irq("io"));

	if (ret) {
		pr_err("pm: Failed to request pm_io irq\n");
		goto err2;
	}

	ret = pwrdm_for_each(pwrdms_setup, NULL);
	if (ret) {
		pr_err("Failed to setup powerdomains\n");
		goto err3;
	}

	(void) clkdm_for_each(omap_pm_clkdms_setup, NULL);

	mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
	if (mpu_pwrdm == NULL) {
		pr_err("Failed to get mpu_pwrdm\n");
		ret = -EINVAL;
		goto err3;
	}

	neon_pwrdm = pwrdm_lookup("neon_pwrdm");
	per_pwrdm = pwrdm_lookup("per_pwrdm");
	core_pwrdm = pwrdm_lookup("core_pwrdm");

	neon_clkdm = clkdm_lookup("neon_clkdm");
	mpu_clkdm = clkdm_lookup("mpu_clkdm");
	per_clkdm = clkdm_lookup("per_clkdm");
	wkup_clkdm = clkdm_lookup("wkup_clkdm");

	omap_common_suspend_init(omap3_pm_suspend);

	arm_pm_idle = omap3_pm_idle;
	omap3_idle_init();

	/*
	 * RTA is disabled during initialization as per erratum i608
	 * it is safer to disable RTA by the bootloader, but we would like
	 * to be doubly sure here and prevent any mishaps.
	 */
	if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
		omap3630_ctrl_disable_rta();

	/*
	 * The UART3/4 FIFO and the sidetone memory in McBSP2/3 are
	 * not correctly reset when the PER powerdomain comes back
	 * from OFF or OSWR when the CORE powerdomain is kept active.
	 * See OMAP36xx Erratum i582 "PER Domain reset issue after
	 * Domain-OFF/OSWR Wakeup".  This wakeup dependency is not a
	 * complete workaround.  The kernel must also prevent the PER
	 * powerdomain from going to OSWR/OFF while the CORE
	 * powerdomain is not going to OSWR/OFF.  And if PER last
	 * power state was off while CORE last power state was ON, the
	 * UART3/4 and McBSP2/3 SIDETONE devices need to run a
	 * self-test using their loopback tests; if that fails, those
	 * devices are unusable until the PER/CORE can complete a transition
	 * from ON to OSWR/OFF and then back to ON.
	 *
	 * XXX Technically this workaround is only needed if off-mode
	 * or OSWR is enabled.
	 */
	if (IS_PM34XX_ERRATUM(PM_PER_MEMORIES_ERRATUM_i582))
		clkdm_add_wkdep(per_clkdm, wkup_clkdm);

	clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
	if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
		omap3_secure_ram_storage =
			kmalloc(0x803F, GFP_KERNEL);
		if (!omap3_secure_ram_storage)
			pr_err("Memory allocation failed when allocating for secure sram context\n");

		local_irq_disable();

		omap_dma_global_context_save();
		omap3_save_secure_ram_context();
		omap_dma_global_context_restore();

		local_irq_enable();
	}

	omap3_save_scratchpad_contents();
	return ret;

err3:
	list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
		list_del(&pwrst->node);
		kfree(pwrst);
	}
	free_irq(omap_prcm_event_to_irq("io"), omap3_pm_init);
err2:
	free_irq(omap_prcm_event_to_irq("wkup"), NULL);
err1:
	return ret;
}
Commit	Line	Data
8bd22949 KH	1	/*
	2	* OMAP3 Power Management Routines
	3	*
	4	* Copyright (C) 2006-2008 Nokia Corporation
	5	* Tony Lindgren <tony@atomide.com>
	6	* Jouni Hogander
	7	*
2f5939c3 RN	8	* Copyright (C) 2007 Texas Instruments, Inc.
	9	* Rajendra Nayak <rnayak@ti.com>
	10	*
8bd22949 KH	11	* Copyright (C) 2005 Texas Instruments, Inc.
	12	* Richard Woodruff <r-woodruff2@ti.com>
	13	*
	14	* Based on pm.c for omap1
	15	*
	16	* This program is free software; you can redistribute it and/or modify
	17	* it under the terms of the GNU General Public License version 2 as
	18	* published by the Free Software Foundation.
	19	*/
	20
	21	#include <linux/pm.h>
	22	#include <linux/suspend.h>
	23	#include <linux/interrupt.h>
	24	#include <linux/module.h>
	25	#include <linux/list.h>
	26	#include <linux/err.h>
	27	#include <linux/gpio.h>
c40552bc	28	#include <linux/clk.h>
dccaad89	29	#include <linux/delay.h>
5a0e3ad6	30	#include <linux/slab.h>
45c3eb7d	31	#include <linux/omap-dma.h>
e639cd5b	32	#include <linux/omap-gpmc.h>
4b25408f TL	33	#include <linux/platform_data/gpio-omap.h>
4b25408f TL	34
5e7c58dc	35	#include <trace/events/power.h>
8bd22949	36
bf027ca1	37	#include <asm/fncpy.h>
2c74a0ce	38	#include <asm/suspend.h>
9f97da78	39	#include <asm/system_misc.h>
2c74a0ce	40
1540f214	41	#include "clockdomain.h"
72e06d08	42	#include "powerdomain.h"
e4c060db	43	#include "soc.h"
4e65331c	44	#include "common.h"
ff4ae5d9	45	#include "cm3xxx.h"
8bd22949 KH	46	#include "cm-regbits-34xx.h"
8bd22949 KH	47	#include "prm-regbits-34xx.h"
139563ad	48	#include "prm3xxx.h"
8bd22949	49	#include "pm.h"
13a6fe0f	50	#include "sdrc.h"
bf027ca1	51	#include "sram.h"
4814ced5	52	#include "control.h"
3b8c4ebb	53	#include "vc.h"
13a6fe0f	54
8cdfd834 NM	55	/* pm34xx errata defined in pm.h */
	56	u16 pm34xx_errata;
	57
8bd22949 KH	58	struct power_state {
	59	struct powerdomain *pwrdm;
	60	u32 next_state;
10f90ed2	61	#ifdef CONFIG_SUSPEND
8bd22949	62	u32 saved_state;
10f90ed2	63	#endif
8bd22949 KH	64	struct list_head node;
	65	};
	66
	67	static LIST_HEAD(pwrst_list);
	68
27d59a4a	69	static int (_omap_save_secure_sram)(u32 addr);
46e130d2	70	void (*omap3_do_wfi_sram)(void);
27d59a4a	71
fa3c2a4f RN	72	static struct powerdomain mpu_pwrdm, neon_pwrdm;
fa3c2a4f RN	73	static struct powerdomain core_pwrdm, per_pwrdm;
3a7ec26b	74
2f5939c3 RN	75	static void omap3_core_save_context(void)
2f5939c3 RN	76	{
596efe47	77	omap3_ctrl_save_padconf();
dccaad89 TK	78
	79	/*
	80	* Force write last pad into memory, as this can fail in some
83521291	81	* cases according to errata 1.157, 1.185
dccaad89 TK	82	*/
	83	omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
	84	OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
	85
2f5939c3 RN	86	/* Save the Interrupt controller context */
	87	omap_intc_save_context();
	88	/* Save the GPMC context */
	89	omap3_gpmc_save_context();
	90	/* Save the system control module context, padconf already save above*/
	91	omap3_control_save_context();
f2d11858	92	omap_dma_global_context_save();
2f5939c3 RN	93	}
	94
	95	static void omap3_core_restore_context(void)
	96	{
	97	/* Restore the control module context, padconf restored by h/w */
	98	omap3_control_restore_context();
	99	/* Restore the GPMC context */
	100	omap3_gpmc_restore_context();
	101	/* Restore the interrupt controller context */
	102	omap_intc_restore_context();
f2d11858	103	omap_dma_global_context_restore();
2f5939c3 RN	104	}
2f5939c3 RN	105
9d97140b TK	106	/*
	107	* FIXME: This function should be called before entering off-mode after
	108	* OMAP3 secure services have been accessed. Currently it is only called
	109	* once during boot sequence, but this works as we are not using secure
	110	* services.
	111	*/
617fcc98	112	static void omap3_save_secure_ram_context(void)
27d59a4a TK	113	{
27d59a4a TK	114	u32 ret;
617fcc98	115	int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
27d59a4a TK	116
27d59a4a TK	117	if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
27d59a4a TK	118	/*
	119	* MPU next state must be set to POWER_ON temporarily,
	120	* otherwise the WFI executed inside the ROM code
	121	* will hang the system.
	122	*/
	123	pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
6dd1e357	124	ret = _omap_save_secure_sram((u32 *)(unsigned long)
27d59a4a	125	__pa(omap3_secure_ram_storage));
617fcc98	126	pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state);
27d59a4a TK	127	/* Following is for error tracking, it should not happen */
27d59a4a TK	128	if (ret) {
98179856	129	pr_err("save_secure_sram() returns %08x\n", ret);
27d59a4a TK	130	while (1)
	131	;
	132	}
	133	}
	134	}
	135
22f51371	136	static irqreturn_t _prcm_int_handle_io(int irq, void *unused)
8cb0ac99 PW	137	{
	138	int c;
	139
9cb6d363 TK	140	c = omap_prm_clear_mod_irqs(WKUP_MOD, 1, OMAP3430_ST_IO_MASK \|
9cb6d363 TK	141	OMAP3430_ST_IO_CHAIN_MASK);
8cb0ac99	142
22f51371	143	return c ? IRQ_HANDLED : IRQ_NONE;
77da2d91	144	}
8bd22949	145
22f51371	146	static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused)
77da2d91	147	{
22f51371	148	int c;
d6290a3e	149
22f51371 TK	150	/*
	151	* Clear all except ST_IO and ST_IO_CHAIN for wkup module,
	152	* these are handled in a separate handler to avoid acking
	153	* IO events before parsing in mux code
	154	*/
9cb6d363 TK	155	c = omap_prm_clear_mod_irqs(WKUP_MOD, 1, ~(OMAP3430_ST_IO_MASK \|
	156	OMAP3430_ST_IO_CHAIN_MASK));
	157	c += omap_prm_clear_mod_irqs(CORE_MOD, 1, ~0);
	158	c += omap_prm_clear_mod_irqs(OMAP3430_PER_MOD, 1, ~0);
22f51371	159	if (omap_rev() > OMAP3430_REV_ES1_0) {
9cb6d363 TK	160	c += omap_prm_clear_mod_irqs(CORE_MOD, 3, ~0);
9cb6d363 TK	161	c += omap_prm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, ~0);
22f51371	162	}
8bd22949	163
22f51371	164	return c ? IRQ_HANDLED : IRQ_NONE;
8bd22949 KH	165	}
8bd22949 KH	166
cbe26349 RK	167	static void omap34xx_save_context(u32 *save)
	168	{
	169	u32 val;
	170
	171	/* Read Auxiliary Control Register */
	172	asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val));
	173	*save++ = 1;
	174	*save++ = val;
	175
	176	/* Read L2 AUX ctrl register */
	177	asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
	178	*save++ = 1;
	179	*save++ = val;
	180	}
	181
29cb3cd2	182	static int omap34xx_do_sram_idle(unsigned long save_state)
57f277b0	183	{
cbe26349	184	omap34xx_cpu_suspend(save_state);
29cb3cd2	185	return 0;
57f277b0 RN	186	}
57f277b0 RN	187
99e6a4d2	188	void omap_sram_idle(void)
8bd22949 KH	189	{
	190	/* Variable to tell what needs to be saved and restored
	191	* in omap_sram_idle*/
	192	/* save_state = 0 => Nothing to save and restored */
	193	/* save_state = 1 => Only L1 and logic lost */
	194	/* save_state = 2 => Only L2 lost */
	195	/* save_state = 3 => L1, L2 and logic lost */
fa3c2a4f RN	196	int save_state = 0;
	197	int mpu_next_state = PWRDM_POWER_ON;
	198	int per_next_state = PWRDM_POWER_ON;
	199	int core_next_state = PWRDM_POWER_ON;
72e06d08	200	int per_going_off;
13a6fe0f	201	u32 sdrc_pwr = 0;
8bd22949	202
8bd22949 KH	203	mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
8bd22949 KH	204	switch (mpu_next_state) {
fa3c2a4f	205	case PWRDM_POWER_ON:
8bd22949 KH	206	case PWRDM_POWER_RET:
	207	/* No need to save context */
	208	save_state = 0;
	209	break;
61255ab9 RN	210	case PWRDM_POWER_OFF:
	211	save_state = 3;
	212	break;
8bd22949 KH	213	default:
8bd22949 KH	214	/* Invalid state */
98179856	215	pr_err("Invalid mpu state in sram_idle\n");
8bd22949 KH	216	return;
8bd22949 KH	217	}
fe617af7	218
fa3c2a4f RN	219	/* NEON control */
fa3c2a4f RN	220	if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
7139178e	221	pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
fa3c2a4f	222
40742fa8	223	/* Enable IO-PAD and IO-CHAIN wakeups */
658ce97e	224	per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
ecf157d0	225	core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
40742fa8	226
e0e29fd7	227	pwrdm_pre_transition(NULL);
ff2f8e5f	228
40742fa8	229	/* PER */
658ce97e	230	if (per_next_state < PWRDM_POWER_ON) {
72e06d08	231	per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
72e06d08	232	omap2_gpio_prepare_for_idle(per_going_off);
658ce97e KH	233	}
	234
	235	/* CORE */
fa3c2a4f	236	if (core_next_state < PWRDM_POWER_ON) {
2f5939c3 RN	237	if (core_next_state == PWRDM_POWER_OFF) {
2f5939c3 RN	238	omap3_core_save_context();
f0611a5c	239	omap3_cm_save_context();
2f5939c3	240	}
fa3c2a4f	241	}
40742fa8	242
3b8c4ebb TL	243	/* Configure PMIC signaling for I2C4 or sys_off_mode */
	244	omap3_vc_set_pmic_signaling(core_next_state);
	245
f18cc2ff	246	omap3_intc_prepare_idle();
8bd22949	247
13a6fe0f	248	/*
30474544 PW	249	* On EMU/HS devices ROM code restores a SRDC value
	250	* from scratchpad which has automatic self refresh on timeout
	251	* of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.
	252	* Hence store/restore the SDRC_POWER register here.
	253	*/
	254	if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
	255	(omap_type() == OMAP2_DEVICE_TYPE_EMU \|\|
	256	omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
f265dc4c	257	core_next_state == PWRDM_POWER_OFF)
13a6fe0f	258	sdrc_pwr = sdrc_read_reg(SDRC_POWER);
13a6fe0f	259
61255ab9	260	/*
076f2cc4 RK	261	* omap3_arm_context is the location where some ARM context
	262	* get saved. The rest is placed on the stack, and restored
	263	* from there before resuming.
61255ab9	264	*/
cbe26349 RK	265	if (save_state)
cbe26349 RK	266	omap34xx_save_context(omap3_arm_context);
076f2cc4	267	if (save_state == 1 \|\| save_state == 3)
2c74a0ce	268	cpu_suspend(save_state, omap34xx_do_sram_idle);
076f2cc4 RK	269	else
076f2cc4 RK	270	omap34xx_do_sram_idle(save_state);
8bd22949	271
f265dc4c	272	/* Restore normal SDRC POWER settings */
30474544 PW	273	if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
	274	(omap_type() == OMAP2_DEVICE_TYPE_EMU \|\|
	275	omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
13a6fe0f TK	276	core_next_state == PWRDM_POWER_OFF)
	277	sdrc_write_reg(sdrc_pwr, SDRC_POWER);
	278
658ce97e	279	/* CORE */
1560d158 DG	280	if (core_next_state < PWRDM_POWER_ON &&
	281	pwrdm_read_prev_pwrst(core_pwrdm) == PWRDM_POWER_OFF) {
	282	omap3_core_restore_context();
	283	omap3_cm_restore_context();
	284	omap3_sram_restore_context();
	285	omap2_sms_restore_context();
	286	} else {
	287	/*
	288	* In off-mode resume path above, omap3_core_restore_context
	289	* also handles the INTC autoidle restore done here so limit
	290	* this to non-off mode resume paths so we don't do it twice.
	291	*/
	292	omap3_intc_resume_idle();
658ce97e KH	293	}
658ce97e KH	294
e0e29fd7 KH	295	pwrdm_post_transition(NULL);
e0e29fd7 KH	296
658ce97e	297	/* PER */
e0e29fd7	298	if (per_next_state < PWRDM_POWER_ON)
43ffcd9a	299	omap2_gpio_resume_after_idle();
8bd22949 KH	300	}
8bd22949 KH	301
8bd22949 KH	302	static void omap3_pm_idle(void)
8bd22949 KH	303	{
0bcd24b0	304	if (omap_irq_pending())
6b85638b	305	return;
8bd22949	306
6ca22700	307	trace_cpu_idle_rcuidle(1, smp_processor_id());
5e7c58dc	308
8bd22949 KH	309	omap_sram_idle();
8bd22949 KH	310
6ca22700	311	trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
8bd22949 KH	312	}
8bd22949 KH	313
10f90ed2	314	#ifdef CONFIG_SUSPEND
8bd22949 KH	315	static int omap3_pm_suspend(void)
	316	{
	317	struct power_state *pwrst;
	318	int state, ret = 0;
	319
	320	/* Read current next_pwrsts */
	321	list_for_each_entry(pwrst, &pwrst_list, node)
	322	pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
	323	/* Set ones wanted by suspend */
	324	list_for_each_entry(pwrst, &pwrst_list, node) {
eb6a2c75	325	if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
8bd22949 KH	326	goto restore;
	327	if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
	328	goto restore;
	329	}
	330
2bbe3af3 TK	331	omap3_intc_suspend();
2bbe3af3 TK	332
8bd22949 KH	333	omap_sram_idle();
	334
	335	restore:
	336	/* Restore next_pwrsts */
	337	list_for_each_entry(pwrst, &pwrst_list, node) {
8bd22949 KH	338	state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
8bd22949 KH	339	if (state > pwrst->next_state) {
7852ec05 PW	340	pr_info("Powerdomain (%s) didn't enter target state %d\n",
7852ec05 PW	341	pwrst->pwrdm->name, pwrst->next_state);
8bd22949 KH	342	ret = -1;
8bd22949 KH	343	}
eb6a2c75	344	omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
8bd22949 KH	345	}
8bd22949 KH	346	if (ret)
98179856	347	pr_err("Could not enter target state in pm_suspend\n");
8bd22949	348	else
98179856	349	pr_info("Successfully put all powerdomains to target state\n");
8bd22949 KH	350
	351	return ret;
	352	}
2e4b62dc DG	353	#else
2e4b62dc DG	354	#define omap3_pm_suspend NULL
10f90ed2	355	#endif /* CONFIG_SUSPEND */
8bd22949	356
8111b221 KH	357	static void __init prcm_setup_regs(void)
8111b221 KH	358	{
ba12c242	359	omap3_ctrl_init();
b296c811	360
c5180a2b	361	omap3_prm_init_pm(cpu_is_omap3630(), omap3_has_iva());
8bd22949 KH	362	}
8bd22949 KH	363
c40552bc KH	364	void omap3_pm_off_mode_enable(int enable)
	365	{
	366	struct power_state *pwrst;
	367	u32 state;
	368
	369	if (enable)
	370	state = PWRDM_POWER_OFF;
	371	else
	372	state = PWRDM_POWER_RET;
	373
	374	list_for_each_entry(pwrst, &pwrst_list, node) {
cc1b6028 EV	375	if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
	376	pwrst->pwrdm == core_pwrdm &&
	377	state == PWRDM_POWER_OFF) {
	378	pwrst->next_state = PWRDM_POWER_RET;
e16b41bf	379	pr_warn("%s: Core OFF disabled due to errata i583\n",
cc1b6028 EV	380	__func__);
	381	} else {
	382	pwrst->next_state = state;
	383	}
	384	omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
c40552bc KH	385	}
	386	}
	387
68d4778c TK	388	int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
	389	{
	390	struct power_state *pwrst;
	391
	392	list_for_each_entry(pwrst, &pwrst_list, node) {
	393	if (pwrst->pwrdm == pwrdm)
	394	return pwrst->next_state;
	395	}
	396	return -EINVAL;
	397	}
	398
	399	int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
	400	{
	401	struct power_state *pwrst;
	402
	403	list_for_each_entry(pwrst, &pwrst_list, node) {
	404	if (pwrst->pwrdm == pwrdm) {
	405	pwrst->next_state = state;
	406	return 0;
	407	}
	408	}
	409	return -EINVAL;
	410	}
	411
a23456e9	412	static int __init pwrdms_setup(struct powerdomain pwrdm, void unused)
8bd22949 KH	413	{
	414	struct power_state *pwrst;
	415
	416	if (!pwrdm->pwrsts)
	417	return 0;
	418
d3d381c6	419	pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
8bd22949 KH	420	if (!pwrst)
	421	return -ENOMEM;
	422	pwrst->pwrdm = pwrdm;
	423	pwrst->next_state = PWRDM_POWER_RET;
	424	list_add(&pwrst->node, &pwrst_list);
	425
	426	if (pwrdm_has_hdwr_sar(pwrdm))
	427	pwrdm_enable_hdwr_sar(pwrdm);
	428
eb6a2c75	429	return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
8bd22949 KH	430	}
8bd22949 KH	431
46e130d2 JP	432	/*
	433	* Push functions to SRAM
	434	*
	435	* The minimum set of functions is pushed to SRAM for execution:
	436	* - omap3_do_wfi for erratum i581 WA,
	437	* - save_secure_ram_context for security extensions.
	438	*/
3231fc88 RN	439	void omap_push_sram_idle(void)
3231fc88 RN	440	{
46e130d2 JP	441	omap3_do_wfi_sram = omap_sram_push(omap3_do_wfi, omap3_do_wfi_sz);
46e130d2 JP	442
27d59a4a TK	443	if (omap_type() != OMAP2_DEVICE_TYPE_GP)
	444	_omap_save_secure_sram = omap_sram_push(save_secure_ram_context,
	445	save_secure_ram_context_sz);
3231fc88 RN	446	}
3231fc88 RN	447
8cdfd834 NM	448	static void __init pm_errata_configure(void)
8cdfd834 NM	449	{
c4236d2e	450	if (cpu_is_omap3630()) {
458e999e	451	pm34xx_errata \|= PM_RTA_ERRATUM_i608;
c4236d2e PDS	452	/* Enable the l2 cache toggling in sleep logic */
c4236d2e PDS	453	enable_omap3630_toggle_l2_on_restore();
cc1b6028	454	if (omap_rev() < OMAP3630_REV_ES1_2)
856c3c5b PW	455	pm34xx_errata \|= (PM_SDRC_WAKEUP_ERRATUM_i583 \|
	456	PM_PER_MEMORIES_ERRATUM_i582);
	457	} else if (cpu_is_omap34xx()) {
	458	pm34xx_errata \|= PM_PER_MEMORIES_ERRATUM_i582;
c4236d2e	459	}
8cdfd834 NM	460	}
8cdfd834 NM	461
bbd707ac	462	int __init omap3_pm_init(void)
8bd22949 KH	463	{
8bd22949 KH	464	struct power_state pwrst, tmp;
856c3c5b	465	struct clockdomain neon_clkdm, mpu_clkdm, per_clkdm, wkup_clkdm;
8bd22949 KH	466	int ret;
8bd22949 KH	467
b02b9172	468	if (!omap3_has_io_chain_ctrl())
3d0cb73e	469	pr_warn("PM: no software I/O chain control; some wakeups may be lost\n");
b02b9172	470
8cdfd834 NM	471	pm_errata_configure();
8cdfd834 NM	472
8bd22949 KH	473	/* XXX prcm_setup_regs needs to be before enabling hw
	474	* supervised mode for powerdomains */
	475	prcm_setup_regs();
	476
22f51371 TK	477	ret = request_irq(omap_prcm_event_to_irq("wkup"),
	478	_prcm_int_handle_wakeup, IRQF_NO_SUSPEND, "pm_wkup", NULL);
	479
	480	if (ret) {
	481	pr_err("pm: Failed to request pm_wkup irq\n");
	482	goto err1;
	483	}
	484
	485	/* IO interrupt is shared with mux code */
	486	ret = request_irq(omap_prcm_event_to_irq("io"),
	487	_prcm_int_handle_io, IRQF_SHARED \| IRQF_NO_SUSPEND, "pm_io",
	488	omap3_pm_init);
99b59df0	489	enable_irq(omap_prcm_event_to_irq("io"));
22f51371	490
8bd22949	491	if (ret) {
22f51371	492	pr_err("pm: Failed to request pm_io irq\n");
ce229c5d	493	goto err2;
8bd22949 KH	494	}
8bd22949 KH	495
a23456e9	496	ret = pwrdm_for_each(pwrdms_setup, NULL);
8bd22949	497	if (ret) {
98179856	498	pr_err("Failed to setup powerdomains\n");
ce229c5d	499	goto err3;
8bd22949 KH	500	}
8bd22949 KH	501
92206fd2	502	(void) clkdm_for_each(omap_pm_clkdms_setup, NULL);
8bd22949 KH	503
	504	mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
	505	if (mpu_pwrdm == NULL) {
98179856	506	pr_err("Failed to get mpu_pwrdm\n");
ce229c5d MG	507	ret = -EINVAL;
ce229c5d MG	508	goto err3;
8bd22949 KH	509	}
8bd22949 KH	510
fa3c2a4f RN	511	neon_pwrdm = pwrdm_lookup("neon_pwrdm");
	512	per_pwrdm = pwrdm_lookup("per_pwrdm");
	513	core_pwrdm = pwrdm_lookup("core_pwrdm");
	514
55ed9694 PW	515	neon_clkdm = clkdm_lookup("neon_clkdm");
55ed9694 PW	516	mpu_clkdm = clkdm_lookup("mpu_clkdm");
856c3c5b PW	517	per_clkdm = clkdm_lookup("per_clkdm");
856c3c5b PW	518	wkup_clkdm = clkdm_lookup("wkup_clkdm");
55ed9694	519
2e4b62dc	520	omap_common_suspend_init(omap3_pm_suspend);
8bd22949	521
0bcd24b0	522	arm_pm_idle = omap3_pm_idle;
0343371e	523	omap3_idle_init();
8bd22949	524
458e999e NM	525	/*
	526	* RTA is disabled during initialization as per erratum i608
	527	* it is safer to disable RTA by the bootloader, but we would like
	528	* to be doubly sure here and prevent any mishaps.
	529	*/
	530	if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
	531	omap3630_ctrl_disable_rta();
	532
856c3c5b PW	533	/*
	534	* The UART3/4 FIFO and the sidetone memory in McBSP2/3 are
	535	* not correctly reset when the PER powerdomain comes back
	536	* from OFF or OSWR when the CORE powerdomain is kept active.
	537	* See OMAP36xx Erratum i582 "PER Domain reset issue after
	538	* Domain-OFF/OSWR Wakeup". This wakeup dependency is not a
	539	* complete workaround. The kernel must also prevent the PER
	540	* powerdomain from going to OSWR/OFF while the CORE
	541	* powerdomain is not going to OSWR/OFF. And if PER last
	542	* power state was off while CORE last power state was ON, the
	543	* UART3/4 and McBSP2/3 SIDETONE devices need to run a
	544	* self-test using their loopback tests; if that fails, those
	545	* devices are unusable until the PER/CORE can complete a transition
	546	* from ON to OSWR/OFF and then back to ON.
	547	*
	548	* XXX Technically this workaround is only needed if off-mode
	549	* or OSWR is enabled.
	550	*/
	551	if (IS_PM34XX_ERRATUM(PM_PER_MEMORIES_ERRATUM_i582))
	552	clkdm_add_wkdep(per_clkdm, wkup_clkdm);
	553
55ed9694	554	clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
27d59a4a TK	555	if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
	556	omap3_secure_ram_storage =
	557	kmalloc(0x803F, GFP_KERNEL);
	558	if (!omap3_secure_ram_storage)
7852ec05	559	pr_err("Memory allocation failed when allocating for secure sram context\n");
9d97140b TK	560
9d97140b TK	561	local_irq_disable();
9d97140b TK	562
9d97140b TK	563	omap_dma_global_context_save();
617fcc98	564	omap3_save_secure_ram_context();
9d97140b TK	565	omap_dma_global_context_restore();
	566
	567	local_irq_enable();
27d59a4a	568	}
27d59a4a	569
9d97140b	570	omap3_save_scratchpad_contents();
8bd22949	571	return ret;
ce229c5d MG	572
ce229c5d MG	573	err3:
8bd22949 KH	574	list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
	575	list_del(&pwrst->node);
	576	kfree(pwrst);
	577	}
ce229c5d MG	578	free_irq(omap_prcm_event_to_irq("io"), omap3_pm_init);
	579	err2:
	580	free_irq(omap_prcm_event_to_irq("wkup"), NULL);
	581	err1:
8bd22949 KH	582	return ret;
8bd22949 KH	583	}