[linux-2.6-block.git] / arch / arm / mach-omap2 / iommu2.c

/*
 * omap iommu: omap2/3 architecture specific functions
 *
 * Copyright (C) 2008-2009 Nokia Corporation
 *
 * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>,
 *		Paul Mundt and Toshihiro Kobayashi
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/err.h>
#include <linux/device.h>
#include <linux/jiffies.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/stringify.h>

#include <plat/iommu.h>

/*
 * omap2 architecture specific register bit definitions
 */
#define IOMMU_ARCH_VERSION	0x00000011

/* SYSCONF */
#define MMU_SYS_IDLE_SHIFT	3
#define MMU_SYS_IDLE_FORCE	(0 << MMU_SYS_IDLE_SHIFT)
#define MMU_SYS_IDLE_NONE	(1 << MMU_SYS_IDLE_SHIFT)
#define MMU_SYS_IDLE_SMART	(2 << MMU_SYS_IDLE_SHIFT)
#define MMU_SYS_IDLE_MASK	(3 << MMU_SYS_IDLE_SHIFT)

#define MMU_SYS_SOFTRESET	(1 << 1)
#define MMU_SYS_AUTOIDLE	1

/* SYSSTATUS */
#define MMU_SYS_RESETDONE	1

/* IRQSTATUS & IRQENABLE */
#define MMU_IRQ_MULTIHITFAULT	(1 << 4)
#define MMU_IRQ_TABLEWALKFAULT	(1 << 3)
#define MMU_IRQ_EMUMISS		(1 << 2)
#define MMU_IRQ_TRANSLATIONFAULT	(1 << 1)
#define MMU_IRQ_TLBMISS		(1 << 0)
#define MMU_IRQ_MASK	\
	(MMU_IRQ_MULTIHITFAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_EMUMISS | \
	 MMU_IRQ_TRANSLATIONFAULT)

/* MMU_CNTL */
#define MMU_CNTL_SHIFT		1
#define MMU_CNTL_MASK		(7 << MMU_CNTL_SHIFT)
#define MMU_CNTL_EML_TLB	(1 << 3)
#define MMU_CNTL_TWL_EN		(1 << 2)
#define MMU_CNTL_MMU_EN		(1 << 1)

#define get_cam_va_mask(pgsz)				\
	(((pgsz) == MMU_CAM_PGSZ_16M) ? 0xff000000 :	\
	 ((pgsz) == MMU_CAM_PGSZ_1M)  ? 0xfff00000 :	\
	 ((pgsz) == MMU_CAM_PGSZ_64K) ? 0xffff0000 :	\
	 ((pgsz) == MMU_CAM_PGSZ_4K)  ? 0xfffff000 : 0)

static int omap2_iommu_enable(struct iommu *obj)
{
	u32 l, pa;
	unsigned long timeout;

	if (!obj->iopgd || !IS_ALIGNED((u32)obj->iopgd,  SZ_16K))
		return -EINVAL;

	pa = virt_to_phys(obj->iopgd);
	if (!IS_ALIGNED(pa, SZ_16K))
		return -EINVAL;

	iommu_write_reg(obj, MMU_SYS_SOFTRESET, MMU_SYSCONFIG);

	timeout = jiffies + msecs_to_jiffies(20);
	do {
		l = iommu_read_reg(obj, MMU_SYSSTATUS);
		if (l & MMU_SYS_RESETDONE)
			break;
	} while (!time_after(jiffies, timeout));

	if (!(l & MMU_SYS_RESETDONE)) {
		dev_err(obj->dev, "can't take mmu out of reset\n");
		return -ENODEV;
	}

	l = iommu_read_reg(obj, MMU_REVISION);
	dev_info(obj->dev, "%s: version %d.%d\n", obj->name,
		 (l >> 4) & 0xf, l & 0xf);

	l = iommu_read_reg(obj, MMU_SYSCONFIG);
	l &= ~MMU_SYS_IDLE_MASK;
	l |= (MMU_SYS_IDLE_SMART | MMU_SYS_AUTOIDLE);
	iommu_write_reg(obj, l, MMU_SYSCONFIG);

	iommu_write_reg(obj, MMU_IRQ_MASK, MMU_IRQENABLE);
	iommu_write_reg(obj, pa, MMU_TTB);

	l = iommu_read_reg(obj, MMU_CNTL);
	l &= ~MMU_CNTL_MASK;
	l |= (MMU_CNTL_MMU_EN | MMU_CNTL_TWL_EN);
	iommu_write_reg(obj, l, MMU_CNTL);

	return 0;
}

static void omap2_iommu_disable(struct iommu *obj)
{
	u32 l = iommu_read_reg(obj, MMU_CNTL);

	l &= ~MMU_CNTL_MASK;
	iommu_write_reg(obj, l, MMU_CNTL);
	iommu_write_reg(obj, MMU_SYS_IDLE_FORCE, MMU_SYSCONFIG);

	dev_dbg(obj->dev, "%s is shutting down\n", obj->name);
}

static u32 omap2_iommu_fault_isr(struct iommu *obj, u32 *ra)
{
	int i;
	u32 stat, da;
	const char *err_msg[] =	{
		"tlb miss",
		"translation fault",
		"emulation miss",
		"table walk fault",
		"multi hit fault",
	};

	stat = iommu_read_reg(obj, MMU_IRQSTATUS);
	stat &= MMU_IRQ_MASK;
	if (!stat)
		return 0;

	da = iommu_read_reg(obj, MMU_FAULT_AD);
	*ra = da;

	dev_err(obj->dev, "%s:\tda:%08x ", __func__, da);

	for (i = 0; i < ARRAY_SIZE(err_msg); i++) {
		if (stat & (1 << i))
			printk("%s ", err_msg[i]);
	}
	printk("\n");

	iommu_write_reg(obj, stat, MMU_IRQSTATUS);
	return stat;
}

static void omap2_tlb_read_cr(struct iommu *obj, struct cr_regs *cr)
{
	cr->cam = iommu_read_reg(obj, MMU_READ_CAM);
	cr->ram = iommu_read_reg(obj, MMU_READ_RAM);
}

static void omap2_tlb_load_cr(struct iommu *obj, struct cr_regs *cr)
{
	iommu_write_reg(obj, cr->cam | MMU_CAM_V, MMU_CAM);
	iommu_write_reg(obj, cr->ram, MMU_RAM);
}

static u32 omap2_cr_to_virt(struct cr_regs *cr)
{
	u32 page_size = cr->cam & MMU_CAM_PGSZ_MASK;
	u32 mask = get_cam_va_mask(cr->cam & page_size);

	return cr->cam & mask;
}

static struct cr_regs *omap2_alloc_cr(struct iommu *obj, struct iotlb_entry *e)
{
	struct cr_regs *cr;

	if (e->da & ~(get_cam_va_mask(e->pgsz))) {
		dev_err(obj->dev, "%s:\twrong alignment: %08x\n", __func__,
			e->da);
		return ERR_PTR(-EINVAL);
	}

	cr = kmalloc(sizeof(*cr), GFP_KERNEL);
	if (!cr)
		return ERR_PTR(-ENOMEM);

	cr->cam = (e->da & MMU_CAM_VATAG_MASK) | e->prsvd | e->pgsz;
	cr->ram = e->pa | e->endian | e->elsz | e->mixed;

	return cr;
}

static inline int omap2_cr_valid(struct cr_regs *cr)
{
	return cr->cam & MMU_CAM_V;
}

static u32 omap2_get_pte_attr(struct iotlb_entry *e)
{
	u32 attr;

	attr = e->mixed << 5;
	attr |= e->endian;
	attr |= e->elsz >> 3;
	attr <<= ((e->pgsz & MMU_CAM_PGSZ_4K) ? 0 : 6);

	return attr;
}

static ssize_t omap2_dump_cr(struct iommu *obj, struct cr_regs *cr, char *buf)
{
	char *p = buf;

	/* FIXME: Need more detail analysis of cam/ram */
	p += sprintf(p, "%08x %08x\n", cr->cam, cr->ram);

	return p - buf;
}

#define pr_reg(name)							\
	do {								\
		ssize_t bytes;						\
		const char *str = "%20s: %08x\n";			\
		const int maxcol = 32;					\
		bytes = snprintf(p, maxcol, str, __stringify(name),	\
				 iommu_read_reg(obj, MMU_##name));	\
		p += bytes;						\
		len -= bytes;						\
		if (len < maxcol)					\
			goto out;					\
	} while (0)

static ssize_t omap2_iommu_dump_ctx(struct iommu *obj, char *buf, ssize_t len)
{
	char *p = buf;

	pr_reg(REVISION);
	pr_reg(SYSCONFIG);
	pr_reg(SYSSTATUS);
	pr_reg(IRQSTATUS);
	pr_reg(IRQENABLE);
	pr_reg(WALKING_ST);
	pr_reg(CNTL);
	pr_reg(FAULT_AD);
	pr_reg(TTB);
	pr_reg(LOCK);
	pr_reg(LD_TLB);
	pr_reg(CAM);
	pr_reg(RAM);
	pr_reg(GFLUSH);
	pr_reg(FLUSH_ENTRY);
	pr_reg(READ_CAM);
	pr_reg(READ_RAM);
	pr_reg(EMU_FAULT_AD);
out:
	return p - buf;
}

static void omap2_iommu_save_ctx(struct iommu *obj)
{
	int i;
	u32 *p = obj->ctx;

	for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) {
		p[i] = iommu_read_reg(obj, i * sizeof(u32));
		dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]);
	}

	BUG_ON(p[0] != IOMMU_ARCH_VERSION);
}

static void omap2_iommu_restore_ctx(struct iommu *obj)
{
	int i;
	u32 *p = obj->ctx;

	for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) {
		iommu_write_reg(obj, p[i], i * sizeof(u32));
		dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]);
	}

	BUG_ON(p[0] != IOMMU_ARCH_VERSION);
}

static void omap2_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e)
{
	e->da		= cr->cam & MMU_CAM_VATAG_MASK;
	e->pa		= cr->ram & MMU_RAM_PADDR_MASK;
	e->valid	= cr->cam & MMU_CAM_V;
	e->pgsz		= cr->cam & MMU_CAM_PGSZ_MASK;
	e->endian	= cr->ram & MMU_RAM_ENDIAN_MASK;
	e->elsz		= cr->ram & MMU_RAM_ELSZ_MASK;
	e->mixed	= cr->ram & MMU_RAM_MIXED;
}

static const struct iommu_functions omap2_iommu_ops = {
	.version	= IOMMU_ARCH_VERSION,

	.enable		= omap2_iommu_enable,
	.disable	= omap2_iommu_disable,
	.fault_isr	= omap2_iommu_fault_isr,

	.tlb_read_cr	= omap2_tlb_read_cr,
	.tlb_load_cr	= omap2_tlb_load_cr,

	.cr_to_e	= omap2_cr_to_e,
	.cr_to_virt	= omap2_cr_to_virt,
	.alloc_cr	= omap2_alloc_cr,
	.cr_valid	= omap2_cr_valid,
	.dump_cr	= omap2_dump_cr,

	.get_pte_attr	= omap2_get_pte_attr,

	.save_ctx	= omap2_iommu_save_ctx,
	.restore_ctx	= omap2_iommu_restore_ctx,
	.dump_ctx	= omap2_iommu_dump_ctx,
};

static int __init omap2_iommu_init(void)
{
	return install_iommu_arch(&omap2_iommu_ops);
}
module_init(omap2_iommu_init);

static void __exit omap2_iommu_exit(void)
{
	uninstall_iommu_arch(&omap2_iommu_ops);
}
module_exit(omap2_iommu_exit);

MODULE_AUTHOR("Hiroshi DOYU, Paul Mundt and Toshihiro Kobayashi");
MODULE_DESCRIPTION("omap iommu: omap2/3 architecture specific functions");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
2bcb5733 HD	1	/*
	2	* omap iommu: omap2/3 architecture specific functions
	3	*
	4	* Copyright (C) 2008-2009 Nokia Corporation
	5	*
	6	* Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>,
	7	* Paul Mundt and Toshihiro Kobayashi
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*/
	13
	14	#include <linux/err.h>
	15	#include <linux/device.h>
	16	#include <linux/jiffies.h>
	17	#include <linux/module.h>
5a0e3ad6	18	#include <linux/slab.h>
2bcb5733 HD	19	#include <linux/stringify.h>
2bcb5733 HD	20
ce491cf8	21	#include <plat/iommu.h>
2bcb5733 HD	22
	23	/*
	24	* omap2 architecture specific register bit definitions
	25	*/
	26	#define IOMMU_ARCH_VERSION 0x00000011
	27
	28	/* SYSCONF */
	29	#define MMU_SYS_IDLE_SHIFT 3
	30	#define MMU_SYS_IDLE_FORCE (0 << MMU_SYS_IDLE_SHIFT)
	31	#define MMU_SYS_IDLE_NONE (1 << MMU_SYS_IDLE_SHIFT)
	32	#define MMU_SYS_IDLE_SMART (2 << MMU_SYS_IDLE_SHIFT)
	33	#define MMU_SYS_IDLE_MASK (3 << MMU_SYS_IDLE_SHIFT)
	34
	35	#define MMU_SYS_SOFTRESET (1 << 1)
	36	#define MMU_SYS_AUTOIDLE 1
	37
	38	/* SYSSTATUS */
	39	#define MMU_SYS_RESETDONE 1
	40
	41	/* IRQSTATUS & IRQENABLE */
	42	#define MMU_IRQ_MULTIHITFAULT (1 << 4)
	43	#define MMU_IRQ_TABLEWALKFAULT (1 << 3)
	44	#define MMU_IRQ_EMUMISS (1 << 2)
	45	#define MMU_IRQ_TRANSLATIONFAULT (1 << 1)
	46	#define MMU_IRQ_TLBMISS (1 << 0)
	47	#define MMU_IRQ_MASK \
	48	(MMU_IRQ_MULTIHITFAULT \| MMU_IRQ_TABLEWALKFAULT \| MMU_IRQ_EMUMISS \| \
	49	MMU_IRQ_TRANSLATIONFAULT)
	50
	51	/* MMU_CNTL */
	52	#define MMU_CNTL_SHIFT 1
	53	#define MMU_CNTL_MASK (7 << MMU_CNTL_SHIFT)
	54	#define MMU_CNTL_EML_TLB (1 << 3)
	55	#define MMU_CNTL_TWL_EN (1 << 2)
	56	#define MMU_CNTL_MMU_EN (1 << 1)
	57
	58	#define get_cam_va_mask(pgsz) \
	59	(((pgsz) == MMU_CAM_PGSZ_16M) ? 0xff000000 : \
	60	((pgsz) == MMU_CAM_PGSZ_1M) ? 0xfff00000 : \
	61	((pgsz) == MMU_CAM_PGSZ_64K) ? 0xffff0000 : \
	62	((pgsz) == MMU_CAM_PGSZ_4K) ? 0xfffff000 : 0)
	63
	64	static int omap2_iommu_enable(struct iommu *obj)
	65	{
	66	u32 l, pa;
	67	unsigned long timeout;
	68
	69	if (!obj->iopgd \|\| !IS_ALIGNED((u32)obj->iopgd, SZ_16K))
	70	return -EINVAL;
	71
	72	pa = virt_to_phys(obj->iopgd);
	73	if (!IS_ALIGNED(pa, SZ_16K))
	74	return -EINVAL;
	75
	76	iommu_write_reg(obj, MMU_SYS_SOFTRESET, MMU_SYSCONFIG);
	77
	78	timeout = jiffies + msecs_to_jiffies(20);
	79	do {
	80	l = iommu_read_reg(obj, MMU_SYSSTATUS);
	81	if (l & MMU_SYS_RESETDONE)
	82	break;
055c49d2	83	} while (!time_after(jiffies, timeout));
2bcb5733 HD	84
	85	if (!(l & MMU_SYS_RESETDONE)) {
	86	dev_err(obj->dev, "can't take mmu out of reset\n");
	87	return -ENODEV;
	88	}
	89
	90	l = iommu_read_reg(obj, MMU_REVISION);
	91	dev_info(obj->dev, "%s: version %d.%d\n", obj->name,
	92	(l >> 4) & 0xf, l & 0xf);
	93
	94	l = iommu_read_reg(obj, MMU_SYSCONFIG);
	95	l &= ~MMU_SYS_IDLE_MASK;
	96	l \|= (MMU_SYS_IDLE_SMART \| MMU_SYS_AUTOIDLE);
	97	iommu_write_reg(obj, l, MMU_SYSCONFIG);
	98
	99	iommu_write_reg(obj, MMU_IRQ_MASK, MMU_IRQENABLE);
	100	iommu_write_reg(obj, pa, MMU_TTB);
	101
	102	l = iommu_read_reg(obj, MMU_CNTL);
	103	l &= ~MMU_CNTL_MASK;
	104	l \|= (MMU_CNTL_MMU_EN \| MMU_CNTL_TWL_EN);
	105	iommu_write_reg(obj, l, MMU_CNTL);
	106
	107	return 0;
	108	}
	109
	110	static void omap2_iommu_disable(struct iommu *obj)
	111	{
	112	u32 l = iommu_read_reg(obj, MMU_CNTL);
	113
	114	l &= ~MMU_CNTL_MASK;
	115	iommu_write_reg(obj, l, MMU_CNTL);
	116	iommu_write_reg(obj, MMU_SYS_IDLE_FORCE, MMU_SYSCONFIG);
	117
	118	dev_dbg(obj->dev, "%s is shutting down\n", obj->name);
	119	}
	120
	121	static u32 omap2_iommu_fault_isr(struct iommu obj, u32 ra)
	122	{
	123	int i;
	124	u32 stat, da;
	125	const char *err_msg[] = {
	126	"tlb miss",
	127	"translation fault",
	128	"emulation miss",
	129	"table walk fault",
	130	"multi hit fault",
	131	};
	132
	133	stat = iommu_read_reg(obj, MMU_IRQSTATUS);
	134	stat &= MMU_IRQ_MASK;
	135	if (!stat)
	136	return 0;
	137
	138	da = iommu_read_reg(obj, MMU_FAULT_AD);
	139	*ra = da;
	140
	141	dev_err(obj->dev, "%s:\tda:%08x ", __func__, da);
	142
	143	for (i = 0; i < ARRAY_SIZE(err_msg); i++) {
	144	if (stat & (1 << i))
	145	printk("%s ", err_msg[i]);
	146	}
	147	printk("\n");
148
149	iommu_write_reg(obj, stat, MMU_IRQSTATUS);
150	return stat;
151	}
152
153	static void omap2_tlb_read_cr(struct iommu obj, struct cr_regs cr)
154	{
155	cr->cam = iommu_read_reg(obj, MMU_READ_CAM);
156	cr->ram = iommu_read_reg(obj, MMU_READ_RAM);
157	}
158
159	static void omap2_tlb_load_cr(struct iommu obj, struct cr_regs cr)
160	{
161	iommu_write_reg(obj, cr->cam \| MMU_CAM_V, MMU_CAM);
162	iommu_write_reg(obj, cr->ram, MMU_RAM);
163	}
164
165	static u32 omap2_cr_to_virt(struct cr_regs *cr)
166	{
167	u32 page_size = cr->cam & MMU_CAM_PGSZ_MASK;
168	u32 mask = get_cam_va_mask(cr->cam & page_size);
169
170	return cr->cam & mask;
171	}
172
173	static struct cr_regs omap2_alloc_cr(struct iommu obj, struct iotlb_entry *e)
174	{
175	struct cr_regs *cr;
176
177	if (e->da & ~(get_cam_va_mask(e->pgsz))) {
178	dev_err(obj->dev, "%s:\twrong alignment: %08x\n", __func__,
179	e->da);
180	return ERR_PTR(-EINVAL);
181	}
182
183	cr = kmalloc(sizeof(*cr), GFP_KERNEL);
184	if (!cr)
185	return ERR_PTR(-ENOMEM);
186
187	cr->cam = (e->da & MMU_CAM_VATAG_MASK) \| e->prsvd \| e->pgsz;
188	cr->ram = e->pa \| e->endian \| e->elsz \| e->mixed;
189
190	return cr;
191	}
192
193	static inline int omap2_cr_valid(struct cr_regs *cr)
194	{
195	return cr->cam & MMU_CAM_V;
196	}
197
198	static u32 omap2_get_pte_attr(struct iotlb_entry *e)
199	{
200	u32 attr;
201
202	attr = e->mixed << 5;
203	attr \|= e->endian;
204	attr \|= e->elsz >> 3;
205	attr <<= ((e->pgsz & MMU_CAM_PGSZ_4K) ? 0 : 6);
206
207	return attr;
208	}
209
210	static ssize_t omap2_dump_cr(struct iommu obj, struct cr_regs cr, char *buf)
211	{
212	char *p = buf;
213
214	/* FIXME: Need more detail analysis of cam/ram */
215	p += sprintf(p, "%08x %08x\n", cr->cam, cr->ram);
216
217	return p - buf;
218	}
219
220	#define pr_reg(name) \
14e0e679 HD	221	do { \
	222	ssize_t bytes; \
	223	const char *str = "%20s: %08x\n"; \
	224	const int maxcol = 32; \
	225	bytes = snprintf(p, maxcol, str, __stringify(name), \
	226	iommu_read_reg(obj, MMU_##name)); \
	227	p += bytes; \
	228	len -= bytes; \
	229	if (len < maxcol) \
	230	goto out; \
	231	} while (0)
	232
	233	static ssize_t omap2_iommu_dump_ctx(struct iommu obj, char buf, ssize_t len)
2bcb5733 HD	234	{
	235	char *p = buf;
	236
	237	pr_reg(REVISION);
	238	pr_reg(SYSCONFIG);
	239	pr_reg(SYSSTATUS);
	240	pr_reg(IRQSTATUS);
	241	pr_reg(IRQENABLE);
	242	pr_reg(WALKING_ST);
	243	pr_reg(CNTL);
	244	pr_reg(FAULT_AD);
	245	pr_reg(TTB);
	246	pr_reg(LOCK);
	247	pr_reg(LD_TLB);
	248	pr_reg(CAM);
	249	pr_reg(RAM);
	250	pr_reg(GFLUSH);
	251	pr_reg(FLUSH_ENTRY);
	252	pr_reg(READ_CAM);
	253	pr_reg(READ_RAM);
	254	pr_reg(EMU_FAULT_AD);
14e0e679	255	out:
2bcb5733 HD	256	return p - buf;
	257	}
	258
	259	static void omap2_iommu_save_ctx(struct iommu *obj)
	260	{
	261	int i;
	262	u32 *p = obj->ctx;
	263
	264	for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) {
	265	p[i] = iommu_read_reg(obj, i * sizeof(u32));
	266	dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]);
	267	}
	268
	269	BUG_ON(p[0] != IOMMU_ARCH_VERSION);
	270	}
	271
	272	static void omap2_iommu_restore_ctx(struct iommu *obj)
	273	{
	274	int i;
	275	u32 *p = obj->ctx;
	276
	277	for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) {
	278	iommu_write_reg(obj, p[i], i * sizeof(u32));
	279	dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]);
	280	}
	281
	282	BUG_ON(p[0] != IOMMU_ARCH_VERSION);
	283	}
	284
	285	static void omap2_cr_to_e(struct cr_regs cr, struct iotlb_entry e)
	286	{
	287	e->da = cr->cam & MMU_CAM_VATAG_MASK;
	288	e->pa = cr->ram & MMU_RAM_PADDR_MASK;
	289	e->valid = cr->cam & MMU_CAM_V;
	290	e->pgsz = cr->cam & MMU_CAM_PGSZ_MASK;
	291	e->endian = cr->ram & MMU_RAM_ENDIAN_MASK;
	292	e->elsz = cr->ram & MMU_RAM_ELSZ_MASK;
	293	e->mixed = cr->ram & MMU_RAM_MIXED;
	294	}
	295
	296	static const struct iommu_functions omap2_iommu_ops = {
	297	.version = IOMMU_ARCH_VERSION,
	298
	299	.enable = omap2_iommu_enable,
	300	.disable = omap2_iommu_disable,
	301	.fault_isr = omap2_iommu_fault_isr,
	302
	303	.tlb_read_cr = omap2_tlb_read_cr,
	304	.tlb_load_cr = omap2_tlb_load_cr,
	305
	306	.cr_to_e = omap2_cr_to_e,
	307	.cr_to_virt = omap2_cr_to_virt,
	308	.alloc_cr = omap2_alloc_cr,
	309	.cr_valid = omap2_cr_valid,
	310	.dump_cr = omap2_dump_cr,
	311
	312	.get_pte_attr = omap2_get_pte_attr,
	313
	314	.save_ctx = omap2_iommu_save_ctx,
	315	.restore_ctx = omap2_iommu_restore_ctx,
	316	.dump_ctx = omap2_iommu_dump_ctx,
	317	};
	318
	319	static int __init omap2_iommu_init(void)
320	{
321	return install_iommu_arch(&omap2_iommu_ops);
322	}
323	module_init(omap2_iommu_init);
324
325	static void __exit omap2_iommu_exit(void)
326	{
327	uninstall_iommu_arch(&omap2_iommu_ops);
328	}
329	module_exit(omap2_iommu_exit);
330
331	MODULE_AUTHOR("Hiroshi DOYU, Paul Mundt and Toshihiro Kobayashi");
332	MODULE_DESCRIPTION("omap iommu: omap2/3 architecture specific functions");
333	MODULE_LICENSE("GPL v2");