[linux-2.6-block.git] / arch / arm / mach-omap2 / clock34xx.c

/*
 * OMAP3-specific clock framework functions
 *
 * Copyright (C) 2007-2008 Texas Instruments, Inc.
 * Copyright (C) 2007-2009 Nokia Corporation
 *
 * Written by Paul Walmsley
 * Testing and integration fixes by Jouni Högander
 *
 * Parts of this code are based on code written by
 * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#undef DEBUG

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/limits.h>
#include <linux/bitops.h>

#include <plat/cpu.h>
#include <plat/clock.h>
#include <plat/sram.h>
#include <plat/sdrc.h>
#include <asm/div64.h>
#include <asm/clkdev.h>

#include <plat/sdrc.h>
#include "clock.h"
#include "clock34xx.h"
#include "sdrc.h"
#include "prm.h"
#include "prm-regbits-34xx.h"
#include "cm.h"
#include "cm-regbits-34xx.h"

#define CYCLES_PER_MHZ			1000000

/*
 * DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks
 * that are sourced by DPLL5, and both of these require this clock
 * to be at 120 MHz for proper operation.
 */
#define DPLL5_FREQ_FOR_USBHOST		120000000

/* needed by omap3_core_dpll_m2_set_rate() */
struct clk *sdrc_ick_p, *arm_fck_p;

/**
 * omap3430es2_clk_ssi_find_idlest - return CM_IDLEST info for SSI
 * @clk: struct clk * being enabled
 * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
 * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
 *
 * The OMAP3430ES2 SSI target CM_IDLEST bit is at a different shift
 * from the CM_{I,F}CLKEN bit.  Pass back the correct info via
 * @idlest_reg and @idlest_bit.  No return value.
 */
static void omap3430es2_clk_ssi_find_idlest(struct clk *clk,
					    void __iomem **idlest_reg,
					    u8 *idlest_bit)
{
	u32 r;

	r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
	*idlest_reg = (__force void __iomem *)r;
	*idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT;
}

const struct clkops clkops_omap3430es2_ssi_wait = {
	.enable		= omap2_dflt_clk_enable,
	.disable	= omap2_dflt_clk_disable,
	.find_idlest	= omap3430es2_clk_ssi_find_idlest,
	.find_companion = omap2_clk_dflt_find_companion,
};

/**
 * omap3430es2_clk_dss_usbhost_find_idlest - CM_IDLEST info for DSS, USBHOST
 * @clk: struct clk * being enabled
 * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
 * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
 *
 * Some OMAP modules on OMAP3 ES2+ chips have both initiator and
 * target IDLEST bits.  For our purposes, we are concerned with the
 * target IDLEST bits, which exist at a different bit position than
 * the *CLKEN bit position for these modules (DSS and USBHOST) (The
 * default find_idlest code assumes that they are at the same
 * position.)  No return value.
 */
static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk,
						    void __iomem **idlest_reg,
						    u8 *idlest_bit)
{
	u32 r;

	r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
	*idlest_reg = (__force void __iomem *)r;
	/* USBHOST_IDLE has same shift */
	*idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT;
}

const struct clkops clkops_omap3430es2_dss_usbhost_wait = {
	.enable		= omap2_dflt_clk_enable,
	.disable	= omap2_dflt_clk_disable,
	.find_idlest	= omap3430es2_clk_dss_usbhost_find_idlest,
	.find_companion = omap2_clk_dflt_find_companion,
};

/**
 * omap3430es2_clk_hsotgusb_find_idlest - return CM_IDLEST info for HSOTGUSB
 * @clk: struct clk * being enabled
 * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
 * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
 *
 * The OMAP3430ES2 HSOTGUSB target CM_IDLEST bit is at a different
 * shift from the CM_{I,F}CLKEN bit.  Pass back the correct info via
 * @idlest_reg and @idlest_bit.  No return value.
 */
static void omap3430es2_clk_hsotgusb_find_idlest(struct clk *clk,
						 void __iomem **idlest_reg,
						 u8 *idlest_bit)
{
	u32 r;

	r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
	*idlest_reg = (__force void __iomem *)r;
	*idlest_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT;
}

const struct clkops clkops_omap3430es2_hsotgusb_wait = {
	.enable		= omap2_dflt_clk_enable,
	.disable	= omap2_dflt_clk_disable,
	.find_idlest	= omap3430es2_clk_hsotgusb_find_idlest,
	.find_companion = omap2_clk_dflt_find_companion,
};

const struct clkops clkops_noncore_dpll_ops = {
	.enable		= omap3_noncore_dpll_enable,
	.disable	= omap3_noncore_dpll_disable,
};

int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate)
{
	/*
	 * According to the 12-5 CDP code from TI, "Limitation 2.5"
	 * on 3430ES1 prevents us from changing DPLL multipliers or dividers
	 * on DPLL4.
	 */
	if (omap_rev() == OMAP3430_REV_ES1_0) {
		printk(KERN_ERR "clock: DPLL4 cannot change rate due to "
		       "silicon 'Limitation 2.5' on 3430ES1.\n");
		return -EINVAL;
	}
	return omap3_noncore_dpll_set_rate(clk, rate);
}


/*
 * CORE DPLL (DPLL3) rate programming functions
 *
 * These call into SRAM code to do the actual CM writes, since the SDRAM
 * is clocked from DPLL3.
 */

/**
 * omap3_core_dpll_m2_set_rate - set CORE DPLL M2 divider
 * @clk: struct clk * of DPLL to set
 * @rate: rounded target rate
 *
 * Program the DPLL M2 divider with the rounded target rate.  Returns
 * -EINVAL upon error, or 0 upon success.
 */
int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
{
	u32 new_div = 0;
	u32 unlock_dll = 0;
	u32 c;
	unsigned long validrate, sdrcrate, _mpurate;
	struct omap_sdrc_params *sdrc_cs0;
	struct omap_sdrc_params *sdrc_cs1;
	int ret;

	if (!clk || !rate)
		return -EINVAL;

	validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
	if (validrate != rate)
		return -EINVAL;

	sdrcrate = sdrc_ick_p->rate;
	if (rate > clk->rate)
		sdrcrate <<= ((rate / clk->rate) >> 1);
	else
		sdrcrate >>= ((clk->rate / rate) >> 1);

	ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1);
	if (ret)
		return -EINVAL;

	if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) {
		pr_debug("clock: will unlock SDRC DLL\n");
		unlock_dll = 1;
	}

	/*
	 * XXX This only needs to be done when the CPU frequency changes
	 */
	_mpurate = arm_fck_p->rate / CYCLES_PER_MHZ;
	c = (_mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT;
	c += 1;  /* for safety */
	c *= SDRC_MPURATE_LOOPS;
	c >>= SDRC_MPURATE_SCALE;
	if (c == 0)
		c = 1;

	pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
		 validrate);
	pr_debug("clock: SDRC CS0 timing params used:"
		 " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
		 sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
		 sdrc_cs0->actim_ctrlb, sdrc_cs0->mr);
	if (sdrc_cs1)
		pr_debug("clock: SDRC CS1 timing params used: "
		 " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
		 sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
		 sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);

	if (sdrc_cs1)
		omap3_configure_core_dpll(
				  new_div, unlock_dll, c, rate > clk->rate,
				  sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
				  sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
				  sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
				  sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
	else
		omap3_configure_core_dpll(
				  new_div, unlock_dll, c, rate > clk->rate,
				  sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
				  sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
				  0, 0, 0, 0);

	return 0;
}

/* Common clock code */

/*
 * As it is structured now, this will prevent an OMAP2/3 multiboot
 * kernel from compiling.  This will need further attention.
 */
#if defined(CONFIG_ARCH_OMAP3)

struct clk_functions omap2_clk_functions = {
	.clk_enable		= omap2_clk_enable,
	.clk_disable		= omap2_clk_disable,
	.clk_round_rate		= omap2_clk_round_rate,
	.clk_set_rate		= omap2_clk_set_rate,
	.clk_set_parent		= omap2_clk_set_parent,
	.clk_disable_unused	= omap2_clk_disable_unused,
};

/*
 * Set clocks for bypass mode for reboot to work.
 */
void omap2_clk_prepare_for_reboot(void)
{
	/* REVISIT: Not ready for 343x */
#if 0
	u32 rate;

	if (vclk == NULL || sclk == NULL)
		return;

	rate = clk_get_rate(sclk);
	clk_set_rate(vclk, rate);
#endif
}

void omap3_clk_lock_dpll5(void)
{
	struct clk *dpll5_clk;
	struct clk *dpll5_m2_clk;

	dpll5_clk = clk_get(NULL, "dpll5_ck");
	clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST);
	clk_enable(dpll5_clk);

	/* Enable autoidle to allow it to enter low power bypass */
	omap3_dpll_allow_idle(dpll5_clk);

	/* Program dpll5_m2_clk divider for no division */
	dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck");
	clk_enable(dpll5_m2_clk);
	clk_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST);

	clk_disable(dpll5_m2_clk);
	clk_disable(dpll5_clk);
	return;
}

/* REVISIT: Move this init stuff out into clock.c */

/*
 * Switch the MPU rate if specified on cmdline.
 * We cannot do this early until cmdline is parsed.
 */
static int __init omap2_clk_arch_init(void)
{
	struct clk *osc_sys_ck, *dpll1_ck, *arm_fck, *core_ck;
	unsigned long osc_sys_rate;

	if (!mpurate)
		return -EINVAL;

	/* XXX test these for success */
	dpll1_ck = clk_get(NULL, "dpll1_ck");
	arm_fck = clk_get(NULL, "arm_fck");
	core_ck = clk_get(NULL, "core_ck");
	osc_sys_ck = clk_get(NULL, "osc_sys_ck");

	/* REVISIT: not yet ready for 343x */
	if (clk_set_rate(dpll1_ck, mpurate))
		printk(KERN_ERR "*** Unable to set MPU rate\n");

	recalculate_root_clocks();

	osc_sys_rate = clk_get_rate(osc_sys_ck);

	pr_info("Switched to new clocking rate (Crystal/Core/MPU): "
		"%ld.%01ld/%ld/%ld MHz\n",
		(osc_sys_rate / 1000000),
		((osc_sys_rate / 100000) % 10),
		(clk_get_rate(core_ck) / 1000000),
		(clk_get_rate(arm_fck) / 1000000));

	calibrate_delay();

	return 0;
}
arch_initcall(omap2_clk_arch_init);


#endif
Commit	Line	Data
02e19a96 PW	1	/*
	2	* OMAP3-specific clock framework functions
	3	*
542313cc	4	* Copyright (C) 2007-2008 Texas Instruments, Inc.
3c82e229	5	* Copyright (C) 2007-2009 Nokia Corporation
02e19a96 PW	6	*
02e19a96 PW	7	* Written by Paul Walmsley
542313cc	8	* Testing and integration fixes by Jouni Högander
02e19a96 PW	9	*
	10	* Parts of this code are based on code written by
	11	* Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
	12	*
	13	* This program is free software; you can redistribute it and/or modify
	14	* it under the terms of the GNU General Public License version 2 as
	15	* published by the Free Software Foundation.
	16	*/
	17	#undef DEBUG
	18
	19	#include <linux/module.h>
	20	#include <linux/kernel.h>
	21	#include <linux/device.h>
	22	#include <linux/list.h>
	23	#include <linux/errno.h>
	24	#include <linux/delay.h>
	25	#include <linux/clk.h>
	26	#include <linux/io.h>
542313cc	27	#include <linux/limits.h>
fbd3bdb2	28	#include <linux/bitops.h>
02e19a96	29
ce491cf8 TL	30	#include <plat/cpu.h>
	31	#include <plat/clock.h>
	32	#include <plat/sram.h>
82e9bd58	33	#include <plat/sdrc.h>
02e19a96	34	#include <asm/div64.h>
44dc9d02	35	#include <asm/clkdev.h>
02e19a96	36
ce491cf8	37	#include <plat/sdrc.h>
02e19a96	38	#include "clock.h"
82e9bd58 PW	39	#include "clock34xx.h"
82e9bd58 PW	40	#include "sdrc.h"
02e19a96 PW	41	#include "prm.h"
	42	#include "prm-regbits-34xx.h"
	43	#include "cm.h"
	44	#include "cm-regbits-34xx.h"
	45
c9812d04 PW	46	#define CYCLES_PER_MHZ 1000000
c9812d04 PW	47
7a66a39b RN	48	/*
	49	* DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks
	50	* that are sourced by DPLL5, and both of these require this clock
	51	* to be at 120 MHz for proper operation.
	52	*/
	53	#define DPLL5_FREQ_FOR_USBHOST 120000000
	54
82e9bd58 PW	55	/* needed by omap3_core_dpll_m2_set_rate() */
	56	struct clk sdrc_ick_p, arm_fck_p;
	57
3c82e229 PW	58	/**
	59	* omap3430es2_clk_ssi_find_idlest - return CM_IDLEST info for SSI
	60	* @clk: struct clk * being enabled
	61	* @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
	62	* @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
	63	*
	64	* The OMAP3430ES2 SSI target CM_IDLEST bit is at a different shift
	65	* from the CM_{I,F}CLKEN bit. Pass back the correct info via
	66	* @idlest_reg and @idlest_bit. No return value.
	67	*/
	68	static void omap3430es2_clk_ssi_find_idlest(struct clk *clk,
	69	void __iomem **idlest_reg,
	70	u8 *idlest_bit)
	71	{
	72	u32 r;
	73
	74	r = (((__force u32)clk->enable_reg & ~0xf0) \| 0x20);
	75	idlest_reg = (__force void __iomem )r;
	76	*idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT;
	77	}
	78
82e9bd58 PW	79	const struct clkops clkops_omap3430es2_ssi_wait = {
	80	.enable = omap2_dflt_clk_enable,
	81	.disable = omap2_dflt_clk_disable,
	82	.find_idlest = omap3430es2_clk_ssi_find_idlest,
	83	.find_companion = omap2_clk_dflt_find_companion,
	84	};
	85
3c82e229 PW	86	/**
	87	* omap3430es2_clk_dss_usbhost_find_idlest - CM_IDLEST info for DSS, USBHOST
	88	* @clk: struct clk * being enabled
	89	* @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
	90	* @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
	91	*
	92	* Some OMAP modules on OMAP3 ES2+ chips have both initiator and
	93	* target IDLEST bits. For our purposes, we are concerned with the
	94	* target IDLEST bits, which exist at a different bit position than
	95	* the *CLKEN bit position for these modules (DSS and USBHOST) (The
	96	* default find_idlest code assumes that they are at the same
	97	* position.) No return value.
	98	*/
	99	static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk,
	100	void __iomem **idlest_reg,
	101	u8 *idlest_bit)
	102	{
	103	u32 r;
	104
	105	r = (((__force u32)clk->enable_reg & ~0xf0) \| 0x20);
	106	idlest_reg = (__force void __iomem )r;
	107	/* USBHOST_IDLE has same shift */
	108	*idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT;
	109	}
	110
82e9bd58 PW	111	const struct clkops clkops_omap3430es2_dss_usbhost_wait = {
	112	.enable = omap2_dflt_clk_enable,
	113	.disable = omap2_dflt_clk_disable,
	114	.find_idlest = omap3430es2_clk_dss_usbhost_find_idlest,
	115	.find_companion = omap2_clk_dflt_find_companion,
	116	};
	117
3c82e229 PW	118	/**
	119	* omap3430es2_clk_hsotgusb_find_idlest - return CM_IDLEST info for HSOTGUSB
	120	* @clk: struct clk * being enabled
	121	* @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
	122	* @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
	123	*
	124	* The OMAP3430ES2 HSOTGUSB target CM_IDLEST bit is at a different
	125	* shift from the CM_{I,F}CLKEN bit. Pass back the correct info via
	126	* @idlest_reg and @idlest_bit. No return value.
	127	*/
	128	static void omap3430es2_clk_hsotgusb_find_idlest(struct clk *clk,
	129	void __iomem **idlest_reg,
	130	u8 *idlest_bit)
	131	{
	132	u32 r;
	133
	134	r = (((__force u32)clk->enable_reg & ~0xf0) \| 0x20);
	135	idlest_reg = (__force void __iomem )r;
	136	*idlest_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT;
	137	}
	138
82e9bd58 PW	139	const struct clkops clkops_omap3430es2_hsotgusb_wait = {
	140	.enable = omap2_dflt_clk_enable,
	141	.disable = omap2_dflt_clk_disable,
	142	.find_idlest = omap3430es2_clk_hsotgusb_find_idlest,
	143	.find_companion = omap2_clk_dflt_find_companion,
	144	};
	145
82e9bd58 PW	146	const struct clkops clkops_noncore_dpll_ops = {
	147	.enable = omap3_noncore_dpll_enable,
	148	.disable = omap3_noncore_dpll_disable,
	149	};
16c90f02	150
82e9bd58	151	int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate)
16c90f02 PW	152	{
	153	/*
	154	* According to the 12-5 CDP code from TI, "Limitation 2.5"
	155	* on 3430ES1 prevents us from changing DPLL multipliers or dividers
	156	* on DPLL4.
	157	*/
	158	if (omap_rev() == OMAP3430_REV_ES1_0) {
	159	printk(KERN_ERR "clock: DPLL4 cannot change rate due to "
	160	"silicon 'Limitation 2.5' on 3430ES1.\n");
	161	return -EINVAL;
	162	}
	163	return omap3_noncore_dpll_set_rate(clk, rate);
	164	}
	165
0eafd472 PW	166
	167	/*
	168	* CORE DPLL (DPLL3) rate programming functions
	169	*
	170	* These call into SRAM code to do the actual CM writes, since the SDRAM
	171	* is clocked from DPLL3.
	172	*/
	173
	174	/**
	175	* omap3_core_dpll_m2_set_rate - set CORE DPLL M2 divider
	176	* @clk: struct clk * of DPLL to set
	177	* @rate: rounded target rate
	178	*
	179	* Program the DPLL M2 divider with the rounded target rate. Returns
	180	* -EINVAL upon error, or 0 upon success.
	181	*/
82e9bd58	182	int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
0eafd472 PW	183	{
0eafd472 PW	184	u32 new_div = 0;
4519c2bf	185	u32 unlock_dll = 0;
c9812d04	186	u32 c;
82e9bd58	187	unsigned long validrate, sdrcrate, _mpurate;
58cda884 JP	188	struct omap_sdrc_params *sdrc_cs0;
	189	struct omap_sdrc_params *sdrc_cs1;
	190	int ret;
0eafd472 PW	191
	192	if (!clk \|\| !rate)
	193	return -EINVAL;
	194
0eafd472 PW	195	validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
	196	if (validrate != rate)
	197	return -EINVAL;
	198
82e9bd58	199	sdrcrate = sdrc_ick_p->rate;
0eafd472	200	if (rate > clk->rate)
3afec633	201	sdrcrate <<= ((rate / clk->rate) >> 1);
0eafd472	202	else
3afec633	203	sdrcrate >>= ((clk->rate / rate) >> 1);
0eafd472	204
58cda884 JP	205	ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1);
58cda884 JP	206	if (ret)
0eafd472 PW	207	return -EINVAL;
0eafd472 PW	208
4519c2bf PW	209	if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) {
	210	pr_debug("clock: will unlock SDRC DLL\n");
	211	unlock_dll = 1;
	212	}
	213
c9812d04 PW	214	/*
	215	* XXX This only needs to be done when the CPU frequency changes
	216	*/
82e9bd58 PW	217	_mpurate = arm_fck_p->rate / CYCLES_PER_MHZ;
82e9bd58 PW	218	c = (_mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT;
c9812d04 PW	219	c += 1; /* for safety */
	220	c *= SDRC_MPURATE_LOOPS;
	221	c >>= SDRC_MPURATE_SCALE;
	222	if (c == 0)
	223	c = 1;
	224
b7aee4bf PW	225	pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
b7aee4bf PW	226	validrate);
58cda884 JP	227	pr_debug("clock: SDRC CS0 timing params used:"
	228	" RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
	229	sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
	230	sdrc_cs0->actim_ctrlb, sdrc_cs0->mr);
	231	if (sdrc_cs1)
	232	pr_debug("clock: SDRC CS1 timing params used: "
	233	" RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
	234	sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
	235	sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
	236
	237	if (sdrc_cs1)
	238	omap3_configure_core_dpll(
	239	new_div, unlock_dll, c, rate > clk->rate,
	240	sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
	241	sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
	242	sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
	243	sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
	244	else
	245	omap3_configure_core_dpll(
	246	new_div, unlock_dll, c, rate > clk->rate,
	247	sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
	248	sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
	249	0, 0, 0, 0);
0eafd472	250
0eafd472 PW	251	return 0;
	252	}
	253
542313cc PW	254	/* Common clock code */
542313cc PW	255
02e19a96 PW	256	/*
	257	* As it is structured now, this will prevent an OMAP2/3 multiboot
	258	* kernel from compiling. This will need further attention.
	259	*/
	260	#if defined(CONFIG_ARCH_OMAP3)
	261
82e9bd58	262	struct clk_functions omap2_clk_functions = {
02e19a96 PW	263	.clk_enable = omap2_clk_enable,
	264	.clk_disable = omap2_clk_disable,
	265	.clk_round_rate = omap2_clk_round_rate,
	266	.clk_set_rate = omap2_clk_set_rate,
	267	.clk_set_parent = omap2_clk_set_parent,
	268	.clk_disable_unused = omap2_clk_disable_unused,
	269	};
	270
	271	/*
	272	* Set clocks for bypass mode for reboot to work.
	273	*/
	274	void omap2_clk_prepare_for_reboot(void)
	275	{
	276	/* REVISIT: Not ready for 343x */
	277	#if 0
	278	u32 rate;
	279
	280	if (vclk == NULL \|\| sclk == NULL)
	281	return;
	282
	283	rate = clk_get_rate(sclk);
	284	clk_set_rate(vclk, rate);
	285	#endif
	286	}
	287
82e9bd58	288	void omap3_clk_lock_dpll5(void)
7a66a39b RN	289	{
	290	struct clk *dpll5_clk;
	291	struct clk *dpll5_m2_clk;
	292
	293	dpll5_clk = clk_get(NULL, "dpll5_ck");
	294	clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST);
	295	clk_enable(dpll5_clk);
	296
	297	/* Enable autoidle to allow it to enter low power bypass */
	298	omap3_dpll_allow_idle(dpll5_clk);
	299
	300	/* Program dpll5_m2_clk divider for no division */
	301	dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck");
	302	clk_enable(dpll5_m2_clk);
	303	clk_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST);
	304
	305	clk_disable(dpll5_m2_clk);
	306	clk_disable(dpll5_clk);
	307	return;
	308	}
	309
02e19a96 PW	310	/* REVISIT: Move this init stuff out into clock.c */
	311
	312	/*
	313	* Switch the MPU rate if specified on cmdline.
	314	* We cannot do this early until cmdline is parsed.
	315	*/
	316	static int __init omap2_clk_arch_init(void)
	317	{
82e9bd58 PW	318	struct clk osc_sys_ck, dpll1_ck, arm_fck, core_ck;
	319	unsigned long osc_sys_rate;
	320
02e19a96 PW	321	if (!mpurate)
	322	return -EINVAL;
	323
82e9bd58 PW	324	/* XXX test these for success */
	325	dpll1_ck = clk_get(NULL, "dpll1_ck");
	326	arm_fck = clk_get(NULL, "arm_fck");
	327	core_ck = clk_get(NULL, "core_ck");
	328	osc_sys_ck = clk_get(NULL, "osc_sys_ck");
	329
02e19a96	330	/* REVISIT: not yet ready for 343x */
82e9bd58	331	if (clk_set_rate(dpll1_ck, mpurate))
11b66383	332	printk(KERN_ERR "*** Unable to set MPU rate\n");
02e19a96 PW	333
	334	recalculate_root_clocks();
	335
82e9bd58 PW	336	osc_sys_rate = clk_get_rate(osc_sys_ck);
	337
	338	pr_info("Switched to new clocking rate (Crystal/Core/MPU): "
	339	"%ld.%01ld/%ld/%ld MHz\n",
	340	(osc_sys_rate / 1000000),
	341	((osc_sys_rate / 100000) % 10),
	342	(clk_get_rate(core_ck) / 1000000),
	343	(clk_get_rate(arm_fck) / 1000000));
11b66383 SP	344
11b66383 SP	345	calibrate_delay();
02e19a96 PW	346
	347	return 0;
	348	}
	349	arch_initcall(omap2_clk_arch_init);
	350
02e19a96	351
02e19a96 PW	352	#endif
02e19a96 PW	353
02e19a96	354