sh: update defconfigs.
[linux-2.6-block.git] / arch / arm / mach-omap1 / timer32k.c
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a569c6ec 1/*
5c8388e5 2 * linux/arch/arm/mach-omap1/timer32k.c
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3 *
4 * OMAP 32K Timer
5 *
6 * Copyright (C) 2004 - 2005 Nokia Corporation
7 * Partial timer rewrite and additional dynamic tick timer support by
8 * Tony Lindgen <tony@atomide.com> and
9 * Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
77900a2f 10 * OMAP Dual-mode timer framework support by Timo Teras
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11 *
12 * MPU timer code based on the older MPU timer code for OMAP
13 * Copyright (C) 2000 RidgeRun, Inc.
14 * Author: Greg Lonnon <glonnon@ridgerun.com>
15 *
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the
18 * Free Software Foundation; either version 2 of the License, or (at your
19 * option) any later version.
20 *
21 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
22 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
24 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
27 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * You should have received a copy of the GNU General Public License along
33 * with this program; if not, write to the Free Software Foundation, Inc.,
34 * 675 Mass Ave, Cambridge, MA 02139, USA.
35 */
36
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37#include <linux/kernel.h>
38#include <linux/init.h>
39#include <linux/delay.h>
40#include <linux/interrupt.h>
41#include <linux/sched.h>
42#include <linux/spinlock.h>
43#include <linux/err.h>
44#include <linux/clk.h>
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45#include <linux/clocksource.h>
46#include <linux/clockchips.h>
fced80c7 47#include <linux/io.h>
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48
49#include <asm/system.h>
a09e64fb 50#include <mach/hardware.h>
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51#include <asm/leds.h>
52#include <asm/irq.h>
53#include <asm/mach/irq.h>
54#include <asm/mach/time.h>
ce491cf8 55#include <plat/dmtimer.h>
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56
57struct sys_timer omap_timer;
58
59/*
60 * ---------------------------------------------------------------------------
61 * 32KHz OS timer
62 *
63 * This currently works only on 16xx, as 1510 does not have the continuous
64 * 32KHz synchronous timer. The 32KHz synchronous timer is used to keep track
65 * of time in addition to the 32KHz OS timer. Using only the 32KHz OS timer
66 * on 1510 would be possible, but the timer would not be as accurate as
67 * with the 32KHz synchronized timer.
68 * ---------------------------------------------------------------------------
69 */
70
71#if defined(CONFIG_ARCH_OMAP16XX)
72#define TIMER_32K_SYNCHRONIZED 0xfffbc410
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73#else
74#error OMAP 32KHz timer does not currently work on 15XX!
75#endif
76
77/* 16xx specific defines */
78#define OMAP1_32K_TIMER_BASE 0xfffb9000
79#define OMAP1_32K_TIMER_CR 0x08
80#define OMAP1_32K_TIMER_TVR 0x00
81#define OMAP1_32K_TIMER_TCR 0x04
82
075192ae 83#define OMAP_32K_TICKS_PER_SEC (32768)
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84
85/*
86 * TRM says 1 / HZ = ( TVR + 1) / 32768, so TRV = (32768 / HZ) - 1
87 * so with HZ = 128, TVR = 255.
88 */
075192ae 89#define OMAP_32K_TIMER_TICK_PERIOD ((OMAP_32K_TICKS_PER_SEC / HZ) - 1)
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90
91#define JIFFIES_TO_HW_TICKS(nr_jiffies, clock_rate) \
92 (((nr_jiffies) * (clock_rate)) / HZ)
93
94static inline void omap_32k_timer_write(int val, int reg)
95{
77900a2f 96 omap_writew(val, OMAP1_32K_TIMER_BASE + reg);
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97}
98
99static inline unsigned long omap_32k_timer_read(int reg)
100{
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101 return omap_readl(OMAP1_32K_TIMER_BASE + reg) & 0xffffff;
102}
a569c6ec 103
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104static inline void omap_32k_timer_start(unsigned long load_val)
105{
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106 if (!load_val)
107 load_val = 1;
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108 omap_32k_timer_write(load_val, OMAP1_32K_TIMER_TVR);
109 omap_32k_timer_write(0x0f, OMAP1_32K_TIMER_CR);
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110}
111
77900a2f 112static inline void omap_32k_timer_stop(void)
a569c6ec 113{
77900a2f 114 omap_32k_timer_write(0x0, OMAP1_32K_TIMER_CR);
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115}
116
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117#define omap_32k_timer_ack_irq()
118
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119static int omap_32k_timer_set_next_event(unsigned long delta,
120 struct clock_event_device *dev)
121{
122 omap_32k_timer_start(delta);
123
124 return 0;
125}
126
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127static void omap_32k_timer_set_mode(enum clock_event_mode mode,
128 struct clock_event_device *evt)
129{
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130 omap_32k_timer_stop();
131
075192ae 132 switch (mode) {
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133 case CLOCK_EVT_MODE_PERIODIC:
134 omap_32k_timer_start(OMAP_32K_TIMER_TICK_PERIOD);
135 break;
5c5dccad 136 case CLOCK_EVT_MODE_ONESHOT:
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137 case CLOCK_EVT_MODE_UNUSED:
138 case CLOCK_EVT_MODE_SHUTDOWN:
075192ae 139 break;
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140 case CLOCK_EVT_MODE_RESUME:
141 break;
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142 }
143}
144
145static struct clock_event_device clockevent_32k_timer = {
146 .name = "32k-timer",
5c8388e5 147 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
075192ae 148 .shift = 32,
5c8388e5 149 .set_next_event = omap_32k_timer_set_next_event,
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150 .set_mode = omap_32k_timer_set_mode,
151};
152
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153/*
154 * The 32KHz synchronized timer is an additional timer on 16xx.
155 * It is always running.
156 */
157static inline unsigned long omap_32k_sync_timer_read(void)
158{
159 return omap_readl(TIMER_32K_SYNCHRONIZED);
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160}
161
0cd61b68 162static irqreturn_t omap_32k_timer_interrupt(int irq, void *dev_id)
14188b3a 163{
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164 struct clock_event_device *evt = &clockevent_32k_timer;
165 omap_32k_timer_ack_irq();
14188b3a 166
075192ae 167 evt->event_handler(evt);
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168
169 return IRQ_HANDLED;
170}
171
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172static struct irqaction omap_32k_timer_irq = {
173 .name = "32KHz timer",
b30fabad 174 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
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175 .handler = omap_32k_timer_interrupt,
176};
177
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178static __init void omap_init_32k_timer(void)
179{
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180 setup_irq(INT_OS_TIMER, &omap_32k_timer_irq);
181
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182 clockevent_32k_timer.mult = div_sc(OMAP_32K_TICKS_PER_SEC,
183 NSEC_PER_SEC,
184 clockevent_32k_timer.shift);
185 clockevent_32k_timer.max_delta_ns =
186 clockevent_delta2ns(0xfffffffe, &clockevent_32k_timer);
187 clockevent_32k_timer.min_delta_ns =
188 clockevent_delta2ns(1, &clockevent_32k_timer);
189
320ab2b0 190 clockevent_32k_timer.cpumask = cpumask_of(0);
075192ae 191 clockevents_register_device(&clockevent_32k_timer);
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192}
193
194/*
195 * ---------------------------------------------------------------------------
196 * Timer initialization
197 * ---------------------------------------------------------------------------
198 */
199static void __init omap_timer_init(void)
200{
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201#ifdef CONFIG_OMAP_DM_TIMER
202 omap_dm_timer_init();
203#endif
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204 omap_init_32k_timer();
205}
206
207struct sys_timer omap_timer = {
208 .init = omap_timer_init,
a569c6ec 209};