projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| ea566a4b MY |
1 | // SPDX-License-Identifier: GPL-2.0+ OR MIT |
| 2 | // | |
| 3 | // Device Tree Source for UniPhier PXs2 SoC | |
| 4 | // | |
| 5 | // Copyright (C) 2015-2016 Socionext Inc. | |
| 6 | // Author: Masahiro Yamada <yamada.masahiro@socionext.com> | |
| a5e921b4 | 7 | |
| d1194d49 | 8 | #include <dt-bindings/gpio/uniphier-gpio.h> |
| fbd8d583 KH |
9 | #include <dt-bindings/thermal/thermal.h> |
| 10 | ||
| a5e921b4 | 11 | / { |
| 77896e4d | 12 | compatible = "socionext,uniphier-pxs2"; |
| 8e2b908b MY |
13 | #address-cells = <1>; |
| 14 | #size-cells = <1>; | |
| a5e921b4 MY |
15 | |
| 16 | cpus { | |
| 17 | #address-cells = <1>; | |
| 18 | #size-cells = <0>; | |
| a5e921b4 | 19 | |
| fbd8d583 | 20 | cpu0: cpu@0 { |
| a5e921b4 MY |
21 | device_type = "cpu"; |
| 22 | compatible = "arm,cortex-a9"; | |
| 23 | reg = <0>; | |
| 7a8a6588 | 24 | clocks = <&sys_clk 32>; |
| 3bdba5ac | 25 | enable-method = "psci"; |
| 7c62f299 | 26 | next-level-cache = <&l2>; |
| 7a8a6588 | 27 | operating-points-v2 = <&cpu_opp>; |
| fbd8d583 | 28 | #cooling-cells = <2>; |
| a5e921b4 MY |
29 | }; |
| 30 | ||
| fbd8d583 | 31 | cpu1: cpu@1 { |
| a5e921b4 MY |
32 | device_type = "cpu"; |
| 33 | compatible = "arm,cortex-a9"; | |
| 34 | reg = <1>; | |
| 7a8a6588 | 35 | clocks = <&sys_clk 32>; |
| 3bdba5ac | 36 | enable-method = "psci"; |
| 7c62f299 | 37 | next-level-cache = <&l2>; |
| 7a8a6588 | 38 | operating-points-v2 = <&cpu_opp>; |
| 38dc27c8 | 39 | #cooling-cells = <2>; |
| a5e921b4 MY |
40 | }; |
| 41 | ||
| fbd8d583 | 42 | cpu2: cpu@2 { |
| a5e921b4 MY |
43 | device_type = "cpu"; |
| 44 | compatible = "arm,cortex-a9"; | |
| 45 | reg = <2>; | |
| 7a8a6588 | 46 | clocks = <&sys_clk 32>; |
| 3bdba5ac | 47 | enable-method = "psci"; |
| 7c62f299 | 48 | next-level-cache = <&l2>; |
| 7a8a6588 | 49 | operating-points-v2 = <&cpu_opp>; |
| 38dc27c8 | 50 | #cooling-cells = <2>; |
| a5e921b4 MY |
51 | }; |
| 52 | ||
| fbd8d583 | 53 | cpu3: cpu@3 { |
| a5e921b4 MY |
54 | device_type = "cpu"; |
| 55 | compatible = "arm,cortex-a9"; | |
| 56 | reg = <3>; | |
| 7a8a6588 | 57 | clocks = <&sys_clk 32>; |
| 3bdba5ac | 58 | enable-method = "psci"; |
| 7c62f299 | 59 | next-level-cache = <&l2>; |
| 7a8a6588 | 60 | operating-points-v2 = <&cpu_opp>; |
| 38dc27c8 | 61 | #cooling-cells = <2>; |
| 7a8a6588 MY |
62 | }; |
| 63 | }; | |
| 64 | ||
| 1658b84d | 65 | cpu_opp: opp-table { |
| 7a8a6588 MY |
66 | compatible = "operating-points-v2"; |
| 67 | opp-shared; | |
| 68 | ||
| f21683ae | 69 | opp-100000000 { |
| 7a8a6588 MY |
70 | opp-hz = /bits/ 64 <100000000>; |
| 71 | clock-latency-ns = <300>; | |
| 72 | }; | |
| f21683ae | 73 | opp-150000000 { |
| 7a8a6588 MY |
74 | opp-hz = /bits/ 64 <150000000>; |
| 75 | clock-latency-ns = <300>; | |
| 76 | }; | |
| f21683ae | 77 | opp-200000000 { |
| 7a8a6588 MY |
78 | opp-hz = /bits/ 64 <200000000>; |
| 79 | clock-latency-ns = <300>; | |
| 80 | }; | |
| f21683ae | 81 | opp-300000000 { |
| 7a8a6588 MY |
82 | opp-hz = /bits/ 64 <300000000>; |
| 83 | clock-latency-ns = <300>; | |
| 84 | }; | |
| f21683ae | 85 | opp-400000000 { |
| 7a8a6588 MY |
86 | opp-hz = /bits/ 64 <400000000>; |
| 87 | clock-latency-ns = <300>; | |
| 88 | }; | |
| f21683ae | 89 | opp-600000000 { |
| 7a8a6588 MY |
90 | opp-hz = /bits/ 64 <600000000>; |
| 91 | clock-latency-ns = <300>; | |
| 92 | }; | |
| f21683ae | 93 | opp-800000000 { |
| 7a8a6588 MY |
94 | opp-hz = /bits/ 64 <800000000>; |
| 95 | clock-latency-ns = <300>; | |
| 96 | }; | |
| f21683ae | 97 | opp-1200000000 { |
| 7a8a6588 MY |
98 | opp-hz = /bits/ 64 <1200000000>; |
| 99 | clock-latency-ns = <300>; | |
| a5e921b4 MY |
100 | }; |
| 101 | }; | |
| 102 | ||
| 2752bcaa MY |
103 | psci { |
| 104 | compatible = "arm,psci-0.2"; | |
| 105 | method = "smc"; | |
| 106 | }; | |
| 107 | ||
| a5e921b4 | 108 | clocks { |
| 2752bcaa MY |
109 | refclk: ref { |
| 110 | compatible = "fixed-clock"; | |
| 111 | #clock-cells = <0>; | |
| 112 | clock-frequency = <25000000>; | |
| 113 | }; | |
| 114 | ||
| 1658b84d | 115 | arm_timer_clk: arm-timer { |
| a5e921b4 MY |
116 | #clock-cells = <0>; |
| 117 | compatible = "fixed-clock"; | |
| 118 | clock-frequency = <50000000>; | |
| 119 | }; | |
| a5e921b4 MY |
120 | }; |
| 121 | ||
| fbd8d583 KH |
122 | thermal-zones { |
| 123 | cpu-thermal { | |
| 124 | polling-delay-passive = <250>; /* 250ms */ | |
| 125 | polling-delay = <1000>; /* 1000ms */ | |
| 126 | thermal-sensors = <&pvtctl>; | |
| 127 | ||
| 128 | trips { | |
| 129 | cpu_crit: cpu-crit { | |
| 130 | temperature = <95000>; /* 95C */ | |
| 131 | hysteresis = <2000>; | |
| 132 | type = "critical"; | |
| 133 | }; | |
| 134 | cpu_alert: cpu-alert { | |
| 135 | temperature = <85000>; /* 85C */ | |
| 136 | hysteresis = <2000>; | |
| 137 | type = "passive"; | |
| 138 | }; | |
| 139 | }; | |
| 140 | ||
| 141 | cooling-maps { | |
| 142 | map { | |
| 143 | trip = <&cpu_alert>; | |
| aec2c812 VK |
144 | cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| 145 | <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 146 | <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 147 | <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
| fbd8d583 KH |
148 | }; |
| 149 | }; | |
| 150 | }; | |
| 151 | }; | |
| 152 | ||
| 2752bcaa MY |
153 | soc { |
| 154 | compatible = "simple-bus"; | |
| 629b557a | 155 | #address-cells = <1>; |
| 2752bcaa MY |
156 | #size-cells = <1>; |
| 157 | ranges; | |
| 158 | interrupt-parent = <&intc>; | |
| a5e921b4 | 159 | |
| 2752bcaa MY |
160 | l2: l2-cache@500c0000 { |
| 161 | compatible = "socionext,uniphier-system-cache"; | |
| 162 | reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, | |
| 163 | <0x506c0000 0x400>; | |
| 164 | interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>; | |
| 165 | cache-unified; | |
| 166 | cache-size = <(1280 * 1024)>; | |
| 167 | cache-sets = <512>; | |
| 168 | cache-line-size = <128>; | |
| 169 | cache-level = <2>; | |
| 170 | }; | |
| a5e921b4 | 171 | |
| 92fa4f4c KH |
172 | spi0: spi@54006000 { |
| 173 | compatible = "socionext,uniphier-scssi"; | |
| 174 | status = "disabled"; | |
| 175 | reg = <0x54006000 0x100>; | |
| 176 | interrupts = <0 39 4>; | |
| 177 | pinctrl-names = "default"; | |
| 178 | pinctrl-0 = <&pinctrl_spi0>; | |
| 179 | clocks = <&peri_clk 11>; | |
| 180 | resets = <&peri_rst 11>; | |
| 181 | }; | |
| 182 | ||
| 183 | spi1: spi@54006100 { | |
| 184 | compatible = "socionext,uniphier-scssi"; | |
| 185 | status = "disabled"; | |
| 186 | reg = <0x54006100 0x100>; | |
| 187 | interrupts = <0 216 4>; | |
| 188 | pinctrl-names = "default"; | |
| 189 | pinctrl-0 = <&pinctrl_spi1>; | |
| 190 | clocks = <&peri_clk 11>; | |
| 191 | resets = <&peri_rst 11>; | |
| 192 | }; | |
| 193 | ||
| 2752bcaa MY |
194 | serial0: serial@54006800 { |
| 195 | compatible = "socionext,uniphier-uart"; | |
| 196 | status = "disabled"; | |
| 197 | reg = <0x54006800 0x40>; | |
| 198 | interrupts = <0 33 4>; | |
| 199 | pinctrl-names = "default"; | |
| 200 | pinctrl-0 = <&pinctrl_uart0>; | |
| 201 | clocks = <&peri_clk 0>; | |
| a1763a82 | 202 | resets = <&peri_rst 0>; |
| 2752bcaa | 203 | }; |
| a5e921b4 | 204 | |
| 2752bcaa MY |
205 | serial1: serial@54006900 { |
| 206 | compatible = "socionext,uniphier-uart"; | |
| 207 | status = "disabled"; | |
| 208 | reg = <0x54006900 0x40>; | |
| 209 | interrupts = <0 35 4>; | |
| 210 | pinctrl-names = "default"; | |
| 211 | pinctrl-0 = <&pinctrl_uart1>; | |
| 212 | clocks = <&peri_clk 1>; | |
| a1763a82 | 213 | resets = <&peri_rst 1>; |
| 2752bcaa | 214 | }; |
| a5e921b4 | 215 | |
| 2752bcaa MY |
216 | serial2: serial@54006a00 { |
| 217 | compatible = "socionext,uniphier-uart"; | |
| 218 | status = "disabled"; | |
| 219 | reg = <0x54006a00 0x40>; | |
| 220 | interrupts = <0 37 4>; | |
| 221 | pinctrl-names = "default"; | |
| 222 | pinctrl-0 = <&pinctrl_uart2>; | |
| 223 | clocks = <&peri_clk 2>; | |
| a1763a82 | 224 | resets = <&peri_rst 2>; |
| 2752bcaa | 225 | }; |
| a5e921b4 | 226 | |
| 2752bcaa MY |
227 | serial3: serial@54006b00 { |
| 228 | compatible = "socionext,uniphier-uart"; | |
| 229 | status = "disabled"; | |
| 230 | reg = <0x54006b00 0x40>; | |
| 231 | interrupts = <0 177 4>; | |
| 232 | pinctrl-names = "default"; | |
| 233 | pinctrl-0 = <&pinctrl_uart3>; | |
| 234 | clocks = <&peri_clk 3>; | |
| a1763a82 | 235 | resets = <&peri_rst 3>; |
| 2752bcaa | 236 | }; |
| a5e921b4 | 237 | |
| 5d4bc4bd MY |
238 | gpio: gpio@55000000 { |
| 239 | compatible = "socionext,uniphier-gpio"; | |
| 240 | reg = <0x55000000 0x200>; | |
| 241 | interrupt-parent = <&aidet>; | |
| 242 | interrupt-controller; | |
| 243 | #interrupt-cells = <2>; | |
| 244 | gpio-controller; | |
| 245 | #gpio-cells = <2>; | |
| 246 | gpio-ranges = <&pinctrl 0 0 0>, | |
| 247 | <&pinctrl 96 0 0>; | |
| 248 | gpio-ranges-group-names = "gpio_range0", | |
| 249 | "gpio_range1"; | |
| 250 | ngpios = <232>; | |
| 251 | socionext,interrupt-ranges = <0 48 16>, <16 154 5>, | |
| 252 | <21 217 3>; | |
| 253 | }; | |
| 254 | ||
| 7f9f76b1 KS |
255 | audio@56000000 { |
| 256 | compatible = "socionext,uniphier-pxs2-aio"; | |
| 257 | reg = <0x56000000 0x80000>; | |
| 258 | interrupts = <0 144 4>; | |
| 259 | pinctrl-names = "default"; | |
| 260 | pinctrl-0 = <&pinctrl_ain1>, | |
| 261 | <&pinctrl_ain2>, | |
| 262 | <&pinctrl_ainiec1>, | |
| 263 | <&pinctrl_aout2>, | |
| 264 | <&pinctrl_aout3>, | |
| 265 | <&pinctrl_aoutiec1>, | |
| 266 | <&pinctrl_aoutiec2>; | |
| 267 | clock-names = "aio"; | |
| 268 | clocks = <&sys_clk 40>; | |
| 269 | reset-names = "aio"; | |
| 270 | resets = <&sys_rst 40>; | |
| 271 | #sound-dai-cells = <1>; | |
| 6f36ee0b | 272 | socionext,syscon = <&soc_glue>; |
| 7f9f76b1 KS |
273 | |
| 274 | i2s_port0: port@0 { | |
| 275 | i2s_hdmi: endpoint { | |
| 276 | }; | |
| 277 | }; | |
| 278 | ||
| 279 | i2s_port1: port@1 { | |
| 280 | i2s_line: endpoint { | |
| 281 | }; | |
| 282 | }; | |
| 283 | ||
| 284 | i2s_port2: port@2 { | |
| 285 | i2s_aux: endpoint { | |
| 286 | }; | |
| 287 | }; | |
| 288 | ||
| 289 | spdif_port0: port@3 { | |
| 290 | spdif_hiecout1: endpoint { | |
| 291 | }; | |
| 292 | }; | |
| 293 | ||
| 294 | spdif_port1: port@4 { | |
| 295 | spdif_iecout1: endpoint { | |
| 296 | }; | |
| 297 | }; | |
| 298 | ||
| 299 | comp_spdif_port0: port@5 { | |
| 300 | comp_spdif_hiecout1: endpoint { | |
| 301 | }; | |
| 302 | }; | |
| 303 | ||
| 304 | comp_spdif_port1: port@6 { | |
| 305 | comp_spdif_iecout1: endpoint { | |
| 306 | }; | |
| 307 | }; | |
| 308 | }; | |
| 309 | ||
| 2752bcaa MY |
310 | i2c0: i2c@58780000 { |
| 311 | compatible = "socionext,uniphier-fi2c"; | |
| 312 | status = "disabled"; | |
| 313 | reg = <0x58780000 0x80>; | |
| 314 | #address-cells = <1>; | |
| 315 | #size-cells = <0>; | |
| 316 | interrupts = <0 41 4>; | |
| 317 | pinctrl-names = "default"; | |
| 318 | pinctrl-0 = <&pinctrl_i2c0>; | |
| 319 | clocks = <&peri_clk 4>; | |
| a1763a82 | 320 | resets = <&peri_rst 4>; |
| 2752bcaa MY |
321 | clock-frequency = <100000>; |
| 322 | }; | |
| a5e921b4 | 323 | |
| 2752bcaa MY |
324 | i2c1: i2c@58781000 { |
| 325 | compatible = "socionext,uniphier-fi2c"; | |
| 326 | status = "disabled"; | |
| 327 | reg = <0x58781000 0x80>; | |
| 328 | #address-cells = <1>; | |
| 329 | #size-cells = <0>; | |
| 330 | interrupts = <0 42 4>; | |
| 331 | pinctrl-names = "default"; | |
| 332 | pinctrl-0 = <&pinctrl_i2c1>; | |
| 333 | clocks = <&peri_clk 5>; | |
| a1763a82 | 334 | resets = <&peri_rst 5>; |
| 2752bcaa MY |
335 | clock-frequency = <100000>; |
| 336 | }; | |
| 61f838c7 | 337 | |
| 2752bcaa MY |
338 | i2c2: i2c@58782000 { |
| 339 | compatible = "socionext,uniphier-fi2c"; | |
| 340 | status = "disabled"; | |
| 341 | reg = <0x58782000 0x80>; | |
| 342 | #address-cells = <1>; | |
| 343 | #size-cells = <0>; | |
| 344 | interrupts = <0 43 4>; | |
| 345 | pinctrl-names = "default"; | |
| 346 | pinctrl-0 = <&pinctrl_i2c2>; | |
| 347 | clocks = <&peri_clk 6>; | |
| a1763a82 | 348 | resets = <&peri_rst 6>; |
| 2752bcaa MY |
349 | clock-frequency = <100000>; |
| 350 | }; | |
| ad0561d4 | 351 | |
| 2752bcaa MY |
352 | i2c3: i2c@58783000 { |
| 353 | compatible = "socionext,uniphier-fi2c"; | |
| 354 | status = "disabled"; | |
| 355 | reg = <0x58783000 0x80>; | |
| 356 | #address-cells = <1>; | |
| 357 | #size-cells = <0>; | |
| 358 | interrupts = <0 44 4>; | |
| 359 | pinctrl-names = "default"; | |
| 360 | pinctrl-0 = <&pinctrl_i2c3>; | |
| 361 | clocks = <&peri_clk 7>; | |
| a1763a82 | 362 | resets = <&peri_rst 7>; |
| 2752bcaa MY |
363 | clock-frequency = <100000>; |
| 364 | }; | |
| ad0561d4 | 365 | |
| 2752bcaa MY |
366 | /* chip-internal connection for DMD */ |
| 367 | i2c4: i2c@58784000 { | |
| 368 | compatible = "socionext,uniphier-fi2c"; | |
| 369 | reg = <0x58784000 0x80>; | |
| 370 | #address-cells = <1>; | |
| 371 | #size-cells = <0>; | |
| 372 | interrupts = <0 45 4>; | |
| 373 | clocks = <&peri_clk 8>; | |
| a1763a82 | 374 | resets = <&peri_rst 8>; |
| 2752bcaa MY |
375 | clock-frequency = <400000>; |
| 376 | }; | |
| ad0561d4 | 377 | |
| 2752bcaa MY |
378 | /* chip-internal connection for STM */ |
| 379 | i2c5: i2c@58785000 { | |
| 380 | compatible = "socionext,uniphier-fi2c"; | |
| 381 | reg = <0x58785000 0x80>; | |
| 382 | #address-cells = <1>; | |
| 383 | #size-cells = <0>; | |
| 384 | interrupts = <0 25 4>; | |
| 385 | clocks = <&peri_clk 9>; | |
| a1763a82 | 386 | resets = <&peri_rst 9>; |
| 2752bcaa MY |
387 | clock-frequency = <400000>; |
| 388 | }; | |
| ad0561d4 | 389 | |
| 2752bcaa MY |
390 | /* chip-internal connection for HDMI */ |
| 391 | i2c6: i2c@58786000 { | |
| 392 | compatible = "socionext,uniphier-fi2c"; | |
| 393 | reg = <0x58786000 0x80>; | |
| 394 | #address-cells = <1>; | |
| 395 | #size-cells = <0>; | |
| 396 | interrupts = <0 26 4>; | |
| 397 | clocks = <&peri_clk 10>; | |
| a1763a82 | 398 | resets = <&peri_rst 10>; |
| 2752bcaa MY |
399 | clock-frequency = <400000>; |
| 400 | }; | |
| ad0561d4 | 401 | |
| 2752bcaa MY |
402 | system_bus: system-bus@58c00000 { |
| 403 | compatible = "socionext,uniphier-system-bus"; | |
| 404 | status = "disabled"; | |
| 405 | reg = <0x58c00000 0x400>; | |
| 406 | #address-cells = <2>; | |
| 407 | #size-cells = <1>; | |
| 408 | pinctrl-names = "default"; | |
| 409 | pinctrl-0 = <&pinctrl_system_bus>; | |
| 410 | }; | |
| 411 | ||
| 18088678 | 412 | smpctrl@59801000 { |
| 2752bcaa MY |
413 | compatible = "socionext,uniphier-smpctrl"; |
| 414 | reg = <0x59801000 0x400>; | |
| 415 | }; | |
| 416 | ||
| 417 | sdctrl@59810000 { | |
| 418 | compatible = "socionext,uniphier-pxs2-sdctrl", | |
| 419 | "simple-mfd", "syscon"; | |
| 7b8330d2 | 420 | reg = <0x59810000 0x400>; |
| 2752bcaa MY |
421 | |
| 422 | sd_clk: clock { | |
| 423 | compatible = "socionext,uniphier-pxs2-sd-clock"; | |
| 424 | #clock-cells = <1>; | |
| 425 | }; | |
| 426 | ||
| 427 | sd_rst: reset { | |
| 428 | compatible = "socionext,uniphier-pxs2-sd-reset"; | |
| 429 | #reset-cells = <1>; | |
| 430 | }; | |
| 431 | }; | |
| ad0561d4 | 432 | |
| 2752bcaa MY |
433 | perictrl@59820000 { |
| 434 | compatible = "socionext,uniphier-pxs2-perictrl", | |
| 435 | "simple-mfd", "syscon"; | |
| 436 | reg = <0x59820000 0x200>; | |
| 437 | ||
| 438 | peri_clk: clock { | |
| 439 | compatible = "socionext,uniphier-pxs2-peri-clock"; | |
| 440 | #clock-cells = <1>; | |
| 441 | }; | |
| 442 | ||
| 443 | peri_rst: reset { | |
| 444 | compatible = "socionext,uniphier-pxs2-peri-reset"; | |
| 445 | #reset-cells = <1>; | |
| 446 | }; | |
| 447 | }; | |
| 448 | ||
| b0a6261f MY |
449 | emmc: sdhc@5a000000 { |
| 450 | compatible = "socionext,uniphier-sd-v3.1.1"; | |
| 451 | status = "disabled"; | |
| 452 | reg = <0x5a000000 0x800>; | |
| 453 | interrupts = <0 78 4>; | |
| 454 | pinctrl-names = "default"; | |
| 455 | pinctrl-0 = <&pinctrl_emmc>; | |
| 456 | clocks = <&sd_clk 1>; | |
| 457 | reset-names = "host", "hw"; | |
| 458 | resets = <&sd_rst 1>, <&sd_rst 6>; | |
| 459 | bus-width = <8>; | |
| 460 | cap-mmc-highspeed; | |
| 461 | cap-mmc-hw-reset; | |
| 462 | non-removable; | |
| 463 | }; | |
| 464 | ||
| 465 | sd: sdhc@5a400000 { | |
| 466 | compatible = "socionext,uniphier-sd-v3.1.1"; | |
| 467 | status = "disabled"; | |
| 468 | reg = <0x5a400000 0x800>; | |
| 469 | interrupts = <0 76 4>; | |
| 470 | pinctrl-names = "default", "uhs"; | |
| 471 | pinctrl-0 = <&pinctrl_sd>; | |
| 472 | pinctrl-1 = <&pinctrl_sd_uhs>; | |
| 473 | clocks = <&sd_clk 0>; | |
| 474 | reset-names = "host"; | |
| 475 | resets = <&sd_rst 0>; | |
| 476 | bus-width = <4>; | |
| 477 | cap-sd-highspeed; | |
| 478 | sd-uhs-sdr12; | |
| 479 | sd-uhs-sdr25; | |
| 480 | sd-uhs-sdr50; | |
| 481 | }; | |
| 482 | ||
| 6f36ee0b | 483 | soc_glue: soc-glue@5f800000 { |
| 2752bcaa MY |
484 | compatible = "socionext,uniphier-pxs2-soc-glue", |
| 485 | "simple-mfd", "syscon"; | |
| 486 | reg = <0x5f800000 0x2000>; | |
| 487 | ||
| 488 | pinctrl: pinctrl { | |
| 489 | compatible = "socionext,uniphier-pxs2-pinctrl"; | |
| 490 | }; | |
| 491 | }; | |
| 492 | ||
| 6b968186 KH |
493 | soc-glue@5f900000 { |
| 494 | compatible = "socionext,uniphier-pxs2-soc-glue-debug", | |
| 495 | "simple-mfd"; | |
| 496 | #address-cells = <1>; | |
| 497 | #size-cells = <1>; | |
| 498 | ranges = <0 0x5f900000 0x2000>; | |
| 499 | ||
| 500 | efuse@100 { | |
| 501 | compatible = "socionext,uniphier-efuse"; | |
| 502 | reg = <0x100 0x28>; | |
| 503 | }; | |
| 504 | ||
| 505 | efuse@200 { | |
| 506 | compatible = "socionext,uniphier-efuse"; | |
| 507 | reg = <0x200 0x58>; | |
| 508 | }; | |
| 509 | }; | |
| 510 | ||
| 80a68704 MY |
511 | aidet: aidet@5fc20000 { |
| 512 | compatible = "socionext,uniphier-pxs2-aidet"; | |
| 513 | reg = <0x5fc20000 0x200>; | |
| 514 | interrupt-controller; | |
| 515 | #interrupt-cells = <2>; | |
| 516 | }; | |
| 517 | ||
| 2752bcaa MY |
518 | timer@60000200 { |
| 519 | compatible = "arm,cortex-a9-global-timer"; | |
| 520 | reg = <0x60000200 0x20>; | |
| 521 | interrupts = <1 11 0xf04>; | |
| 522 | clocks = <&arm_timer_clk>; | |
| 523 | }; | |
| 524 | ||
| 525 | timer@60000600 { | |
| 526 | compatible = "arm,cortex-a9-twd-timer"; | |
| 527 | reg = <0x60000600 0x20>; | |
| 528 | interrupts = <1 13 0xf04>; | |
| 529 | clocks = <&arm_timer_clk>; | |
| 530 | }; | |
| 531 | ||
| 532 | intc: interrupt-controller@60001000 { | |
| 533 | compatible = "arm,cortex-a9-gic"; | |
| 534 | reg = <0x60001000 0x1000>, | |
| 535 | <0x60000100 0x100>; | |
| 536 | #interrupt-cells = <3>; | |
| 537 | interrupt-controller; | |
| 538 | }; | |
| 539 | ||
| 540 | sysctrl@61840000 { | |
| 541 | compatible = "socionext,uniphier-pxs2-sysctrl", | |
| 542 | "simple-mfd", "syscon"; | |
| 543 | reg = <0x61840000 0x10000>; | |
| 544 | ||
| 545 | sys_clk: clock { | |
| 546 | compatible = "socionext,uniphier-pxs2-clock"; | |
| 547 | #clock-cells = <1>; | |
| 548 | }; | |
| 549 | ||
| 550 | sys_rst: reset { | |
| 551 | compatible = "socionext,uniphier-pxs2-reset"; | |
| 552 | #reset-cells = <1>; | |
| 553 | }; | |
| fbd8d583 KH |
554 | |
| 555 | pvtctl: pvtctl { | |
| 556 | compatible = "socionext,uniphier-pxs2-thermal"; | |
| 557 | interrupts = <0 3 4>; | |
| 558 | #thermal-sensor-cells = <0>; | |
| 559 | socionext,tmod-calibration = <0x0f86 0x6844>; | |
| 560 | }; | |
| 2752bcaa | 561 | }; |
| 69f9cdc6 | 562 | |
| e3cc9319 KH |
563 | eth: ethernet@65000000 { |
| 564 | compatible = "socionext,uniphier-pxs2-ave4"; | |
| 565 | status = "disabled"; | |
| 566 | reg = <0x65000000 0x8500>; | |
| 567 | interrupts = <0 66 4>; | |
| 568 | pinctrl-names = "default"; | |
| 569 | pinctrl-0 = <&pinctrl_ether_rgmii>; | |
| 92724c03 | 570 | clock-names = "ether"; |
| e3cc9319 | 571 | clocks = <&sys_clk 6>; |
| 92724c03 | 572 | reset-names = "ether"; |
| e3cc9319 KH |
573 | resets = <&sys_rst 6>; |
| 574 | phy-mode = "rgmii"; | |
| 575 | local-mac-address = [00 00 00 00 00 00]; | |
| 526f872b | 576 | socionext,syscon-phy-mode = <&soc_glue 0>; |
| e3cc9319 KH |
577 | |
| 578 | mdio: mdio { | |
| 579 | #address-cells = <1>; | |
| 580 | #size-cells = <0>; | |
| 581 | }; | |
| 582 | }; | |
| 583 | ||
| 45be1573 KH |
584 | usb0: usb@65a00000 { |
| 585 | compatible = "socionext,uniphier-dwc3", "snps,dwc3"; | |
| 586 | status = "disabled"; | |
| 587 | reg = <0x65a00000 0xcd00>; | |
| 588 | interrupt-names = "host", "peripheral"; | |
| 589 | interrupts = <0 134 4>, <0 135 4>; | |
| 590 | pinctrl-names = "default"; | |
| 591 | pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>; | |
| 592 | clock-names = "ref", "bus_early", "suspend"; | |
| 593 | clocks = <&sys_clk 14>, <&sys_clk 14>, <&sys_clk 14>; | |
| 594 | resets = <&usb0_rst 15>; | |
| 595 | phys = <&usb0_hsphy0>, <&usb0_hsphy1>, | |
| 596 | <&usb0_ssphy0>, <&usb0_ssphy1>; | |
| 597 | dr_mode = "host"; | |
| 598 | }; | |
| 599 | ||
| 600 | usb-glue@65b00000 { | |
| 601 | compatible = "socionext,uniphier-pxs2-dwc3-glue", | |
| 602 | "simple-mfd"; | |
| 603 | #address-cells = <1>; | |
| 604 | #size-cells = <1>; | |
| 605 | ranges = <0 0x65b00000 0x400>; | |
| 606 | ||
| 607 | usb0_rst: reset@0 { | |
| 608 | compatible = "socionext,uniphier-pxs2-usb3-reset"; | |
| 609 | reg = <0x0 0x4>; | |
| 610 | #reset-cells = <1>; | |
| 611 | clock-names = "link"; | |
| 612 | clocks = <&sys_clk 14>; | |
| 613 | reset-names = "link"; | |
| 614 | resets = <&sys_rst 14>; | |
| 615 | }; | |
| 616 | ||
| 617 | usb0_vbus0: regulator@100 { | |
| 618 | compatible = "socionext,uniphier-pxs2-usb3-regulator"; | |
| 619 | reg = <0x100 0x10>; | |
| 620 | clock-names = "link"; | |
| 621 | clocks = <&sys_clk 14>; | |
| 622 | reset-names = "link"; | |
| 623 | resets = <&sys_rst 14>; | |
| 624 | }; | |
| 625 | ||
| 626 | usb0_vbus1: regulator@110 { | |
| 627 | compatible = "socionext,uniphier-pxs2-usb3-regulator"; | |
| 628 | reg = <0x110 0x10>; | |
| 629 | clock-names = "link"; | |
| 630 | clocks = <&sys_clk 14>; | |
| 631 | reset-names = "link"; | |
| 632 | resets = <&sys_rst 14>; | |
| 633 | }; | |
| 634 | ||
| 635 | usb0_hsphy0: hs-phy@200 { | |
| 636 | compatible = "socionext,uniphier-pxs2-usb3-hsphy"; | |
| 637 | reg = <0x200 0x10>; | |
| 638 | #phy-cells = <0>; | |
| 639 | clock-names = "link", "phy"; | |
| 640 | clocks = <&sys_clk 14>, <&sys_clk 16>; | |
| 641 | reset-names = "link", "phy"; | |
| 642 | resets = <&sys_rst 14>, <&sys_rst 16>; | |
| 643 | vbus-supply = <&usb0_vbus0>; | |
| 644 | }; | |
| 645 | ||
| 646 | usb0_hsphy1: hs-phy@210 { | |
| 647 | compatible = "socionext,uniphier-pxs2-usb3-hsphy"; | |
| 648 | reg = <0x210 0x10>; | |
| 649 | #phy-cells = <0>; | |
| 650 | clock-names = "link", "phy"; | |
| 651 | clocks = <&sys_clk 14>, <&sys_clk 16>; | |
| 652 | reset-names = "link", "phy"; | |
| 653 | resets = <&sys_rst 14>, <&sys_rst 16>; | |
| 654 | vbus-supply = <&usb0_vbus1>; | |
| 655 | }; | |
| 656 | ||
| 657 | usb0_ssphy0: ss-phy@300 { | |
| 658 | compatible = "socionext,uniphier-pxs2-usb3-ssphy"; | |
| 659 | reg = <0x300 0x10>; | |
| 660 | #phy-cells = <0>; | |
| 661 | clock-names = "link", "phy"; | |
| 662 | clocks = <&sys_clk 14>, <&sys_clk 17>; | |
| 663 | reset-names = "link", "phy"; | |
| 664 | resets = <&sys_rst 14>, <&sys_rst 17>; | |
| 665 | vbus-supply = <&usb0_vbus0>; | |
| 666 | }; | |
| 667 | ||
| 668 | usb0_ssphy1: ss-phy@310 { | |
| 669 | compatible = "socionext,uniphier-pxs2-usb3-ssphy"; | |
| 670 | reg = <0x310 0x10>; | |
| 671 | #phy-cells = <0>; | |
| 672 | clock-names = "link", "phy"; | |
| 673 | clocks = <&sys_clk 14>, <&sys_clk 18>; | |
| 674 | reset-names = "link", "phy"; | |
| 675 | resets = <&sys_rst 14>, <&sys_rst 18>; | |
| 676 | vbus-supply = <&usb0_vbus1>; | |
| 677 | }; | |
| 678 | }; | |
| 679 | ||
| 680 | usb1: usb@65c00000 { | |
| 681 | compatible = "socionext,uniphier-dwc3", "snps,dwc3"; | |
| 682 | status = "disabled"; | |
| 683 | reg = <0x65c00000 0xcd00>; | |
| 684 | interrupt-names = "host", "peripheral"; | |
| 685 | interrupts = <0 137 4>, <0 138 4>; | |
| 686 | pinctrl-names = "default"; | |
| 687 | pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>; | |
| 688 | clock-names = "ref", "bus_early", "suspend"; | |
| 689 | clocks = <&sys_clk 15>, <&sys_clk 15>, <&sys_clk 15>; | |
| 690 | resets = <&usb1_rst 15>; | |
| 691 | phys = <&usb1_hsphy0>, <&usb1_hsphy1>, <&usb1_ssphy0>; | |
| 692 | dr_mode = "host"; | |
| 693 | }; | |
| 694 | ||
| 695 | usb-glue@65d00000 { | |
| 696 | compatible = "socionext,uniphier-pxs2-dwc3-glue", | |
| 697 | "simple-mfd"; | |
| 698 | #address-cells = <1>; | |
| 699 | #size-cells = <1>; | |
| 700 | ranges = <0 0x65d00000 0x400>; | |
| 701 | ||
| 702 | usb1_rst: reset@0 { | |
| 703 | compatible = "socionext,uniphier-pxs2-usb3-reset"; | |
| 704 | reg = <0x0 0x4>; | |
| 705 | #reset-cells = <1>; | |
| 706 | clock-names = "link"; | |
| 707 | clocks = <&sys_clk 15>; | |
| 708 | reset-names = "link"; | |
| 709 | resets = <&sys_rst 15>; | |
| 710 | }; | |
| 711 | ||
| 712 | usb1_vbus0: regulator@100 { | |
| 713 | compatible = "socionext,uniphier-pxs2-usb3-regulator"; | |
| 714 | reg = <0x100 0x10>; | |
| 715 | clock-names = "link"; | |
| 716 | clocks = <&sys_clk 15>; | |
| 717 | reset-names = "link"; | |
| 718 | resets = <&sys_rst 15>; | |
| 719 | }; | |
| 720 | ||
| 721 | usb1_vbus1: regulator@110 { | |
| 722 | compatible = "socionext,uniphier-pxs2-usb3-regulator"; | |
| 723 | reg = <0x110 0x10>; | |
| 724 | clock-names = "link"; | |
| 725 | clocks = <&sys_clk 15>; | |
| 726 | reset-names = "link"; | |
| 727 | resets = <&sys_rst 15>; | |
| 728 | }; | |
| 729 | ||
| 730 | usb1_hsphy0: hs-phy@200 { | |
| 731 | compatible = "socionext,uniphier-pxs2-usb3-hsphy"; | |
| 732 | reg = <0x200 0x10>; | |
| 733 | #phy-cells = <0>; | |
| 734 | clock-names = "link", "phy"; | |
| 735 | clocks = <&sys_clk 15>, <&sys_clk 20>; | |
| 736 | reset-names = "link", "phy"; | |
| 737 | resets = <&sys_rst 15>, <&sys_rst 20>; | |
| 738 | vbus-supply = <&usb1_vbus0>; | |
| 739 | }; | |
| 740 | ||
| 741 | usb1_hsphy1: hs-phy@210 { | |
| 742 | compatible = "socionext,uniphier-pxs2-usb3-hsphy"; | |
| 743 | reg = <0x210 0x10>; | |
| 744 | #phy-cells = <0>; | |
| 745 | clock-names = "link", "phy"; | |
| 746 | clocks = <&sys_clk 15>, <&sys_clk 20>; | |
| 747 | reset-names = "link", "phy"; | |
| 748 | resets = <&sys_rst 15>, <&sys_rst 20>; | |
| 749 | vbus-supply = <&usb1_vbus1>; | |
| 750 | }; | |
| 751 | ||
| 752 | usb1_ssphy0: ss-phy@300 { | |
| 753 | compatible = "socionext,uniphier-pxs2-usb3-ssphy"; | |
| 754 | reg = <0x300 0x10>; | |
| 755 | #phy-cells = <0>; | |
| 756 | clock-names = "link", "phy"; | |
| 757 | clocks = <&sys_clk 15>, <&sys_clk 21>; | |
| 758 | reset-names = "link", "phy"; | |
| 759 | resets = <&sys_rst 15>, <&sys_rst 21>; | |
| 760 | vbus-supply = <&usb1_vbus0>; | |
| 761 | }; | |
| 762 | }; | |
| 763 | ||
| 69f9cdc6 MY |
764 | nand: nand@68000000 { |
| 765 | compatible = "socionext,uniphier-denali-nand-v5b"; | |
| 766 | status = "disabled"; | |
| 767 | reg-names = "nand_data", "denali_reg"; | |
| 768 | reg = <0x68000000 0x20>, <0x68100000 0x1000>; | |
| 769 | interrupts = <0 65 4>; | |
| 770 | pinctrl-names = "default"; | |
| 771 | pinctrl-0 = <&pinctrl_nand2cs>; | |
| 007a9389 MY |
772 | clock-names = "nand", "nand_x", "ecc"; |
| 773 | clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; | |
| a1763a82 | 774 | resets = <&sys_rst 2>; |
| 69f9cdc6 | 775 | }; |
| 2752bcaa | 776 | }; |
| ad0561d4 | 777 | }; |
| 2752bcaa | 778 | |
| ed8bc76b | 779 | #include "uniphier-pinctrl.dtsi" |