projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| fce152a6 | 1 | // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| 9848ebeb JC |
2 | |
| 3 | #include <dt-bindings/gpio/gpio.h> | |
| 4 | #include <dt-bindings/interrupt-controller/irq.h> | |
| 5 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
| 6 | #include <dt-bindings/pinctrl/rockchip.h> | |
| 7 | #include <dt-bindings/clock/rk3228-cru.h> | |
| 7796031e | 8 | #include <dt-bindings/thermal/thermal.h> |
| 9848ebeb JC |
9 | |
| 10 | / { | |
| 0193273d JMC |
11 | #address-cells = <1>; |
| 12 | #size-cells = <1>; | |
| 13 | ||
| 9848ebeb JC |
14 | interrupt-parent = <&gic>; |
| 15 | ||
| 16 | aliases { | |
| 17 | serial0 = &uart0; | |
| 18 | serial1 = &uart1; | |
| 19 | serial2 = &uart2; | |
| febdf639 | 20 | spi0 = &spi0; |
| 9848ebeb JC |
21 | }; |
| 22 | ||
| 23 | cpus { | |
| 24 | #address-cells = <1>; | |
| 25 | #size-cells = <0>; | |
| 26 | ||
| 27 | cpu0: cpu@f00 { | |
| 28 | device_type = "cpu"; | |
| 29 | compatible = "arm,cortex-a7"; | |
| 30 | reg = <0xf00>; | |
| 31 | resets = <&cru SRST_CORE0>; | |
| 9f12da43 | 32 | operating-points-v2 = <&cpu0_opp_table>; |
| 7796031e | 33 | #cooling-cells = <2>; /* min followed by max */ |
| 9848ebeb JC |
34 | clock-latency = <40000>; |
| 35 | clocks = <&cru ARMCLK>; | |
| 0ae92144 | 36 | enable-method = "psci"; |
| 9848ebeb JC |
37 | }; |
| 38 | ||
| 39 | cpu1: cpu@f01 { | |
| 40 | device_type = "cpu"; | |
| 41 | compatible = "arm,cortex-a7"; | |
| 42 | reg = <0xf01>; | |
| 43 | resets = <&cru SRST_CORE1>; | |
| 9f12da43 | 44 | operating-points-v2 = <&cpu0_opp_table>; |
| 0bac06df | 45 | #cooling-cells = <2>; /* min followed by max */ |
| 0ae92144 | 46 | enable-method = "psci"; |
| 9848ebeb JC |
47 | }; |
| 48 | ||
| 49 | cpu2: cpu@f02 { | |
| 50 | device_type = "cpu"; | |
| 51 | compatible = "arm,cortex-a7"; | |
| 52 | reg = <0xf02>; | |
| 53 | resets = <&cru SRST_CORE2>; | |
| 9f12da43 | 54 | operating-points-v2 = <&cpu0_opp_table>; |
| 0bac06df | 55 | #cooling-cells = <2>; /* min followed by max */ |
| 0ae92144 | 56 | enable-method = "psci"; |
| 9848ebeb JC |
57 | }; |
| 58 | ||
| 59 | cpu3: cpu@f03 { | |
| 60 | device_type = "cpu"; | |
| 61 | compatible = "arm,cortex-a7"; | |
| 62 | reg = <0xf03>; | |
| 63 | resets = <&cru SRST_CORE3>; | |
| 9f12da43 | 64 | operating-points-v2 = <&cpu0_opp_table>; |
| 0bac06df | 65 | #cooling-cells = <2>; /* min followed by max */ |
| 0ae92144 | 66 | enable-method = "psci"; |
| 9f12da43 FX |
67 | }; |
| 68 | }; | |
| 69 | ||
| 70 | cpu0_opp_table: opp_table0 { | |
| 71 | compatible = "operating-points-v2"; | |
| 72 | opp-shared; | |
| 73 | ||
| 74 | opp-408000000 { | |
| 75 | opp-hz = /bits/ 64 <408000000>; | |
| 76 | opp-microvolt = <950000>; | |
| 77 | clock-latency-ns = <40000>; | |
| 78 | opp-suspend; | |
| 79 | }; | |
| 80 | opp-600000000 { | |
| 81 | opp-hz = /bits/ 64 <600000000>; | |
| 82 | opp-microvolt = <975000>; | |
| 83 | }; | |
| 84 | opp-816000000 { | |
| 85 | opp-hz = /bits/ 64 <816000000>; | |
| 86 | opp-microvolt = <1000000>; | |
| 87 | }; | |
| 88 | opp-1008000000 { | |
| 89 | opp-hz = /bits/ 64 <1008000000>; | |
| 90 | opp-microvolt = <1175000>; | |
| 91 | }; | |
| 92 | opp-1200000000 { | |
| 93 | opp-hz = /bits/ 64 <1200000000>; | |
| 94 | opp-microvolt = <1275000>; | |
| 9848ebeb JC |
95 | }; |
| 96 | }; | |
| 97 | ||
| 98 | amba { | |
| 2ef7d5f3 | 99 | compatible = "simple-bus"; |
| 9848ebeb JC |
100 | #address-cells = <1>; |
| 101 | #size-cells = <1>; | |
| 102 | ranges; | |
| 103 | ||
| 104 | pdma: pdma@110f0000 { | |
| 105 | compatible = "arm,pl330", "arm,primecell"; | |
| 106 | reg = <0x110f0000 0x4000>; | |
| 107 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, | |
| 108 | <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; | |
| 109 | #dma-cells = <1>; | |
| 110 | clocks = <&cru ACLK_DMAC>; | |
| 111 | clock-names = "apb_pclk"; | |
| 112 | }; | |
| 113 | }; | |
| 114 | ||
| 115 | arm-pmu { | |
| 116 | compatible = "arm,cortex-a7-pmu"; | |
| 117 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, | |
| 118 | <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, | |
| 119 | <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, | |
| 120 | <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; | |
| 121 | interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; | |
| 122 | }; | |
| 123 | ||
| 0ae92144 FW |
124 | psci { |
| 125 | compatible = "arm,psci-1.0", "arm,psci-0.2"; | |
| 126 | method = "smc"; | |
| 127 | }; | |
| 128 | ||
| 9848ebeb JC |
129 | timer { |
| 130 | compatible = "arm,armv7-timer"; | |
| 131 | arm,cpu-registers-not-fw-configured; | |
| 132 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, | |
| 133 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, | |
| 134 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, | |
| 135 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; | |
| 136 | clock-frequency = <24000000>; | |
| 137 | }; | |
| 138 | ||
| 139 | xin24m: oscillator { | |
| 140 | compatible = "fixed-clock"; | |
| 141 | clock-frequency = <24000000>; | |
| 142 | clock-output-names = "xin24m"; | |
| 143 | #clock-cells = <0>; | |
| 144 | }; | |
| 145 | ||
| ccada248 XZ |
146 | i2s1: i2s1@100b0000 { |
| 147 | compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; | |
| 148 | reg = <0x100b0000 0x4000>; | |
| 149 | interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; | |
| 150 | #address-cells = <1>; | |
| 151 | #size-cells = <0>; | |
| 152 | clock-names = "i2s_clk", "i2s_hclk"; | |
| 153 | clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; | |
| 154 | dmas = <&pdma 14>, <&pdma 15>; | |
| 155 | dma-names = "tx", "rx"; | |
| 156 | pinctrl-names = "default"; | |
| 157 | pinctrl-0 = <&i2s1_bus>; | |
| 158 | status = "disabled"; | |
| 159 | }; | |
| 160 | ||
| 161 | i2s0: i2s0@100c0000 { | |
| 162 | compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; | |
| 163 | reg = <0x100c0000 0x4000>; | |
| 164 | interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; | |
| 165 | #address-cells = <1>; | |
| 166 | #size-cells = <0>; | |
| 167 | clock-names = "i2s_clk", "i2s_hclk"; | |
| 168 | clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; | |
| 169 | dmas = <&pdma 11>, <&pdma 12>; | |
| 170 | dma-names = "tx", "rx"; | |
| 171 | status = "disabled"; | |
| 172 | }; | |
| 173 | ||
| 4b456d20 SZ |
174 | spdif: spdif@100d0000 { |
| 175 | compatible = "rockchip,rk3228-spdif"; | |
| 176 | reg = <0x100d0000 0x1000>; | |
| 177 | interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; | |
| 178 | clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>; | |
| 179 | clock-names = "mclk", "hclk"; | |
| 180 | dmas = <&pdma 10>; | |
| 181 | dma-names = "tx"; | |
| 182 | pinctrl-names = "default"; | |
| 183 | pinctrl-0 = <&spdif_tx>; | |
| 184 | status = "disabled"; | |
| 185 | }; | |
| 186 | ||
| ccada248 XZ |
187 | i2s2: i2s2@100e0000 { |
| 188 | compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; | |
| 189 | reg = <0x100e0000 0x4000>; | |
| 190 | interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; | |
| 191 | #address-cells = <1>; | |
| 192 | #size-cells = <0>; | |
| 193 | clock-names = "i2s_clk", "i2s_hclk"; | |
| 194 | clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; | |
| 195 | dmas = <&pdma 0>, <&pdma 1>; | |
| 196 | dma-names = "tx", "rx"; | |
| 197 | status = "disabled"; | |
| 198 | }; | |
| 199 | ||
| 9848ebeb | 200 | grf: syscon@11000000 { |
| 692f492f | 201 | compatible = "rockchip,rk3228-grf", "syscon", "simple-mfd"; |
| 9848ebeb | 202 | reg = <0x11000000 0x1000>; |
| 3880af45 WW |
203 | #address-cells = <1>; |
| 204 | #size-cells = <1>; | |
| 205 | ||
| 83086adf DW |
206 | io_domains: io-domains { |
| 207 | compatible = "rockchip,rk3228-io-voltage-domain"; | |
| 208 | status = "disabled"; | |
| 209 | }; | |
| 210 | ||
| 3880af45 WW |
211 | u2phy0: usb2-phy@760 { |
| 212 | compatible = "rockchip,rk3228-usb2phy"; | |
| 213 | reg = <0x0760 0x0c>; | |
| 214 | clocks = <&cru SCLK_OTGPHY0>; | |
| 215 | clock-names = "phyclk"; | |
| 216 | clock-output-names = "usb480m_phy0"; | |
| 217 | #clock-cells = <0>; | |
| 218 | status = "disabled"; | |
| 219 | ||
| 220 | u2phy0_otg: otg-port { | |
| 221 | interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, | |
| 222 | <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, | |
| 223 | <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; | |
| 224 | interrupt-names = "otg-bvalid", "otg-id", | |
| 225 | "linestate"; | |
| 226 | #phy-cells = <0>; | |
| 227 | status = "disabled"; | |
| 228 | }; | |
| 229 | ||
| 230 | u2phy0_host: host-port { | |
| 231 | interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; | |
| 232 | interrupt-names = "linestate"; | |
| 233 | #phy-cells = <0>; | |
| 234 | status = "disabled"; | |
| 235 | }; | |
| 236 | }; | |
| 237 | ||
| 238 | u2phy1: usb2-phy@800 { | |
| 239 | compatible = "rockchip,rk3228-usb2phy"; | |
| 240 | reg = <0x0800 0x0c>; | |
| 241 | clocks = <&cru SCLK_OTGPHY1>; | |
| 242 | clock-names = "phyclk"; | |
| 243 | clock-output-names = "usb480m_phy1"; | |
| 244 | #clock-cells = <0>; | |
| 245 | status = "disabled"; | |
| 246 | ||
| 247 | u2phy1_otg: otg-port { | |
| 248 | interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; | |
| 249 | interrupt-names = "linestate"; | |
| 250 | #phy-cells = <0>; | |
| 251 | status = "disabled"; | |
| 252 | }; | |
| 253 | ||
| 254 | u2phy1_host: host-port { | |
| 255 | interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; | |
| 256 | interrupt-names = "linestate"; | |
| 257 | #phy-cells = <0>; | |
| 258 | status = "disabled"; | |
| 259 | }; | |
| 260 | }; | |
| 9848ebeb JC |
261 | }; |
| 262 | ||
| 263 | uart0: serial@11010000 { | |
| 264 | compatible = "snps,dw-apb-uart"; | |
| 265 | reg = <0x11010000 0x100>; | |
| 266 | interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; | |
| 267 | clock-frequency = <24000000>; | |
| 268 | clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; | |
| 269 | clock-names = "baudclk", "apb_pclk"; | |
| 270 | pinctrl-names = "default"; | |
| 271 | pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; | |
| 272 | reg-shift = <2>; | |
| 273 | reg-io-width = <4>; | |
| 274 | status = "disabled"; | |
| 275 | }; | |
| 276 | ||
| 277 | uart1: serial@11020000 { | |
| 278 | compatible = "snps,dw-apb-uart"; | |
| 279 | reg = <0x11020000 0x100>; | |
| 280 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; | |
| 281 | clock-frequency = <24000000>; | |
| 282 | clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; | |
| 283 | clock-names = "baudclk", "apb_pclk"; | |
| 284 | pinctrl-names = "default"; | |
| 285 | pinctrl-0 = <&uart1_xfer>; | |
| 286 | reg-shift = <2>; | |
| 287 | reg-io-width = <4>; | |
| 288 | status = "disabled"; | |
| 289 | }; | |
| 290 | ||
| 291 | uart2: serial@11030000 { | |
| 292 | compatible = "snps,dw-apb-uart"; | |
| 293 | reg = <0x11030000 0x100>; | |
| 294 | interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; | |
| 295 | clock-frequency = <24000000>; | |
| 296 | clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; | |
| 297 | clock-names = "baudclk", "apb_pclk"; | |
| 298 | pinctrl-names = "default"; | |
| 299 | pinctrl-0 = <&uart2_xfer>; | |
| 300 | reg-shift = <2>; | |
| 301 | reg-io-width = <4>; | |
| 302 | status = "disabled"; | |
| 303 | }; | |
| 304 | ||
| 9098be63 FX |
305 | efuse: efuse@11040000 { |
| 306 | compatible = "rockchip,rk3228-efuse"; | |
| 307 | reg = <0x11040000 0x20>; | |
| 308 | clocks = <&cru PCLK_EFUSE_256>; | |
| 309 | clock-names = "pclk_efuse"; | |
| 310 | #address-cells = <1>; | |
| 311 | #size-cells = <1>; | |
| 312 | ||
| 313 | /* Data cells */ | |
| 314 | efuse_id: id@7 { | |
| 315 | reg = <0x7 0x10>; | |
| 316 | }; | |
| 317 | cpu_leakage: cpu_leakage@17 { | |
| 318 | reg = <0x17 0x1>; | |
| 319 | }; | |
| 320 | }; | |
| 321 | ||
| d549df4b YY |
322 | i2c0: i2c@11050000 { |
| 323 | compatible = "rockchip,rk3228-i2c"; | |
| 324 | reg = <0x11050000 0x1000>; | |
| 325 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; | |
| 326 | #address-cells = <1>; | |
| 327 | #size-cells = <0>; | |
| 328 | clock-names = "i2c"; | |
| 329 | clocks = <&cru PCLK_I2C0>; | |
| 330 | pinctrl-names = "default"; | |
| 331 | pinctrl-0 = <&i2c0_xfer>; | |
| 332 | status = "disabled"; | |
| 333 | }; | |
| 334 | ||
| 335 | i2c1: i2c@11060000 { | |
| 336 | compatible = "rockchip,rk3228-i2c"; | |
| 337 | reg = <0x11060000 0x1000>; | |
| 338 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; | |
| 339 | #address-cells = <1>; | |
| 340 | #size-cells = <0>; | |
| 341 | clock-names = "i2c"; | |
| 342 | clocks = <&cru PCLK_I2C1>; | |
| 343 | pinctrl-names = "default"; | |
| 344 | pinctrl-0 = <&i2c1_xfer>; | |
| 345 | status = "disabled"; | |
| 346 | }; | |
| 347 | ||
| 348 | i2c2: i2c@11070000 { | |
| 349 | compatible = "rockchip,rk3228-i2c"; | |
| 350 | reg = <0x11070000 0x1000>; | |
| 351 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; | |
| 352 | #address-cells = <1>; | |
| 353 | #size-cells = <0>; | |
| 354 | clock-names = "i2c"; | |
| 355 | clocks = <&cru PCLK_I2C2>; | |
| 356 | pinctrl-names = "default"; | |
| 357 | pinctrl-0 = <&i2c2_xfer>; | |
| 358 | status = "disabled"; | |
| 359 | }; | |
| 360 | ||
| 361 | i2c3: i2c@11080000 { | |
| 362 | compatible = "rockchip,rk3228-i2c"; | |
| 363 | reg = <0x11080000 0x1000>; | |
| 364 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; | |
| 365 | #address-cells = <1>; | |
| 366 | #size-cells = <0>; | |
| 367 | clock-names = "i2c"; | |
| 368 | clocks = <&cru PCLK_I2C3>; | |
| 369 | pinctrl-names = "default"; | |
| 370 | pinctrl-0 = <&i2c3_xfer>; | |
| 371 | status = "disabled"; | |
| 372 | }; | |
| 373 | ||
| febdf639 HH |
374 | spi0: spi@11090000 { |
| 375 | compatible = "rockchip,rk3228-spi"; | |
| 376 | reg = <0x11090000 0x1000>; | |
| 377 | interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; | |
| 378 | #address-cells = <1>; | |
| 379 | #size-cells = <0>; | |
| 380 | clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; | |
| 381 | clock-names = "spiclk", "apb_pclk"; | |
| 382 | pinctrl-names = "default"; | |
| 383 | pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>; | |
| 384 | status = "disabled"; | |
| 385 | }; | |
| 386 | ||
| fa206984 FW |
387 | wdt: watchdog@110a0000 { |
| 388 | compatible = "snps,dw-wdt"; | |
| 389 | reg = <0x110a0000 0x100>; | |
| 390 | interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; | |
| 391 | clocks = <&cru PCLK_CPU>; | |
| 392 | status = "disabled"; | |
| 393 | }; | |
| 394 | ||
| 9848ebeb JC |
395 | pwm0: pwm@110b0000 { |
| 396 | compatible = "rockchip,rk3288-pwm"; | |
| 397 | reg = <0x110b0000 0x10>; | |
| 398 | #pwm-cells = <3>; | |
| 399 | clocks = <&cru PCLK_PWM>; | |
| 400 | clock-names = "pwm"; | |
| 401 | pinctrl-names = "default"; | |
| 402 | pinctrl-0 = <&pwm0_pin>; | |
| 403 | status = "disabled"; | |
| 404 | }; | |
| 405 | ||
| 406 | pwm1: pwm@110b0010 { | |
| 407 | compatible = "rockchip,rk3288-pwm"; | |
| 408 | reg = <0x110b0010 0x10>; | |
| 409 | #pwm-cells = <3>; | |
| 410 | clocks = <&cru PCLK_PWM>; | |
| 411 | clock-names = "pwm"; | |
| 412 | pinctrl-names = "default"; | |
| 413 | pinctrl-0 = <&pwm1_pin>; | |
| 414 | status = "disabled"; | |
| 415 | }; | |
| 416 | ||
| 417 | pwm2: pwm@110b0020 { | |
| 418 | compatible = "rockchip,rk3288-pwm"; | |
| 419 | reg = <0x110b0020 0x10>; | |
| 420 | #pwm-cells = <3>; | |
| 421 | clocks = <&cru PCLK_PWM>; | |
| 422 | clock-names = "pwm"; | |
| 423 | pinctrl-names = "default"; | |
| 424 | pinctrl-0 = <&pwm2_pin>; | |
| 425 | status = "disabled"; | |
| 426 | }; | |
| 427 | ||
| 428 | pwm3: pwm@110b0030 { | |
| 429 | compatible = "rockchip,rk3288-pwm"; | |
| 430 | reg = <0x110b0030 0x10>; | |
| 431 | #pwm-cells = <2>; | |
| 432 | clocks = <&cru PCLK_PWM>; | |
| 433 | clock-names = "pwm"; | |
| 434 | pinctrl-names = "default"; | |
| 435 | pinctrl-0 = <&pwm3_pin>; | |
| 436 | status = "disabled"; | |
| 437 | }; | |
| 438 | ||
| 439 | timer: timer@110c0000 { | |
| b72af346 | 440 | compatible = "rockchip,rk3228-timer", "rockchip,rk3288-timer"; |
| 9848ebeb JC |
441 | reg = <0x110c0000 0x20>; |
| 442 | interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; | |
| 443 | clocks = <&xin24m>, <&cru PCLK_TIMER>; | |
| 444 | clock-names = "timer", "pclk"; | |
| 445 | }; | |
| 446 | ||
| 447 | cru: clock-controller@110e0000 { | |
| 448 | compatible = "rockchip,rk3228-cru"; | |
| 449 | reg = <0x110e0000 0x1000>; | |
| 450 | rockchip,grf = <&grf>; | |
| 451 | #clock-cells = <1>; | |
| 452 | #reset-cells = <1>; | |
| 30ee5814 EZ |
453 | assigned-clocks = |
| 454 | <&cru PLL_GPLL>, <&cru ARMCLK>, | |
| 455 | <&cru PLL_CPLL>, <&cru ACLK_PERI>, | |
| 456 | <&cru HCLK_PERI>, <&cru PCLK_PERI>, | |
| 457 | <&cru ACLK_CPU>, <&cru HCLK_CPU>, | |
| 458 | <&cru PCLK_CPU>; | |
| 459 | assigned-clock-rates = | |
| 460 | <594000000>, <816000000>, | |
| 461 | <500000000>, <150000000>, | |
| 462 | <150000000>, <75000000>, | |
| 463 | <150000000>, <150000000>, | |
| 464 | <75000000>; | |
| 9848ebeb JC |
465 | }; |
| 466 | ||
| 7796031e CW |
467 | thermal-zones { |
| 468 | cpu_thermal: cpu-thermal { | |
| 469 | polling-delay-passive = <100>; /* milliseconds */ | |
| 470 | polling-delay = <5000>; /* milliseconds */ | |
| 471 | ||
| 472 | thermal-sensors = <&tsadc 0>; | |
| 473 | ||
| 474 | trips { | |
| 475 | cpu_alert0: cpu_alert0 { | |
| 476 | temperature = <70000>; /* millicelsius */ | |
| 477 | hysteresis = <2000>; /* millicelsius */ | |
| 478 | type = "passive"; | |
| 479 | }; | |
| 480 | cpu_alert1: cpu_alert1 { | |
| 481 | temperature = <75000>; /* millicelsius */ | |
| 482 | hysteresis = <2000>; /* millicelsius */ | |
| 483 | type = "passive"; | |
| 484 | }; | |
| 485 | cpu_crit: cpu_crit { | |
| 486 | temperature = <90000>; /* millicelsius */ | |
| 487 | hysteresis = <2000>; /* millicelsius */ | |
| 488 | type = "critical"; | |
| 489 | }; | |
| 490 | }; | |
| 491 | ||
| 492 | cooling-maps { | |
| 493 | map0 { | |
| 494 | trip = <&cpu_alert0>; | |
| 495 | cooling-device = | |
| 99935bd4 VK |
496 | <&cpu0 THERMAL_NO_LIMIT 6>, |
| 497 | <&cpu1 THERMAL_NO_LIMIT 6>, | |
| 498 | <&cpu2 THERMAL_NO_LIMIT 6>, | |
| 499 | <&cpu3 THERMAL_NO_LIMIT 6>; | |
| 7796031e CW |
500 | }; |
| 501 | map1 { | |
| 502 | trip = <&cpu_alert1>; | |
| 503 | cooling-device = | |
| 99935bd4 VK |
504 | <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| 505 | <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 506 | <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 507 | <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
| 7796031e CW |
508 | }; |
| 509 | }; | |
| 510 | }; | |
| 511 | }; | |
| 512 | ||
| 513 | tsadc: tsadc@11150000 { | |
| 514 | compatible = "rockchip,rk3228-tsadc"; | |
| 515 | reg = <0x11150000 0x100>; | |
| 516 | interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; | |
| 517 | clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; | |
| 518 | clock-names = "tsadc", "apb_pclk"; | |
| 2b3f2f37 RH |
519 | assigned-clocks = <&cru SCLK_TSADC>; |
| 520 | assigned-clock-rates = <32768>; | |
| 7796031e CW |
521 | resets = <&cru SRST_TSADC>; |
| 522 | reset-names = "tsadc-apb"; | |
| 523 | pinctrl-names = "init", "default", "sleep"; | |
| 524 | pinctrl-0 = <&otp_gpio>; | |
| 525 | pinctrl-1 = <&otp_out>; | |
| 526 | pinctrl-2 = <&otp_gpio>; | |
| 527 | #thermal-sensor-cells = <0>; | |
| 528 | rockchip,hw-tshut-temp = <95000>; | |
| 529 | status = "disabled"; | |
| 530 | }; | |
| 531 | ||
| 451ef43b HS |
532 | gpu: gpu@20000000 { |
| 533 | compatible = "rockchip,rk3228-mali", "arm,mali-400"; | |
| 534 | reg = <0x20000000 0x10000>; | |
| 535 | interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, | |
| 536 | <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, | |
| 537 | <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, | |
| 538 | <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, | |
| 539 | <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, | |
| 540 | <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; | |
| 541 | interrupt-names = "gp", | |
| 542 | "gpmmu", | |
| 543 | "pp0", | |
| 0133c492 | 544 | "ppmmu0", |
| 451ef43b | 545 | "pp1", |
| 0133c492 | 546 | "ppmmu1"; |
| 451ef43b HS |
547 | clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; |
| 548 | clock-names = "core", "bus"; | |
| 549 | resets = <&cru SRST_GPU_A>; | |
| 550 | status = "disabled"; | |
| 551 | }; | |
| 552 | ||
| 4e1b222d SX |
553 | vpu_mmu: iommu@20020800 { |
| 554 | compatible = "rockchip,iommu"; | |
| 555 | reg = <0x20020800 0x100>; | |
| 556 | interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; | |
| 557 | interrupt-names = "vpu_mmu"; | |
| c78751f9 JC |
558 | clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; |
| 559 | clock-names = "aclk", "iface"; | |
| 4e1b222d SX |
560 | iommu-cells = <0>; |
| 561 | status = "disabled"; | |
| 562 | }; | |
| 563 | ||
| 564 | vdec_mmu: iommu@20030480 { | |
| 565 | compatible = "rockchip,iommu"; | |
| 566 | reg = <0x20030480 0x40>, <0x200304c0 0x40>; | |
| 567 | interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; | |
| 568 | interrupt-names = "vdec_mmu"; | |
| c78751f9 JC |
569 | clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; |
| 570 | clock-names = "aclk", "iface"; | |
| 4e1b222d SX |
571 | iommu-cells = <0>; |
| 572 | status = "disabled"; | |
| 573 | }; | |
| 574 | ||
| 575 | vop_mmu: iommu@20053f00 { | |
| 576 | compatible = "rockchip,iommu"; | |
| 577 | reg = <0x20053f00 0x100>; | |
| 578 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; | |
| 579 | interrupt-names = "vop_mmu"; | |
| c78751f9 JC |
580 | clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; |
| 581 | clock-names = "aclk", "iface"; | |
| 4e1b222d SX |
582 | iommu-cells = <0>; |
| 583 | status = "disabled"; | |
| 584 | }; | |
| 585 | ||
| 586 | iep_mmu: iommu@20070800 { | |
| 587 | compatible = "rockchip,iommu"; | |
| 588 | reg = <0x20070800 0x100>; | |
| 589 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; | |
| 590 | interrupt-names = "iep_mmu"; | |
| c78751f9 JC |
591 | clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; |
| 592 | clock-names = "aclk", "iface"; | |
| 4e1b222d SX |
593 | iommu-cells = <0>; |
| 594 | status = "disabled"; | |
| 595 | }; | |
| 596 | ||
| e409fc3d SL |
597 | sdmmc: dwmmc@30000000 { |
| 598 | compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; | |
| 599 | reg = <0x30000000 0x4000>; | |
| 600 | interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; | |
| 601 | clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, | |
| 602 | <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; | |
| e78c6371 | 603 | clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; |
| e409fc3d SL |
604 | fifo-depth = <0x100>; |
| 605 | pinctrl-names = "default"; | |
| 606 | pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; | |
| 607 | status = "disabled"; | |
| 608 | }; | |
| 609 | ||
| 610 | sdio: dwmmc@30010000 { | |
| 611 | compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; | |
| 612 | reg = <0x30010000 0x4000>; | |
| 613 | interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; | |
| 614 | clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, | |
| 615 | <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; | |
| e78c6371 | 616 | clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; |
| e409fc3d SL |
617 | fifo-depth = <0x100>; |
| 618 | pinctrl-names = "default"; | |
| 619 | pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>; | |
| 620 | status = "disabled"; | |
| 621 | }; | |
| 622 | ||
| 9848ebeb | 623 | emmc: dwmmc@30020000 { |
| 0d6a01f8 | 624 | compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; |
| 9848ebeb JC |
625 | reg = <0x30020000 0x4000>; |
| 626 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; | |
| 627 | clock-frequency = <37500000>; | |
| 6a8883d6 | 628 | max-frequency = <37500000>; |
| 9848ebeb JC |
629 | clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, |
| 630 | <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; | |
| e78c6371 | 631 | clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; |
| 9848ebeb JC |
632 | bus-width = <8>; |
| 633 | default-sample-phase = <158>; | |
| 9848ebeb JC |
634 | fifo-depth = <0x100>; |
| 635 | pinctrl-names = "default"; | |
| 636 | pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; | |
| 2d1f1d4c HS |
637 | resets = <&cru SRST_EMMC>; |
| 638 | reset-names = "reset"; | |
| 9848ebeb JC |
639 | status = "disabled"; |
| 640 | }; | |
| 641 | ||
| 3880af45 WW |
642 | usb_otg: usb@30040000 { |
| 643 | compatible = "rockchip,rk3228-usb", "rockchip,rk3066-usb", | |
| 644 | "snps,dwc2"; | |
| 645 | reg = <0x30040000 0x40000>; | |
| 646 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; | |
| 647 | clocks = <&cru HCLK_OTG>; | |
| 648 | clock-names = "otg"; | |
| 649 | dr_mode = "otg"; | |
| 650 | g-np-tx-fifo-size = <16>; | |
| 651 | g-rx-fifo-size = <280>; | |
| 652 | g-tx-fifo-size = <256 128 128 64 32 16>; | |
| 653 | g-use-dma; | |
| 654 | phys = <&u2phy0_otg>; | |
| 655 | phy-names = "usb2-phy"; | |
| 656 | status = "disabled"; | |
| 657 | }; | |
| 658 | ||
| 659 | usb_host0_ehci: usb@30080000 { | |
| 660 | compatible = "generic-ehci"; | |
| 661 | reg = <0x30080000 0x20000>; | |
| 662 | interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; | |
| 663 | clocks = <&cru HCLK_HOST0>, <&u2phy0>; | |
| 664 | clock-names = "usbhost", "utmi"; | |
| 665 | phys = <&u2phy0_host>; | |
| 666 | phy-names = "usb"; | |
| 667 | status = "disabled"; | |
| 668 | }; | |
| 669 | ||
| 670 | usb_host0_ohci: usb@300a0000 { | |
| 671 | compatible = "generic-ohci"; | |
| 672 | reg = <0x300a0000 0x20000>; | |
| 673 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; | |
| 674 | clocks = <&cru HCLK_HOST0>, <&u2phy0>; | |
| 675 | clock-names = "usbhost", "utmi"; | |
| 676 | phys = <&u2phy0_host>; | |
| 677 | phy-names = "usb"; | |
| 678 | status = "disabled"; | |
| 679 | }; | |
| 680 | ||
| 681 | usb_host1_ehci: usb@300c0000 { | |
| 682 | compatible = "generic-ehci"; | |
| 683 | reg = <0x300c0000 0x20000>; | |
| 684 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; | |
| 685 | clocks = <&cru HCLK_HOST1>, <&u2phy1>; | |
| 686 | clock-names = "usbhost", "utmi"; | |
| 687 | phys = <&u2phy1_otg>; | |
| 688 | phy-names = "usb"; | |
| 689 | status = "disabled"; | |
| 690 | }; | |
| 691 | ||
| 692 | usb_host1_ohci: usb@300e0000 { | |
| 693 | compatible = "generic-ohci"; | |
| 694 | reg = <0x300e0000 0x20000>; | |
| 695 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; | |
| 696 | clocks = <&cru HCLK_HOST1>, <&u2phy1>; | |
| 697 | clock-names = "usbhost", "utmi"; | |
| 698 | phys = <&u2phy1_otg>; | |
| 699 | phy-names = "usb"; | |
| 700 | status = "disabled"; | |
| 701 | }; | |
| 702 | ||
| 703 | usb_host2_ehci: usb@30100000 { | |
| 704 | compatible = "generic-ehci"; | |
| 705 | reg = <0x30100000 0x20000>; | |
| 706 | interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; | |
| 707 | clocks = <&cru HCLK_HOST2>, <&u2phy1>; | |
| 708 | phys = <&u2phy1_host>; | |
| 709 | phy-names = "usb"; | |
| 710 | clock-names = "usbhost", "utmi"; | |
| 711 | status = "disabled"; | |
| 712 | }; | |
| 713 | ||
| 714 | usb_host2_ohci: usb@30120000 { | |
| 715 | compatible = "generic-ohci"; | |
| 716 | reg = <0x30120000 0x20000>; | |
| 717 | interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; | |
| 718 | clocks = <&cru HCLK_HOST2>, <&u2phy1>; | |
| 719 | clock-names = "usbhost", "utmi"; | |
| 720 | phys = <&u2phy1_host>; | |
| 721 | phy-names = "usb"; | |
| 722 | status = "disabled"; | |
| 723 | }; | |
| 724 | ||
| 5d3d7c72 XZ |
725 | gmac: ethernet@30200000 { |
| 726 | compatible = "rockchip,rk3228-gmac"; | |
| 727 | reg = <0x30200000 0x10000>; | |
| 728 | interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; | |
| 729 | interrupt-names = "macirq"; | |
| 730 | clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, | |
| 731 | <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>, | |
| 732 | <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>, | |
| 733 | <&cru PCLK_GMAC>; | |
| 734 | clock-names = "stmmaceth", "mac_clk_rx", | |
| 735 | "mac_clk_tx", "clk_mac_ref", | |
| 736 | "clk_mac_refout", "aclk_mac", | |
| 737 | "pclk_mac"; | |
| 738 | resets = <&cru SRST_GMAC>; | |
| 739 | reset-names = "stmmaceth"; | |
| 740 | rockchip,grf = <&grf>; | |
| 741 | status = "disabled"; | |
| 742 | }; | |
| 743 | ||
| 9848ebeb JC |
744 | gic: interrupt-controller@32010000 { |
| 745 | compatible = "arm,gic-400"; | |
| 746 | interrupt-controller; | |
| 747 | #interrupt-cells = <3>; | |
| 748 | #address-cells = <0>; | |
| 749 | ||
| 750 | reg = <0x32011000 0x1000>, | |
| 387720c9 | 751 | <0x32012000 0x2000>, |
| 9848ebeb JC |
752 | <0x32014000 0x2000>, |
| 753 | <0x32016000 0x2000>; | |
| 754 | interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; | |
| 755 | }; | |
| 756 | ||
| 757 | pinctrl: pinctrl { | |
| 758 | compatible = "rockchip,rk3228-pinctrl"; | |
| 759 | rockchip,grf = <&grf>; | |
| 760 | #address-cells = <1>; | |
| 761 | #size-cells = <1>; | |
| 762 | ranges; | |
| 763 | ||
| 764 | gpio0: gpio0@11110000 { | |
| 765 | compatible = "rockchip,gpio-bank"; | |
| 766 | reg = <0x11110000 0x100>; | |
| 767 | interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; | |
| 768 | clocks = <&cru PCLK_GPIO0>; | |
| 769 | ||
| 770 | gpio-controller; | |
| 771 | #gpio-cells = <2>; | |
| 772 | ||
| 773 | interrupt-controller; | |
| 774 | #interrupt-cells = <2>; | |
| 775 | }; | |
| 776 | ||
| 777 | gpio1: gpio1@11120000 { | |
| 778 | compatible = "rockchip,gpio-bank"; | |
| 779 | reg = <0x11120000 0x100>; | |
| 780 | interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; | |
| 781 | clocks = <&cru PCLK_GPIO1>; | |
| 782 | ||
| 783 | gpio-controller; | |
| 784 | #gpio-cells = <2>; | |
| 785 | ||
| 786 | interrupt-controller; | |
| 787 | #interrupt-cells = <2>; | |
| 788 | }; | |
| 789 | ||
| 790 | gpio2: gpio2@11130000 { | |
| 791 | compatible = "rockchip,gpio-bank"; | |
| 792 | reg = <0x11130000 0x100>; | |
| 793 | interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; | |
| 794 | clocks = <&cru PCLK_GPIO2>; | |
| 795 | ||
| 796 | gpio-controller; | |
| 797 | #gpio-cells = <2>; | |
| 798 | ||
| 799 | interrupt-controller; | |
| 800 | #interrupt-cells = <2>; | |
| 801 | }; | |
| 802 | ||
| 803 | gpio3: gpio3@11140000 { | |
| 804 | compatible = "rockchip,gpio-bank"; | |
| 805 | reg = <0x11140000 0x100>; | |
| 806 | interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; | |
| 807 | clocks = <&cru PCLK_GPIO3>; | |
| 808 | ||
| 809 | gpio-controller; | |
| 810 | #gpio-cells = <2>; | |
| 811 | ||
| 812 | interrupt-controller; | |
| 813 | #interrupt-cells = <2>; | |
| 814 | }; | |
| 815 | ||
| 816 | pcfg_pull_up: pcfg-pull-up { | |
| 817 | bias-pull-up; | |
| 818 | }; | |
| 819 | ||
| 820 | pcfg_pull_down: pcfg-pull-down { | |
| 821 | bias-pull-down; | |
| 822 | }; | |
| 823 | ||
| 824 | pcfg_pull_none: pcfg-pull-none { | |
| 825 | bias-disable; | |
| 826 | }; | |
| 827 | ||
| 5d3d7c72 XZ |
828 | pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma { |
| 829 | drive-strength = <12>; | |
| 830 | }; | |
| 831 | ||
| e409fc3d SL |
832 | sdmmc { |
| 833 | sdmmc_clk: sdmmc-clk { | |
| 834 | rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none_drv_12ma>; | |
| 835 | }; | |
| 836 | ||
| 837 | sdmmc_cmd: sdmmc-cmd { | |
| 838 | rockchip,pins = <1 RK_PB7 1 &pcfg_pull_none_drv_12ma>; | |
| 839 | }; | |
| 840 | ||
| 841 | sdmmc_bus4: sdmmc-bus4 { | |
| 842 | rockchip,pins = <1 RK_PC2 1 &pcfg_pull_none_drv_12ma>, | |
| 843 | <1 RK_PC3 1 &pcfg_pull_none_drv_12ma>, | |
| 844 | <1 RK_PC4 1 &pcfg_pull_none_drv_12ma>, | |
| 845 | <1 RK_PC5 1 &pcfg_pull_none_drv_12ma>; | |
| 846 | }; | |
| 847 | }; | |
| 848 | ||
| 849 | sdio { | |
| 850 | sdio_clk: sdio-clk { | |
| 851 | rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none_drv_12ma>; | |
| 852 | }; | |
| 853 | ||
| 854 | sdio_cmd: sdio-cmd { | |
| 855 | rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none_drv_12ma>; | |
| 856 | }; | |
| 857 | ||
| 858 | sdio_bus4: sdio-bus4 { | |
| 859 | rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none_drv_12ma>, | |
| 860 | <3 RK_PA3 1 &pcfg_pull_none_drv_12ma>, | |
| 861 | <3 RK_PA4 1 &pcfg_pull_none_drv_12ma>, | |
| 862 | <3 RK_PA5 1 &pcfg_pull_none_drv_12ma>; | |
| 863 | }; | |
| 864 | }; | |
| 865 | ||
| 9848ebeb JC |
866 | emmc { |
| 867 | emmc_clk: emmc-clk { | |
| 868 | rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>; | |
| 869 | }; | |
| 870 | ||
| 871 | emmc_cmd: emmc-cmd { | |
| 872 | rockchip,pins = <1 22 RK_FUNC_2 &pcfg_pull_none>; | |
| 873 | }; | |
| 874 | ||
| 875 | emmc_bus8: emmc-bus8 { | |
| 876 | rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>, | |
| 877 | <1 25 RK_FUNC_2 &pcfg_pull_none>, | |
| 878 | <1 26 RK_FUNC_2 &pcfg_pull_none>, | |
| 879 | <1 27 RK_FUNC_2 &pcfg_pull_none>, | |
| 880 | <1 28 RK_FUNC_2 &pcfg_pull_none>, | |
| 881 | <1 29 RK_FUNC_2 &pcfg_pull_none>, | |
| 882 | <1 30 RK_FUNC_2 &pcfg_pull_none>, | |
| 883 | <1 31 RK_FUNC_2 &pcfg_pull_none>; | |
| 884 | }; | |
| 885 | }; | |
| 886 | ||
| 5d3d7c72 XZ |
887 | gmac { |
| 888 | rgmii_pins: rgmii-pins { | |
| 889 | rockchip,pins = <2 14 RK_FUNC_1 &pcfg_pull_none>, | |
| 890 | <2 12 RK_FUNC_1 &pcfg_pull_none>, | |
| 891 | <2 25 RK_FUNC_1 &pcfg_pull_none>, | |
| 892 | <2 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, | |
| 893 | <2 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, | |
| 894 | <2 22 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, | |
| 895 | <2 23 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, | |
| 896 | <2 9 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, | |
| 897 | <2 13 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, | |
| 898 | <2 17 RK_FUNC_1 &pcfg_pull_none>, | |
| 899 | <2 16 RK_FUNC_1 &pcfg_pull_none>, | |
| 900 | <2 21 RK_FUNC_2 &pcfg_pull_none>, | |
| 901 | <2 20 RK_FUNC_2 &pcfg_pull_none>, | |
| 902 | <2 11 RK_FUNC_1 &pcfg_pull_none>, | |
| 903 | <2 8 RK_FUNC_1 &pcfg_pull_none>; | |
| 904 | }; | |
| 905 | ||
| 906 | rmii_pins: rmii-pins { | |
| 907 | rockchip,pins = <2 14 RK_FUNC_1 &pcfg_pull_none>, | |
| 908 | <2 12 RK_FUNC_1 &pcfg_pull_none>, | |
| 909 | <2 25 RK_FUNC_1 &pcfg_pull_none>, | |
| 910 | <2 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, | |
| 911 | <2 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, | |
| 912 | <2 13 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, | |
| 913 | <2 17 RK_FUNC_1 &pcfg_pull_none>, | |
| 914 | <2 16 RK_FUNC_1 &pcfg_pull_none>, | |
| 915 | <2 8 RK_FUNC_1 &pcfg_pull_none>, | |
| 916 | <2 15 RK_FUNC_1 &pcfg_pull_none>; | |
| 917 | }; | |
| 918 | ||
| 919 | phy_pins: phy-pins { | |
| 920 | rockchip,pins = <2 14 RK_FUNC_2 &pcfg_pull_none>, | |
| 921 | <2 8 RK_FUNC_2 &pcfg_pull_none>; | |
| 922 | }; | |
| 923 | }; | |
| 924 | ||
| d549df4b YY |
925 | i2c0 { |
| 926 | i2c0_xfer: i2c0-xfer { | |
| 927 | rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>, | |
| 928 | <0 1 RK_FUNC_1 &pcfg_pull_none>; | |
| 929 | }; | |
| 930 | }; | |
| 931 | ||
| 932 | i2c1 { | |
| 933 | i2c1_xfer: i2c1-xfer { | |
| 934 | rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>, | |
| 935 | <0 3 RK_FUNC_1 &pcfg_pull_none>; | |
| 936 | }; | |
| 937 | }; | |
| 938 | ||
| 939 | i2c2 { | |
| 940 | i2c2_xfer: i2c2-xfer { | |
| 941 | rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>, | |
| 942 | <2 21 RK_FUNC_1 &pcfg_pull_none>; | |
| 943 | }; | |
| 944 | }; | |
| 945 | ||
| 946 | i2c3 { | |
| 947 | i2c3_xfer: i2c3-xfer { | |
| 948 | rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>, | |
| 949 | <0 7 RK_FUNC_1 &pcfg_pull_none>; | |
| 950 | }; | |
| 951 | }; | |
| 952 | ||
| febdf639 HH |
953 | spi-0 { |
| 954 | spi0_clk: spi0-clk { | |
| 955 | rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_up>; | |
| 956 | }; | |
| 957 | spi0_cs0: spi0-cs0 { | |
| 958 | rockchip,pins = <0 14 RK_FUNC_2 &pcfg_pull_up>; | |
| 959 | }; | |
| 960 | spi0_tx: spi0-tx { | |
| 961 | rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>; | |
| 962 | }; | |
| 963 | spi0_rx: spi0-rx { | |
| 964 | rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>; | |
| 965 | }; | |
| 966 | spi0_cs1: spi0-cs1 { | |
| 967 | rockchip,pins = <1 12 RK_FUNC_1 &pcfg_pull_up>; | |
| 968 | }; | |
| 969 | }; | |
| 970 | ||
| 971 | spi-1 { | |
| 972 | spi1_clk: spi1-clk { | |
| 973 | rockchip,pins = <0 23 RK_FUNC_2 &pcfg_pull_up>; | |
| 974 | }; | |
| 975 | spi1_cs0: spi1-cs0 { | |
| 976 | rockchip,pins = <2 2 RK_FUNC_2 &pcfg_pull_up>; | |
| 977 | }; | |
| 978 | spi1_rx: spi1-rx { | |
| 979 | rockchip,pins = <2 0 RK_FUNC_2 &pcfg_pull_up>; | |
| 980 | }; | |
| 981 | spi1_tx: spi1-tx { | |
| 982 | rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_up>; | |
| 983 | }; | |
| 984 | spi1_cs1: spi1-cs1 { | |
| 985 | rockchip,pins = <2 3 RK_FUNC_2 &pcfg_pull_up>; | |
| 986 | }; | |
| 987 | }; | |
| 988 | ||
| ccada248 XZ |
989 | i2s1 { |
| 990 | i2s1_bus: i2s1-bus { | |
| 991 | rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_none>, | |
| 992 | <0 9 RK_FUNC_1 &pcfg_pull_none>, | |
| 993 | <0 11 RK_FUNC_1 &pcfg_pull_none>, | |
| 994 | <0 12 RK_FUNC_1 &pcfg_pull_none>, | |
| 995 | <0 13 RK_FUNC_1 &pcfg_pull_none>, | |
| 996 | <0 14 RK_FUNC_1 &pcfg_pull_none>, | |
| 9d420e9b SZ |
997 | <1 2 RK_FUNC_2 &pcfg_pull_none>, |
| 998 | <1 4 RK_FUNC_2 &pcfg_pull_none>, | |
| 999 | <1 5 RK_FUNC_2 &pcfg_pull_none>; | |
| ccada248 XZ |
1000 | }; |
| 1001 | }; | |
| 1002 | ||
| 9848ebeb JC |
1003 | pwm0 { |
| 1004 | pwm0_pin: pwm0-pin { | |
| 1005 | rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_none>; | |
| 1006 | }; | |
| 1007 | }; | |
| 1008 | ||
| 1009 | pwm1 { | |
| 1010 | pwm1_pin: pwm1-pin { | |
| 1011 | rockchip,pins = <0 30 RK_FUNC_2 &pcfg_pull_none>; | |
| 1012 | }; | |
| 1013 | }; | |
| 1014 | ||
| 1015 | pwm2 { | |
| 1016 | pwm2_pin: pwm2-pin { | |
| 1017 | rockchip,pins = <1 12 RK_FUNC_2 &pcfg_pull_none>; | |
| 1018 | }; | |
| 1019 | }; | |
| 1020 | ||
| 1021 | pwm3 { | |
| 1022 | pwm3_pin: pwm3-pin { | |
| 1023 | rockchip,pins = <1 11 RK_FUNC_2 &pcfg_pull_none>; | |
| 1024 | }; | |
| 1025 | }; | |
| 1026 | ||
| 4b456d20 SZ |
1027 | spdif { |
| 1028 | spdif_tx: spdif-tx { | |
| 1029 | rockchip,pins = <3 31 RK_FUNC_2 &pcfg_pull_none>; | |
| 1030 | }; | |
| 1031 | }; | |
| 1032 | ||
| 7796031e CW |
1033 | tsadc { |
| 1034 | otp_gpio: otp-gpio { | |
| 1035 | rockchip,pins = <0 24 RK_FUNC_GPIO &pcfg_pull_none>; | |
| 1036 | }; | |
| 1037 | ||
| 1038 | otp_out: otp-out { | |
| 1039 | rockchip,pins = <0 24 RK_FUNC_2 &pcfg_pull_none>; | |
| 1040 | }; | |
| 1041 | }; | |
| 1042 | ||
| 9848ebeb JC |
1043 | uart0 { |
| 1044 | uart0_xfer: uart0-xfer { | |
| 1045 | rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>, | |
| 1046 | <2 27 RK_FUNC_1 &pcfg_pull_none>; | |
| 1047 | }; | |
| 1048 | ||
| 1049 | uart0_cts: uart0-cts { | |
| 1050 | rockchip,pins = <2 29 RK_FUNC_1 &pcfg_pull_none>; | |
| 1051 | }; | |
| 1052 | ||
| 1053 | uart0_rts: uart0-rts { | |
| 1054 | rockchip,pins = <0 17 RK_FUNC_1 &pcfg_pull_none>; | |
| 1055 | }; | |
| 1056 | }; | |
| 1057 | ||
| 1058 | uart1 { | |
| 1059 | uart1_xfer: uart1-xfer { | |
| 1060 | rockchip,pins = <1 9 RK_FUNC_1 &pcfg_pull_none>, | |
| 1061 | <1 10 RK_FUNC_1 &pcfg_pull_none>; | |
| 1062 | }; | |
| 1063 | ||
| 1064 | uart1_cts: uart1-cts { | |
| 1065 | rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>; | |
| 1066 | }; | |
| 1067 | ||
| 1068 | uart1_rts: uart1-rts { | |
| 1069 | rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>; | |
| 1070 | }; | |
| 1071 | }; | |
| 1072 | ||
| 1073 | uart2 { | |
| 1074 | uart2_xfer: uart2-xfer { | |
| 02131477 | 1075 | rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>, |
| 9848ebeb JC |
1076 | <1 19 RK_FUNC_2 &pcfg_pull_none>; |
| 1077 | }; | |
| 1078 | ||
| 738e4511 FW |
1079 | uart21_xfer: uart21-xfer { |
| 1080 | rockchip,pins = <1 10 RK_FUNC_2 &pcfg_pull_up>, | |
| 1081 | <1 9 RK_FUNC_2 &pcfg_pull_none>; | |
| 1082 | }; | |
| 1083 | ||
| 9848ebeb JC |
1084 | uart2_cts: uart2-cts { |
| 1085 | rockchip,pins = <0 25 RK_FUNC_1 &pcfg_pull_none>; | |
| 1086 | }; | |
| 1087 | ||
| 1088 | uart2_rts: uart2-rts { | |
| 1089 | rockchip,pins = <0 24 RK_FUNC_1 &pcfg_pull_none>; | |
| 1090 | }; | |
| 1091 | }; | |
| 1092 | }; | |
| 1093 | }; |