[linux-2.6-block.git] / arch / arm / boot / dts / qcom-msm8974.dtsi

/dts-v1/;

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/qcom,gcc-msm8974.h>
#include "skeleton.dtsi"

/ {
	model = "Qualcomm MSM8974";
	compatible = "qcom,msm8974";
	interrupt-parent = <&intc>;

	reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		mpss@08000000 {
			reg = <0x08000000 0x5100000>;
			no-map;
		};

		mba@00d100000 {
			reg = <0x0d100000 0x100000>;
			no-map;
		};

		reserved@0d200000 {
			reg = <0x0d200000 0xa00000>;
			no-map;
		};

		adsp@0dc00000 {
			reg = <0x0dc00000 0x1900000>;
			no-map;
		};

		venus@0f500000 {
			reg = <0x0f500000 0x500000>;
			no-map;
		};

		smem_region: smem@fa00000 {
			reg = <0xfa00000 0x200000>;
			no-map;
		};

		tz@0fc00000 {
			reg = <0x0fc00000 0x160000>;
			no-map;
		};

		efs@0fd600000 {
			reg = <0x0fd60000 0x1a0000>;
			no-map;
		};

		unused@0ff00000 {
			reg = <0x0ff00000 0x10100000>;
			no-map;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		interrupts = <1 9 0xf04>;

		cpu@0 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v2";
			device_type = "cpu";
			reg = <0>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc0>;
			qcom,saw = <&saw0>;
			cpu-idle-states = <&CPU_SPC>;
		};

		cpu@1 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v2";
			device_type = "cpu";
			reg = <1>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc1>;
			qcom,saw = <&saw1>;
			cpu-idle-states = <&CPU_SPC>;
		};

		cpu@2 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v2";
			device_type = "cpu";
			reg = <2>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc2>;
			qcom,saw = <&saw2>;
			cpu-idle-states = <&CPU_SPC>;
		};

		cpu@3 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v2";
			device_type = "cpu";
			reg = <3>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc3>;
			qcom,saw = <&saw3>;
			cpu-idle-states = <&CPU_SPC>;
		};

		L2: l2-cache {
			compatible = "cache";
			cache-level = <2>;
			qcom,saw = <&saw_l2>;
		};

		idle-states {
			CPU_SPC: spc {
				compatible = "qcom,idle-state-spc",
						"arm,idle-state";
				entry-latency-us = <150>;
				exit-latency-us = <200>;
				min-residency-us = <2000>;
			};
		};
	};

	cpu-pmu {
		compatible = "qcom,krait-pmu";
		interrupts = <1 7 0xf04>;
	};

	clocks {
		xo_board {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <19200000>;
		};

		sleep_clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32768>;
		};
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <1 2 0xf08>,
			     <1 3 0xf08>,
			     <1 4 0xf08>,
			     <1 1 0xf08>;
		clock-frequency = <19200000>;
	};

	smem {
		compatible = "qcom,smem";

		memory-region = <&smem_region>;
		qcom,rpm-msg-ram = <&rpm_msg_ram>;

		hwlocks = <&tcsr_mutex 3>;
	};

	smp2p-wcnss {
		compatible = "qcom,smp2p";
		qcom,smem = <451>, <431>;

		interrupt-parent = <&intc>;
		interrupts = <0 143 IRQ_TYPE_EDGE_RISING>;

		qcom,ipc = <&apcs 8 18>;

		qcom,local-pid = <0>;
		qcom,remote-pid = <4>;

		wcnss_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";

			#qcom,state-cells = <1>;
		};

		wcnss_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";

			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	smsm {
		compatible = "qcom,smsm";

		#address-cells = <1>;
		#size-cells = <0>;

		qcom,ipc-1 = <&apcs 8 13>;
		qcom,ipc-2 = <&apcs 8 9>;
		qcom,ipc-3 = <&apcs 8 19>;

		apps_smsm: apps@0 {
			reg = <0>;

			#qcom,state-cells = <1>;
		};

		modem_smsm: modem@1 {
			reg = <1>;
			interrupts = <0 26 IRQ_TYPE_EDGE_RISING>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		adsp_smsm: adsp@2 {
			reg = <2>;
			interrupts = <0 157 IRQ_TYPE_EDGE_RISING>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		wcnss_smsm: wcnss@7 {
			reg = <7>;
			interrupts = <0 144 IRQ_TYPE_EDGE_RISING>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	soc: soc {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		compatible = "simple-bus";

		intc: interrupt-controller@f9000000 {
			compatible = "qcom,msm-qgic2";
			interrupt-controller;
			#interrupt-cells = <3>;
			reg = <0xf9000000 0x1000>,
			      <0xf9002000 0x1000>;
		};

		apcs: syscon@f9011000 {
			compatible = "syscon";
			reg = <0xf9011000 0x1000>;
		};

		timer@f9020000 {
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			compatible = "arm,armv7-timer-mem";
			reg = <0xf9020000 0x1000>;
			clock-frequency = <19200000>;

			frame@f9021000 {
				frame-number = <0>;
				interrupts = <0 8 0x4>,
					     <0 7 0x4>;
				reg = <0xf9021000 0x1000>,
				      <0xf9022000 0x1000>;
			};

			frame@f9023000 {
				frame-number = <1>;
				interrupts = <0 9 0x4>;
				reg = <0xf9023000 0x1000>;
				status = "disabled";
			};

			frame@f9024000 {
				frame-number = <2>;
				interrupts = <0 10 0x4>;
				reg = <0xf9024000 0x1000>;
				status = "disabled";
			};

			frame@f9025000 {
				frame-number = <3>;
				interrupts = <0 11 0x4>;
				reg = <0xf9025000 0x1000>;
				status = "disabled";
			};

			frame@f9026000 {
				frame-number = <4>;
				interrupts = <0 12 0x4>;
				reg = <0xf9026000 0x1000>;
				status = "disabled";
			};

			frame@f9027000 {
				frame-number = <5>;
				interrupts = <0 13 0x4>;
				reg = <0xf9027000 0x1000>;
				status = "disabled";
			};

			frame@f9028000 {
				frame-number = <6>;
				interrupts = <0 14 0x4>;
				reg = <0xf9028000 0x1000>;
				status = "disabled";
			};
		};

		saw0: power-controller@f9089000 {
			compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
			reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
		};

		saw1: power-controller@f9099000 {
			compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
			reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
		};

		saw2: power-controller@f90a9000 {
			compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
			reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
		};

		saw3: power-controller@f90b9000 {
			compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
			reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
		};

		saw_l2: power-controller@f9012000 {
			compatible = "qcom,saw2";
			reg = <0xf9012000 0x1000>;
			regulator;
		};

		acc0: clock-controller@f9088000 {
			compatible = "qcom,kpss-acc-v2";
			reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
		};

		acc1: clock-controller@f9098000 {
			compatible = "qcom,kpss-acc-v2";
			reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
		};

		acc2: clock-controller@f90a8000 {
			compatible = "qcom,kpss-acc-v2";
			reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
		};

		acc3: clock-controller@f90b8000 {
			compatible = "qcom,kpss-acc-v2";
			reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
		};

		restart@fc4ab000 {
			compatible = "qcom,pshold";
			reg = <0xfc4ab000 0x4>;
		};

		gcc: clock-controller@fc400000 {
			compatible = "qcom,gcc-msm8974";
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
			reg = <0xfc400000 0x4000>;
		};

		tcsr_mutex_block: syscon@fd484000 {
			compatible = "syscon";
			reg = <0xfd484000 0x2000>;
		};

		mmcc: clock-controller@fd8c0000 {
			compatible = "qcom,mmcc-msm8974";
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
			reg = <0xfd8c0000 0x6000>;
		};

		tcsr_mutex: tcsr-mutex {
			compatible = "qcom,tcsr-mutex";
			syscon = <&tcsr_mutex_block 0 0x80>;

			#hwlock-cells = <1>;
		};

		rpm_msg_ram: memory@fc428000 {
			compatible = "qcom,rpm-msg-ram";
			reg = <0xfc428000 0x4000>;
		};

		blsp1_uart2: serial@f991e000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0xf991e000 0x1000>;
			interrupts = <0 108 0x0>;
			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			status = "disabled";
		};

		sdhci@f9824900 {
			compatible = "qcom,sdhci-msm-v4";
			reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
			reg-names = "hc_mem", "core_mem";
			interrupts = <0 123 0>, <0 138 0>;
			interrupt-names = "hc_irq", "pwr_irq";
			clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
			clock-names = "core", "iface";
			status = "disabled";
		};

		sdhci@f98a4900 {
			compatible = "qcom,sdhci-msm-v4";
			reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
			reg-names = "hc_mem", "core_mem";
			interrupts = <0 125 0>, <0 221 0>;
			interrupt-names = "hc_irq", "pwr_irq";
			clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
			clock-names = "core", "iface";
			status = "disabled";
		};

		rng@f9bff000 {
			compatible = "qcom,prng";
			reg = <0xf9bff000 0x200>;
			clocks = <&gcc GCC_PRNG_AHB_CLK>;
			clock-names = "core";
		};

		msmgpio: pinctrl@fd510000 {
			compatible = "qcom,msm8974-pinctrl";
			reg = <0xfd510000 0x4000>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupts = <0 208 0>;
		};

		blsp_i2c8: i2c@f9964000 {
			status = "disabled";
			compatible = "qcom,i2c-qup-v2.1.1";
			reg = <0xf9964000 0x1000>;
			interrupts = <0 102 IRQ_TYPE_NONE>;
			clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
			clock-names = "core", "iface";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		blsp_i2c11: i2c@f9967000 {
			status = "disabled";
			compatible = "qcom,i2c-qup-v2.1.1";
			reg = <0xf9967000 0x1000>;
			interrupts = <0 105 IRQ_TYPE_NONE>;
			clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
			clock-names = "core", "iface";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		spmi_bus: spmi@fc4cf000 {
			compatible = "qcom,spmi-pmic-arb";
			reg-names = "core", "intr", "cnfg";
			reg = <0xfc4cf000 0x1000>,
			      <0xfc4cb000 0x1000>,
			      <0xfc4ca000 0x1000>;
			interrupt-names = "periph_irq";
			interrupts = <0 190 0>;
			qcom,ee = <0>;
			qcom,channel = <0>;
			#address-cells = <2>;
			#size-cells = <0>;
			interrupt-controller;
			#interrupt-cells = <4>;
		};
	};

	smd {
		compatible = "qcom,smd";

		rpm {
			interrupts = <0 168 1>;
			qcom,ipc = <&apcs 8 0>;
			qcom,smd-edge = <15>;

			rpm_requests {
				compatible = "qcom,rpm-msm8974";
				qcom,smd-channels = "rpm_requests";

				pm8841-regulators {
					compatible = "qcom,rpm-pm8841-regulators";

					pm8841_s1: s1 {};
					pm8841_s2: s2 {};
					pm8841_s3: s3 {};
					pm8841_s4: s4 {};
					pm8841_s5: s5 {};
					pm8841_s6: s6 {};
					pm8841_s7: s7 {};
					pm8841_s8: s8 {};
				};

				pm8941-regulators {
					compatible = "qcom,rpm-pm8941-regulators";

					pm8941_s1: s1 {};
					pm8941_s2: s2 {};
					pm8941_s3: s3 {};
					pm8941_5v: s4 {};

					pm8941_l1: l1 {};
					pm8941_l2: l2 {};
					pm8941_l3: l3 {};
					pm8941_l4: l4 {};
					pm8941_l5: l5 {};
					pm8941_l6: l6 {};
					pm8941_l7: l7 {};
					pm8941_l8: l8 {};
					pm8941_l9: l9 {};
					pm8941_l10: l10 {};
					pm8941_l11: l11 {};
					pm8941_l12: l12 {};
					pm8941_l13: l13 {};
					pm8941_l14: l14 {};
					pm8941_l15: l15 {};
					pm8941_l16: l16 {};
					pm8941_l17: l17 {};
					pm8941_l18: l18 {};
					pm8941_l19: l19 {};
					pm8941_l20: l20 {};
					pm8941_l21: l21 {};
					pm8941_l22: l22 {};
					pm8941_l23: l23 {};
					pm8941_l24: l24 {};

					pm8941_lvs1: lvs1 {};
					pm8941_lvs2: lvs2 {};
					pm8941_lvs3: lvs3 {};

					pm8941_5vs1: 5vs1 {};
					pm8941_5vs2: 5vs2 {};
				};
			};
		};
	};
};
Commit	Line	Data
2aec37c6 RV	1	/dts-v1/;
2aec37c6 RV	2
338d5188	3	#include <dt-bindings/interrupt-controller/irq.h>
3933d267	4	#include <dt-bindings/clock/qcom,gcc-msm8974.h>
bf7f6b04	5	#include "skeleton.dtsi"
3933d267	6
2aec37c6 RV	7	/ {
	8	model = "Qualcomm MSM8974";
	9	compatible = "qcom,msm8974";
	10	interrupt-parent = <&intc>;
	11
6297c4b2 BA	12	reserved-memory {
	13	#address-cells = <1>;
	14	#size-cells = <1>;
	15	ranges;
	16
ca3971cf BA	17	mpss@08000000 {
	18	reg = <0x08000000 0x5100000>;
	19	no-map;
	20	};
	21
	22	mba@00d100000 {
	23	reg = <0x0d100000 0x100000>;
	24	no-map;
	25	};
	26
	27	reserved@0d200000 {
	28	reg = <0x0d200000 0xa00000>;
	29	no-map;
	30	};
	31
	32	adsp@0dc00000 {
	33	reg = <0x0dc00000 0x1900000>;
	34	no-map;
	35	};
	36
	37	venus@0f500000 {
	38	reg = <0x0f500000 0x500000>;
	39	no-map;
	40	};
	41
6297c4b2 BA	42	smem_region: smem@fa00000 {
	43	reg = <0xfa00000 0x200000>;
	44	no-map;
	45	};
ca3971cf BA	46
	47	tz@0fc00000 {
	48	reg = <0x0fc00000 0x160000>;
	49	no-map;
	50	};
	51
	52	efs@0fd600000 {
	53	reg = <0x0fd60000 0x1a0000>;
	54	no-map;
	55	};
	56
	57	unused@0ff00000 {
	58	reg = <0x0ff00000 0x10100000>;
	59	no-map;
	60	};
6297c4b2 BA	61	};
6297c4b2 BA	62
2ab27991 RV	63	cpus {
	64	#address-cells = <1>;
	65	#size-cells = <0>;
	66	interrupts = <1 9 0xf04>;
2ab27991 RV	67
2ab27991 RV	68	cpu@0 {
ba08220a KG	69	compatible = "qcom,krait";
ba08220a KG	70	enable-method = "qcom,kpss-acc-v2";
2ab27991 RV	71	device_type = "cpu";
	72	reg = <0>;
	73	next-level-cache = <&L2>;
	74	qcom,acc = <&acc0>;
8c76a638	75	qcom,saw = <&saw0>;
d596d620	76	cpu-idle-states = <&CPU_SPC>;
2ab27991 RV	77	};
	78
	79	cpu@1 {
ba08220a KG	80	compatible = "qcom,krait";
ba08220a KG	81	enable-method = "qcom,kpss-acc-v2";
2ab27991 RV	82	device_type = "cpu";
	83	reg = <1>;
	84	next-level-cache = <&L2>;
	85	qcom,acc = <&acc1>;
8c76a638	86	qcom,saw = <&saw1>;
d596d620	87	cpu-idle-states = <&CPU_SPC>;
2ab27991 RV	88	};
	89
	90	cpu@2 {
ba08220a KG	91	compatible = "qcom,krait";
ba08220a KG	92	enable-method = "qcom,kpss-acc-v2";
2ab27991 RV	93	device_type = "cpu";
	94	reg = <2>;
	95	next-level-cache = <&L2>;
	96	qcom,acc = <&acc2>;
8c76a638	97	qcom,saw = <&saw2>;
d596d620	98	cpu-idle-states = <&CPU_SPC>;
2ab27991 RV	99	};
	100
	101	cpu@3 {
ba08220a KG	102	compatible = "qcom,krait";
ba08220a KG	103	enable-method = "qcom,kpss-acc-v2";
2ab27991 RV	104	device_type = "cpu";
	105	reg = <3>;
	106	next-level-cache = <&L2>;
	107	qcom,acc = <&acc3>;
8c76a638	108	qcom,saw = <&saw3>;
d596d620	109	cpu-idle-states = <&CPU_SPC>;
2ab27991 RV	110	};
	111
	112	L2: l2-cache {
	113	compatible = "cache";
	114	cache-level = <2>;
2ab27991 RV	115	qcom,saw = <&saw_l2>;
2ab27991 RV	116	};
d596d620 LI	117
	118	idle-states {
	119	CPU_SPC: spc {
	120	compatible = "qcom,idle-state-spc",
	121	"arm,idle-state";
	122	entry-latency-us = <150>;
	123	exit-latency-us = <200>;
	124	min-residency-us = <2000>;
	125	};
	126	};
2ab27991 RV	127	};
2ab27991 RV	128
3bff5474 SB	129	cpu-pmu {
	130	compatible = "qcom,krait-pmu";
	131	interrupts = <1 7 0xf04>;
	132	};
	133
30fc4212 SB	134	clocks {
	135	xo_board {
	136	compatible = "fixed-clock";
	137	#clock-cells = <0>;
	138	clock-frequency = <19200000>;
	139	};
	140
	141	sleep_clk {
	142	compatible = "fixed-clock";
	143	#clock-cells = <0>;
	144	clock-frequency = <32768>;
	145	};
	146	};
	147
ba08220a KG	148	timer {
	149	compatible = "arm,armv7-timer";
	150	interrupts = <1 2 0xf08>,
	151	<1 3 0xf08>,
	152	<1 4 0xf08>,
	153	<1 1 0xf08>;
	154	clock-frequency = <19200000>;
	155	};
	156
d0bfd7c9 SB	157	smem {
	158	compatible = "qcom,smem";
	159
	160	memory-region = <&smem_region>;
	161	qcom,rpm-msg-ram = <&rpm_msg_ram>;
	162
	163	hwlocks = <&tcsr_mutex 3>;
	164	};
	165
7ccb11e7 BA	166	smp2p-wcnss {
	167	compatible = "qcom,smp2p";
	168	qcom,smem = <451>, <431>;
	169
	170	interrupt-parent = <&intc>;
	171	interrupts = <0 143 IRQ_TYPE_EDGE_RISING>;
	172
	173	qcom,ipc = <&apcs 8 18>;
	174
	175	qcom,local-pid = <0>;
	176	qcom,remote-pid = <4>;
	177
	178	wcnss_smp2p_out: master-kernel {
	179	qcom,entry-name = "master-kernel";
	180
	181	#qcom,state-cells = <1>;
	182	};
	183
	184	wcnss_smp2p_in: slave-kernel {
	185	qcom,entry-name = "slave-kernel";
	186
	187	interrupt-controller;
	188	#interrupt-cells = <2>;
	189	};
	190	};
	191
9af88b2d BA	192	smsm {
	193	compatible = "qcom,smsm";
	194
	195	#address-cells = <1>;
	196	#size-cells = <0>;
	197
	198	qcom,ipc-1 = <&apcs 8 13>;
	199	qcom,ipc-2 = <&apcs 8 9>;
	200	qcom,ipc-3 = <&apcs 8 19>;
	201
	202	apps_smsm: apps@0 {
	203	reg = <0>;
	204
	205	#qcom,state-cells = <1>;
	206	};
	207
	208	modem_smsm: modem@1 {
	209	reg = <1>;
	210	interrupts = <0 26 IRQ_TYPE_EDGE_RISING>;
	211
	212	interrupt-controller;
	213	#interrupt-cells = <2>;
	214	};
	215
	216	adsp_smsm: adsp@2 {
	217	reg = <2>;
	218	interrupts = <0 157 IRQ_TYPE_EDGE_RISING>;
	219
	220	interrupt-controller;
	221	#interrupt-cells = <2>;
	222	};
	223
	224	wcnss_smsm: wcnss@7 {
	225	reg = <7>;
	226	interrupts = <0 144 IRQ_TYPE_EDGE_RISING>;
	227
	228	interrupt-controller;
	229	#interrupt-cells = <2>;
	230	};
	231	};
	232
2aec37c6 RV	233	soc: soc {
	234	#address-cells = <1>;
	235	#size-cells = <1>;
	236	ranges;
	237	compatible = "simple-bus";
	238
	239	intc: interrupt-controller@f9000000 {
	240	compatible = "qcom,msm-qgic2";
	241	interrupt-controller;
	242	#interrupt-cells = <3>;
	243	reg = <0xf9000000 0x1000>,
	244	<0xf9002000 0x1000>;
	245	};
	246
45b0ef05 BA	247	apcs: syscon@f9011000 {
	248	compatible = "syscon";
	249	reg = <0xf9011000 0x1000>;
	250	};
	251
47c5a5d6 SB	252	timer@f9020000 {
	253	#address-cells = <1>;
	254	#size-cells = <1>;
	255	ranges;
	256	compatible = "arm,armv7-timer-mem";
	257	reg = <0xf9020000 0x1000>;
	258	clock-frequency = <19200000>;
	259
	260	frame@f9021000 {
	261	frame-number = <0>;
	262	interrupts = <0 8 0x4>,
	263	<0 7 0x4>;
	264	reg = <0xf9021000 0x1000>,
	265	<0xf9022000 0x1000>;
	266	};
	267
	268	frame@f9023000 {
	269	frame-number = <1>;
	270	interrupts = <0 9 0x4>;
	271	reg = <0xf9023000 0x1000>;
	272	status = "disabled";
	273	};
	274
	275	frame@f9024000 {
	276	frame-number = <2>;
	277	interrupts = <0 10 0x4>;
	278	reg = <0xf9024000 0x1000>;
	279	status = "disabled";
	280	};
	281
	282	frame@f9025000 {
	283	frame-number = <3>;
	284	interrupts = <0 11 0x4>;
	285	reg = <0xf9025000 0x1000>;
	286	status = "disabled";
	287	};
	288
	289	frame@f9026000 {
	290	frame-number = <4>;
	291	interrupts = <0 12 0x4>;
	292	reg = <0xf9026000 0x1000>;
	293	status = "disabled";
	294	};
	295
	296	frame@f9027000 {
	297	frame-number = <5>;
	298	interrupts = <0 13 0x4>;
	299	reg = <0xf9027000 0x1000>;
	300	status = "disabled";
	301	};
	302
	303	frame@f9028000 {
	304	frame-number = <6>;
	305	interrupts = <0 14 0x4>;
	306	reg = <0xf9028000 0x1000>;
	307	status = "disabled";
	308	};
	309	};
	310
8c76a638 LI	311	saw0: power-controller@f9089000 {
	312	compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
	313	reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
	314	};
	315
	316	saw1: power-controller@f9099000 {
	317	compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
	318	reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
	319	};
	320
	321	saw2: power-controller@f90a9000 {
	322	compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
	323	reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
	324	};
	325
	326	saw3: power-controller@f90b9000 {
	327	compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
	328	reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
	329	};
	330
	331	saw_l2: power-controller@f9012000 {
2ab27991 RV	332	compatible = "qcom,saw2";
	333	reg = <0xf9012000 0x1000>;
	334	regulator;
	335	};
	336
	337	acc0: clock-controller@f9088000 {
	338	compatible = "qcom,kpss-acc-v2";
	339	reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
	340	};
	341
	342	acc1: clock-controller@f9098000 {
	343	compatible = "qcom,kpss-acc-v2";
	344	reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
	345	};
	346
	347	acc2: clock-controller@f90a8000 {
	348	compatible = "qcom,kpss-acc-v2";
	349	reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
	350	};
	351
	352	acc3: clock-controller@f90b8000 {
	353	compatible = "qcom,kpss-acc-v2";
	354	reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
	355	};
	356
74e848f6 SB	357	restart@fc4ab000 {
	358	compatible = "qcom,pshold";
	359	reg = <0xfc4ab000 0x4>;
	360	};
3933d267 SB	361
	362	gcc: clock-controller@fc400000 {
	363	compatible = "qcom,gcc-msm8974";
	364	#clock-cells = <1>;
	365	#reset-cells = <1>;
89c7e671	366	#power-domain-cells = <1>;
3933d267 SB	367	reg = <0xfc400000 0x4000>;
	368	};
	369
b4e745e1 BA	370	tcsr_mutex_block: syscon@fd484000 {
	371	compatible = "syscon";
	372	reg = <0xfd484000 0x2000>;
	373	};
	374
3933d267 SB	375	mmcc: clock-controller@fd8c0000 {
	376	compatible = "qcom,mmcc-msm8974";
	377	#clock-cells = <1>;
	378	#reset-cells = <1>;
89c7e671	379	#power-domain-cells = <1>;
3933d267 SB	380	reg = <0xfd8c0000 0x6000>;
	381	};
	382
b4e745e1 BA	383	tcsr_mutex: tcsr-mutex {
	384	compatible = "qcom,tcsr-mutex";
	385	syscon = <&tcsr_mutex_block 0 0x80>;
	386
	387	#hwlock-cells = <1>;
	388	};
	389
d0bfd7c9 SB	390	rpm_msg_ram: memory@fc428000 {
d0bfd7c9 SB	391	compatible = "qcom,rpm-msg-ram";
6297c4b2	392	reg = <0xfc428000 0x4000>;
6297c4b2 BA	393	};
6297c4b2 BA	394
10bfcfea	395	blsp1_uart2: serial@f991e000 {
3933d267 SB	396	compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
	397	reg = <0xf991e000 0x1000>;
	398	interrupts = <0 108 0x0>;
	399	clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
	400	clock-names = "core", "iface";
ba08220a	401	status = "disabled";
3933d267	402	};
19f4f8c1	403
3e944c76 GD	404	sdhci@f9824900 {
	405	compatible = "qcom,sdhci-msm-v4";
	406	reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
	407	reg-names = "hc_mem", "core_mem";
	408	interrupts = <0 123 0>, <0 138 0>;
	409	interrupt-names = "hc_irq", "pwr_irq";
	410	clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
	411	clock-names = "core", "iface";
	412	status = "disabled";
	413	};
	414
	415	sdhci@f98a4900 {
	416	compatible = "qcom,sdhci-msm-v4";
	417	reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
	418	reg-names = "hc_mem", "core_mem";
	419	interrupts = <0 125 0>, <0 221 0>;
	420	interrupt-names = "hc_irq", "pwr_irq";
	421	clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
	422	clock-names = "core", "iface";
	423	status = "disabled";
	424	};
	425
19f4f8c1 SV	426	rng@f9bff000 {
	427	compatible = "qcom,prng";
	428	reg = <0xf9bff000 0x200>;
	429	clocks = <&gcc GCC_PRNG_AHB_CLK>;
	430	clock-names = "core";
	431	};
7d7db8db II	432
	433	msmgpio: pinctrl@fd510000 {
	434	compatible = "qcom,msm8974-pinctrl";
	435	reg = <0xfd510000 0x4000>;
	436	gpio-controller;
	437	#gpio-cells = <2>;
	438	interrupt-controller;
	439	#interrupt-cells = <2>;
	440	interrupts = <0 208 0>;
7d7db8db	441	};
bf7f6b04	442
580df59f BA	443	blsp_i2c8: i2c@f9964000 {
	444	status = "disabled";
	445	compatible = "qcom,i2c-qup-v2.1.1";
	446	reg = <0xf9964000 0x1000>;
	447	interrupts = <0 102 IRQ_TYPE_NONE>;
	448	clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
	449	clock-names = "core", "iface";
	450	#address-cells = <1>;
	451	#size-cells = <0>;
	452	};
	453
bf7f6b04	454	blsp_i2c11: i2c@f9967000 {
04edde25	455	status = "disabled";
bf7f6b04	456	compatible = "qcom,i2c-qup-v2.1.1";
	457	reg = <0xf9967000 0x1000>;
	458	interrupts = <0 105 IRQ_TYPE_NONE>;
	459	clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
	460	clock-names = "core", "iface";
	461	#address-cells = <1>;
	462	#size-cells = <0>;
	463	};
af22e46d II	464
	465	spmi_bus: spmi@fc4cf000 {
	466	compatible = "qcom,spmi-pmic-arb";
	467	reg-names = "core", "intr", "cnfg";
	468	reg = <0xfc4cf000 0x1000>,
	469	<0xfc4cb000 0x1000>,
	470	<0xfc4ca000 0x1000>;
	471	interrupt-names = "periph_irq";
	472	interrupts = <0 190 0>;
	473	qcom,ee = <0>;
	474	qcom,channel = <0>;
	475	#address-cells = <2>;
	476	#size-cells = <0>;
	477	interrupt-controller;
	478	#interrupt-cells = <4>;
	479	};
2aec37c6	480	};
45b0ef05 BA	481
	482	smd {
	483	compatible = "qcom,smd";
	484
	485	rpm {
	486	interrupts = <0 168 1>;
	487	qcom,ipc = <&apcs 8 0>;
	488	qcom,smd-edge = <15>;
	489
	490	rpm_requests {
	491	compatible = "qcom,rpm-msm8974";
	492	qcom,smd-channels = "rpm_requests";
	493
	494	pm8841-regulators {
	495	compatible = "qcom,rpm-pm8841-regulators";
	496
	497	pm8841_s1: s1 {};
	498	pm8841_s2: s2 {};
	499	pm8841_s3: s3 {};
	500	pm8841_s4: s4 {};
	501	pm8841_s5: s5 {};
	502	pm8841_s6: s6 {};
	503	pm8841_s7: s7 {};
	504	pm8841_s8: s8 {};
	505	};
	506
	507	pm8941-regulators {
	508	compatible = "qcom,rpm-pm8941-regulators";
	509
	510	pm8941_s1: s1 {};
	511	pm8941_s2: s2 {};
	512	pm8941_s3: s3 {};
	513	pm8941_5v: s4 {};
	514
	515	pm8941_l1: l1 {};
	516	pm8941_l2: l2 {};
	517	pm8941_l3: l3 {};
	518	pm8941_l4: l4 {};
	519	pm8941_l5: l5 {};
	520	pm8941_l6: l6 {};
	521	pm8941_l7: l7 {};
	522	pm8941_l8: l8 {};
	523	pm8941_l9: l9 {};
	524	pm8941_l10: l10 {};
	525	pm8941_l11: l11 {};
	526	pm8941_l12: l12 {};
	527	pm8941_l13: l13 {};
	528	pm8941_l14: l14 {};
	529	pm8941_l15: l15 {};
	530	pm8941_l16: l16 {};
	531	pm8941_l17: l17 {};
	532	pm8941_l18: l18 {};
	533	pm8941_l19: l19 {};
	534	pm8941_l20: l20 {};
	535	pm8941_l21: l21 {};
	536	pm8941_l22: l22 {};
	537	pm8941_l23: l23 {};
	538	pm8941_l24: l24 {};
	539
	540	pm8941_lvs1: lvs1 {};
	541	pm8941_lvs2: lvs2 {};
	542	pm8941_lvs3: lvs3 {};
	543
	544	pm8941_5vs1: 5vs1 {};
545	pm8941_5vs2: 5vs2 {};
546	};
547	};
548	};
549	};
2aec37c6	550	};