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ARM: dts: ls1021a: Add all CPUs in cooling maps
[linux-2.6-block.git] / arch / arm / boot / dts / ls1021a.dtsi
CommitLineData
7239280c
JL		 1/*
2 * Copyright 2013-2014 Freescale Semiconductor, Inc.
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public
20 * License along with this file; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 * MA 02110-1301 USA
23 *
24 * Or, alternatively,
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
46 */
47
48#include "skeleton64.dtsi"
49#include <dt-bindings/interrupt-controller/arm-gic.h>
4d9e9cbb 50#include <dt-bindings/thermal/thermal.h>
7239280c
JL		 51
52/ {
53 compatible = "fsl,ls1021a";
54 interrupt-parent = <&gic>;
55
56 aliases {
816aa61c 57 crypto = &crypto;
d69cb5d7
CM		 58 ethernet0 = &enet0;
59 ethernet1 = &enet1;
60 ethernet2 = &enet2;
7239280c
JL		 61 serial0 = &lpuart0;
62 serial1 = &lpuart1;
63 serial2 = &lpuart2;
64 serial3 = &lpuart3;
65 serial4 = &lpuart4;
66 serial5 = &lpuart5;
67 sysclk = &sysclk;
68 };
69
70 cpus {
71 #address-cells = <1>;
72 #size-cells = <0>;
73
4d9e9cbb 74 cpu0: cpu@f00 {
7239280c
JL		 75 compatible = "arm,cortex-a7";
76 device_type = "cpu";
77 reg = <0xf00>;
b6f5e701 78 clocks = <&clockgen 1 0>;
4d9e9cbb 79 #cooling-cells = <2>;
7239280c
JL		 80 };
81
4d9e9cbb 82 cpu1: cpu@f01 {
7239280c
JL		 83 compatible = "arm,cortex-a7";
84 device_type = "cpu";
85 reg = <0xf01>;
b6f5e701 86 clocks = <&clockgen 1 0>;
47768f37 87 #cooling-cells = <2>;
7239280c
JL		 88 };
89 };
90
b6f5e701
YT		 91 sysclk: sysclk {
92 compatible = "fixed-clock";
93 #clock-cells = <0>;
94 clock-frequency = <100000000>;
95 clock-output-names = "sysclk";
96 };
97
7239280c
JL		 98 timer {
99 compatible = "arm,armv7-timer";
100 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
101 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
102 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
103 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
104 };
105
106 pmu {
107 compatible = "arm,cortex-a7-pmu";
108 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
109 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
6742139b 110 interrupt-affinity = <&cpu0>, <&cpu1>;
7239280c
JL		 111 };
112
7eaec553
RV		 113 reboot {
114 compatible = "syscon-reboot";
115 regmap = <&dcfg>;
116 offset = <0xb0>;
117 mask = <0x02>;
7239280c
JL		 118 };
119
120 soc {
121 compatible = "simple-bus";
122 #address-cells = <2>;
123 #size-cells = <2>;
124 device_type = "soc";
125 interrupt-parent = <&gic>;
126 ranges;
127
128 gic: interrupt-controller@1400000 {
387720c9 129 compatible = "arm,gic-400", "arm,cortex-a7-gic";
7239280c
JL		 130 #interrupt-cells = <3>;
131 interrupt-controller;
132 reg = <0x0 0x1401000 0x0 0x1000>,
387720c9 133 <0x0 0x1402000 0x0 0x2000>,
7239280c
JL		 134 <0x0 0x1404000 0x0 0x2000>,
135 <0x0 0x1406000 0x0 0x2000>;
136 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
137
138 };
139
f4a458fd 140 msi1: msi-controller@1570e00 {
c9041ea3 141 compatible = "fsl,ls1021a-msi";
f4a458fd
ML		 142 reg = <0x0 0x1570e00 0x0 0x8>;
143 msi-controller;
144 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
145 };
146
147 msi2: msi-controller@1570e08 {
c9041ea3 148 compatible = "fsl,ls1021a-msi";
f4a458fd
ML		 149 reg = <0x0 0x1570e08 0x0 0x8>;
150 msi-controller;
151 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
152 };
153
7239280c
JL		 154 ifc: ifc@1530000 {
155 compatible = "fsl,ifc", "simple-bus";
156 reg = <0x0 0x1530000 0x0 0x10000>;
157 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
158 };
159
160 dcfg: dcfg@1ee0000 {
161 compatible = "fsl,ls1021a-dcfg", "syscon";
162 reg = <0x0 0x1ee0000 0x0 0x10000>;
163 big-endian;
164 };
165
5a2ecf0d 166 qspi: spi@1550000 {
85f8ee78
SL		 167 compatible = "fsl,ls1021a-qspi";
168 #address-cells = <1>;
169 #size-cells = <0>;
170 reg = <0x0 0x1550000 0x0 0x10000>,
171 <0x0 0x40000000 0x0 0x40000000>;
172 reg-names = "QuadSPI", "QuadSPI-memory";
173 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
174 clock-names = "qspi_en", "qspi";
175 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
176 big-endian;
177 status = "disabled";
178 };
179
7239280c 180 esdhc: esdhc@1560000 {
d5c7b4d5 181 compatible = "fsl,ls1021a-esdhc", "fsl,esdhc";
7239280c
JL		 182 reg = <0x0 0x1560000 0x0 0x10000>;
183 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
184 clock-frequency = <0>;
185 voltage-ranges = <1800 1800 3300 3300>;
186 sdhci,auto-cmd12;
187 big-endian;
188 bus-width = <4>;
189 status = "disabled";
190 };
191
318f05e5
TY		 192 sata: sata@3200000 {
193 compatible = "fsl,ls1021a-ahci";
194 reg = <0x0 0x3200000 0x0 0x10000>,
195 <0x0 0x20220520 0x0 0x4>;
196 reg-names = "ahci", "sata-ecc";
197 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
b6f5e701 198 clocks = <&clockgen 4 1>;
318f05e5
TY		 199 dma-coherent;
200 status = "disabled";
201 };
202
7239280c
JL		 203 scfg: scfg@1570000 {
204 compatible = "fsl,ls1021a-scfg", "syscon";
205 reg = <0x0 0x1570000 0x0 0x10000>;
4fe6be0f 206 big-endian;
7239280c
JL		 207 };
208
816aa61c
HG		 209 crypto: crypto@1700000 {
210 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
211 fsl,sec-era = <7>;
212 #address-cells = <1>;
213 #size-cells = <1>;
214 reg = <0x0 0x1700000 0x0 0x100000>;
215 ranges = <0x0 0x0 0x1700000 0x100000>;
216 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
217
218 sec_jr0: jr@10000 {
219 compatible = "fsl,sec-v5.0-job-ring",
220 "fsl,sec-v4.0-job-ring";
221 reg = <0x10000 0x10000>;
222 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
223 };
224
225 sec_jr1: jr@20000 {
226 compatible = "fsl,sec-v5.0-job-ring",
227 "fsl,sec-v4.0-job-ring";
228 reg = <0x20000 0x10000>;
229 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
230 };
231
232 sec_jr2: jr@30000 {
233 compatible = "fsl,sec-v5.0-job-ring",
234 "fsl,sec-v4.0-job-ring";
235 reg = <0x30000 0x10000>;
236 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
237 };
238
239 sec_jr3: jr@40000 {
240 compatible = "fsl,sec-v5.0-job-ring",
241 "fsl,sec-v4.0-job-ring";
242 reg = <0x40000 0x10000>;
243 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
244 };
245
246 };
247
7239280c 248 clockgen: clocking@1ee1000 {
b6f5e701
YT		 249 compatible = "fsl,ls1021a-clockgen";
250 reg = <0x0 0x1ee1000 0x0 0x1000>;
251 #clock-cells = <2>;
252 clocks = <&sysclk>;
7239280c
JL		 253 };
254
4d9e9cbb
HJ		 255 tmu: tmu@1f00000 {
256 compatible = "fsl,qoriq-tmu";
257 reg = <0x0 0x1f00000 0x0 0x10000>;
258 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
259 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x30061>;
260 fsl,tmu-calibration = <0x00000000 0x0000000f
261 0x00000001 0x00000017
262 0x00000002 0x0000001e
263 0x00000003 0x00000026
264 0x00000004 0x0000002e
265 0x00000005 0x00000035
266 0x00000006 0x0000003d
267 0x00000007 0x00000044
268 0x00000008 0x0000004c
269 0x00000009 0x00000053
270 0x0000000a 0x0000005b
271 0x0000000b 0x00000064
272
273 0x00010000 0x00000011
274 0x00010001 0x0000001c
275 0x00010002 0x00000024
276 0x00010003 0x0000002b
277 0x00010004 0x00000034
278 0x00010005 0x00000039
279 0x00010006 0x00000042
280 0x00010007 0x0000004c
281 0x00010008 0x00000051
282 0x00010009 0x0000005a
283 0x0001000a 0x00000063
284
285 0x00020000 0x00000013
286 0x00020001 0x00000019
287 0x00020002 0x00000024
288 0x00020003 0x0000002c
289 0x00020004 0x00000035
290 0x00020005 0x0000003d
291 0x00020006 0x00000046
292 0x00020007 0x00000050
293 0x00020008 0x00000059
294
295 0x00030000 0x00000002
296 0x00030001 0x0000000d
297 0x00030002 0x00000019
298 0x00030003 0x00000024>;
299 #thermal-sensor-cells = <1>;
300 };
301
302 thermal-zones {
303 cpu_thermal: cpu-thermal {
304 polling-delay-passive = <1000>;
305 polling-delay = <5000>;
306
307 thermal-sensors = <&tmu 0>;
308
309 trips {
310 cpu_alert: cpu-alert {
311 temperature = <85000>;
312 hysteresis = <2000>;
313 type = "passive";
314 };
315 cpu_crit: cpu-crit {
316 temperature = <95000>;
317 hysteresis = <2000>;
318 type = "critical";
319 };
320 };
321
322 cooling-maps {
323 map0 {
324 trip = <&cpu_alert>;
325 cooling-device =
326 <&cpu0 THERMAL_NO_LIMIT
4d8aa009
VK		 327 THERMAL_NO_LIMIT>,
328 <&cpu1 THERMAL_NO_LIMIT
4d9e9cbb
HJ		 329 THERMAL_NO_LIMIT>;
330 };
331 };
332 };
333 };
334
5a2ecf0d 335 dspi0: spi@2100000 {
c47d6e38 336 compatible = "fsl,ls1021a-v1.0-dspi";
7239280c
JL		 337 #address-cells = <1>;
338 #size-cells = <0>;
339 reg = <0x0 0x2100000 0x0 0x10000>;
340 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
341 clock-names = "dspi";
b6f5e701 342 clocks = <&clockgen 4 1>;
5b9f967c 343 spi-num-chipselects = <6>;
7239280c
JL		 344 big-endian;
345 status = "disabled";
346 };
347
5a2ecf0d 348 dspi1: spi@2110000 {
c47d6e38 349 compatible = "fsl,ls1021a-v1.0-dspi";
7239280c
JL		 350 #address-cells = <1>;
351 #size-cells = <0>;
352 reg = <0x0 0x2110000 0x0 0x10000>;
353 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
354 clock-names = "dspi";
b6f5e701 355 clocks = <&clockgen 4 1>;
5b9f967c 356 spi-num-chipselects = <6>;
7239280c
JL		 357 big-endian;
358 status = "disabled";
359 };
360
361 i2c0: i2c@2180000 {
362 compatible = "fsl,vf610-i2c";
363 #address-cells = <1>;
364 #size-cells = <0>;
365 reg = <0x0 0x2180000 0x0 0x10000>;
366 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
367 clock-names = "i2c";
b6f5e701 368 clocks = <&clockgen 4 1>;
cc07fd3c
EH		 369 dma-names = "tx", "rx";
370 dmas = <&edma0 1 39>, <&edma0 1 38>;
7239280c
JL		 371 status = "disabled";
372 };
373
374 i2c1: i2c@2190000 {
375 compatible = "fsl,vf610-i2c";
376 #address-cells = <1>;
377 #size-cells = <0>;
378 reg = <0x0 0x2190000 0x0 0x10000>;
379 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
380 clock-names = "i2c";
b6f5e701 381 clocks = <&clockgen 4 1>;
cc07fd3c
EH		 382 dma-names = "tx", "rx";
383 dmas = <&edma0 1 37>, <&edma0 1 36>;
7239280c
JL		 384 status = "disabled";
385 };
386
387 i2c2: i2c@21a0000 {
388 compatible = "fsl,vf610-i2c";
389 #address-cells = <1>;
390 #size-cells = <0>;
391 reg = <0x0 0x21a0000 0x0 0x10000>;
392 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
393 clock-names = "i2c";
b6f5e701 394 clocks = <&clockgen 4 1>;
cc07fd3c
EH		 395 dma-names = "tx", "rx";
396 dmas = <&edma0 1 35>, <&edma0 1 34>;
7239280c
JL		 397 status = "disabled";
398 };
399
400 uart0: serial@21c0500 {
401 compatible = "fsl,16550-FIFO64", "ns16550a";
402 reg = <0x0 0x21c0500 0x0 0x100>;
403 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
404 clock-frequency = <0>;
405 fifo-size = <15>;
406 status = "disabled";
407 };
408
409 uart1: serial@21c0600 {
410 compatible = "fsl,16550-FIFO64", "ns16550a";
411 reg = <0x0 0x21c0600 0x0 0x100>;
412 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
413 clock-frequency = <0>;
414 fifo-size = <15>;
415 status = "disabled";
416 };
417
418 uart2: serial@21d0500 {
419 compatible = "fsl,16550-FIFO64", "ns16550a";
420 reg = <0x0 0x21d0500 0x0 0x100>;
421 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
422 clock-frequency = <0>;
423 fifo-size = <15>;
424 status = "disabled";
425 };
426
427 uart3: serial@21d0600 {
428 compatible = "fsl,16550-FIFO64", "ns16550a";
429 reg = <0x0 0x21d0600 0x0 0x100>;
430 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
431 clock-frequency = <0>;
432 fifo-size = <15>;
433 status = "disabled";
434 };
435
c54dd442
LG		 436 gpio0: gpio@2300000 {
437 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
438 reg = <0x0 0x2300000 0x0 0x10000>;
439 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
440 gpio-controller;
441 #gpio-cells = <2>;
442 interrupt-controller;
443 #interrupt-cells = <2>;
444 };
445
446 gpio1: gpio@2310000 {
447 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
448 reg = <0x0 0x2310000 0x0 0x10000>;
449 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
450 gpio-controller;
451 #gpio-cells = <2>;
452 interrupt-controller;
453 #interrupt-cells = <2>;
454 };
455
456 gpio2: gpio@2320000 {
457 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
458 reg = <0x0 0x2320000 0x0 0x10000>;
459 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
460 gpio-controller;
461 #gpio-cells = <2>;
462 interrupt-controller;
463 #interrupt-cells = <2>;
464 };
465
466 gpio3: gpio@2330000 {
467 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
468 reg = <0x0 0x2330000 0x0 0x10000>;
469 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
470 gpio-controller;
471 #gpio-cells = <2>;
472 interrupt-controller;
473 #interrupt-cells = <2>;
474 };
475
7239280c
JL		 476 lpuart0: serial@2950000 {
477 compatible = "fsl,ls1021a-lpuart";
478 reg = <0x0 0x2950000 0x0 0x1000>;
479 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
480 clocks = <&sysclk>;
481 clock-names = "ipg";
482 status = "disabled";
483 };
484
485 lpuart1: serial@2960000 {
486 compatible = "fsl,ls1021a-lpuart";
487 reg = <0x0 0x2960000 0x0 0x1000>;
488 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
b6f5e701 489 clocks = <&clockgen 4 1>;
7239280c
JL		 490 clock-names = "ipg";
491 status = "disabled";
492 };
493
494 lpuart2: serial@2970000 {
495 compatible = "fsl,ls1021a-lpuart";
496 reg = <0x0 0x2970000 0x0 0x1000>;
497 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
b6f5e701 498 clocks = <&clockgen 4 1>;
7239280c
JL		 499 clock-names = "ipg";
500 status = "disabled";
501 };
502
503 lpuart3: serial@2980000 {
504 compatible = "fsl,ls1021a-lpuart";
505 reg = <0x0 0x2980000 0x0 0x1000>;
506 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
b6f5e701 507 clocks = <&clockgen 4 1>;
7239280c
JL		 508 clock-names = "ipg";
509 status = "disabled";
510 };
511
512 lpuart4: serial@2990000 {
513 compatible = "fsl,ls1021a-lpuart";
514 reg = <0x0 0x2990000 0x0 0x1000>;
515 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
b6f5e701 516 clocks = <&clockgen 4 1>;
7239280c
JL		 517 clock-names = "ipg";
518 status = "disabled";
519 };
520
521 lpuart5: serial@29a0000 {
522 compatible = "fsl,ls1021a-lpuart";
523 reg = <0x0 0x29a0000 0x0 0x1000>;
524 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
b6f5e701 525 clocks = <&clockgen 4 1>;
7239280c
JL		 526 clock-names = "ipg";
527 status = "disabled";
528 };
529
530 wdog0: watchdog@2ad0000 {
531 compatible = "fsl,imx21-wdt";
532 reg = <0x0 0x2ad0000 0x0 0x10000>;
533 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
b6f5e701 534 clocks = <&clockgen 4 1>;
7239280c
JL		 535 clock-names = "wdog-en";
536 big-endian;
537 };
538
539 sai1: sai@2b50000 {
50897cb6 540 #sound-dai-cells = <0>;
7239280c
JL		 541 compatible = "fsl,vf610-sai";
542 reg = <0x0 0x2b50000 0x0 0x10000>;
543 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
b6f5e701
YT		 544 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
545 <&clockgen 4 1>, <&clockgen 4 1>;
50897cb6 546 clock-names = "bus", "mclk1", "mclk2", "mclk3";
7239280c
JL		 547 dma-names = "tx", "rx";
548 dmas = <&edma0 1 47>,
549 <&edma0 1 46>;
7239280c
JL		 550 status = "disabled";
551 };
552
553 sai2: sai@2b60000 {
50897cb6 554 #sound-dai-cells = <0>;
7239280c
JL		 555 compatible = "fsl,vf610-sai";
556 reg = <0x0 0x2b60000 0x0 0x10000>;
557 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
b6f5e701
YT		 558 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
559 <&clockgen 4 1>, <&clockgen 4 1>;
50897cb6 560 clock-names = "bus", "mclk1", "mclk2", "mclk3";
7239280c
JL		 561 dma-names = "tx", "rx";
562 dmas = <&edma0 1 45>,
563 <&edma0 1 44>;
7239280c
JL		 564 status = "disabled";
565 };
566
567 edma0: edma@2c00000 {
568 #dma-cells = <2>;
569 compatible = "fsl,vf610-edma";
570 reg = <0x0 0x2c00000 0x0 0x10000>,
571 <0x0 0x2c10000 0x0 0x10000>,
572 <0x0 0x2c20000 0x0 0x10000>;
573 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
574 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
575 interrupt-names = "edma-tx", "edma-err";
576 dma-channels = <32>;
577 big-endian;
578 clock-names = "dmamux0", "dmamux1";
b6f5e701
YT		 579 clocks = <&clockgen 4 1>,
580 <&clockgen 4 1>;
7239280c
JL		 581 };
582
ab0087df
MY		 583 dcu: dcu@2ce0000 {
584 compatible = "fsl,ls1021a-dcu";
585 reg = <0x0 0x2ce0000 0x0 0x10000>;
586 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
b6f5e701
YT		 587 clocks = <&clockgen 4 0>,
588 <&clockgen 4 0>;
5d01e99e 589 clock-names = "dcu", "pix";
ab0087df
MY		 590 big-endian;
591 status = "disabled";
592 };
593
7239280c
JL		 594 mdio0: mdio@2d24000 {
595 compatible = "gianfar";
596 device_type = "mdio";
597 #address-cells = <1>;
598 #size-cells = <0>;
55711961
EH		 599 reg = <0x0 0x2d24000 0x0 0x4000>,
600 <0x0 0x2d10030 0x0 0x4>;
7239280c
JL		 601 };
602
3db66fdc
YL		 603 ptp_clock@2d10e00 {
604 compatible = "fsl,etsec-ptp";
605 reg = <0x0 0x2d10e00 0x0 0xb0>;
606 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
607 fsl,tclk-period = <5>;
608 fsl,tmr-prsc = <2>;
609 fsl,tmr-add = <0xaaaaaaab>;
bdba5017 610 fsl,tmr-fiper1 = <999999995>;
3db66fdc
YL		 611 fsl,tmr-fiper2 = <99990>;
612 fsl,max-adj = <499999999>;
613 };
614
d69cb5d7
CM		 615 enet0: ethernet@2d10000 {
616 compatible = "fsl,etsec2";
617 device_type = "network";
618 #address-cells = <2>;
619 #size-cells = <2>;
620 interrupt-parent = <&gic>;
621 model = "eTSEC";
622 fsl,magic-packet;
623 ranges;
70b5ea97 624 dma-coherent;
d69cb5d7
CM		 625
626 queue-group@2d10000 {
627 #address-cells = <2>;
628 #size-cells = <2>;
629 reg = <0x0 0x2d10000 0x0 0x1000>;
630 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
631 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
632 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
633 };
634
635 queue-group@2d14000 {
636 #address-cells = <2>;
637 #size-cells = <2>;
638 reg = <0x0 0x2d14000 0x0 0x1000>;
639 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
640 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
641 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
642 };
643 };
644
645 enet1: ethernet@2d50000 {
646 compatible = "fsl,etsec2";
647 device_type = "network";
648 #address-cells = <2>;
649 #size-cells = <2>;
650 interrupt-parent = <&gic>;
651 model = "eTSEC";
652 ranges;
70b5ea97 653 dma-coherent;
d69cb5d7
CM		 654
655 queue-group@2d50000 {
656 #address-cells = <2>;
657 #size-cells = <2>;
658 reg = <0x0 0x2d50000 0x0 0x1000>;
659 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
660 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
661 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
662 };
663
664 queue-group@2d54000 {
665 #address-cells = <2>;
666 #size-cells = <2>;
667 reg = <0x0 0x2d54000 0x0 0x1000>;
668 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
669 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
670 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
671 };
672 };
673
674 enet2: ethernet@2d90000 {
675 compatible = "fsl,etsec2";
676 device_type = "network";
677 #address-cells = <2>;
678 #size-cells = <2>;
679 interrupt-parent = <&gic>;
680 model = "eTSEC";
681 ranges;
70b5ea97 682 dma-coherent;
d69cb5d7
CM		 683
684 queue-group@2d90000 {
685 #address-cells = <2>;
686 #size-cells = <2>;
687 reg = <0x0 0x2d90000 0x0 0x1000>;
688 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
689 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
690 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
691 };
692
693 queue-group@2d94000 {
694 #address-cells = <2>;
695 #size-cells = <2>;
696 reg = <0x0 0x2d94000 0x0 0x1000>;
697 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
698 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
699 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
700 };
701 };
702
31fa7631 703 usb2: usb@8600000 {
7239280c
JL		 704 compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
705 reg = <0x0 0x8600000 0x0 0x1000>;
706 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
707 dr_mode = "host";
708 phy_type = "ulpi";
709 };
710
31fa7631 711 usb3: usb3@3100000 {
7239280c
JL		 712 compatible = "snps,dwc3";
713 reg = <0x0 0x3100000 0x0 0x10000>;
714 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
715 dr_mode = "host";
607e266c 716 snps,quirk-frame-length-adjustment = <0x20>;
6f0808c4 717 snps,dis_rxdet_inp3_quirk;
7239280c 718 };
bc7abb47
ML		 719
720 pcie@3400000 {
4246bd46 721 compatible = "fsl,ls1021a-pcie";
bc7abb47
ML		 722 reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */
723 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
724 reg-names = "regs", "config";
725 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
726 fsl,pcie-scfg = <&scfg 0>;
727 #address-cells = <3>;
728 #size-cells = <2>;
729 device_type = "pci";
730 num-lanes = <4>;
731 bus-range = <0x0 0xff>;
732 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
733 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
df301588 734 msi-parent = <&msi1>, <&msi2>;
bc7abb47
ML		 735 #interrupt-cells = <1>;
736 interrupt-map-mask = <0 0 0 7>;
737 interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
738 <0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
739 <0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
740 <0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
8ab9c127 741 status = "disabled";
bc7abb47
ML		 742 };
743
744 pcie@3500000 {
4246bd46 745 compatible = "fsl,ls1021a-pcie";
bc7abb47
ML		 746 reg = <0x00 0x03500000 0x0 0x00010000 /* controller registers */
747 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
748 reg-names = "regs", "config";
749 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
750 fsl,pcie-scfg = <&scfg 1>;
751 #address-cells = <3>;
752 #size-cells = <2>;
753 device_type = "pci";
754 num-lanes = <4>;
755 bus-range = <0x0 0xff>;
756 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
757 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
df301588 758 msi-parent = <&msi1>, <&msi2>;
bc7abb47
ML		 759 #interrupt-cells = <1>;
760 interrupt-map-mask = <0 0 0 7>;
761 interrupt-map = <0000 0 0 1 &gic GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
762 <0000 0 0 2 &gic GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
763 <0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
764 <0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
8ab9c127 765 status = "disabled";
bc7abb47 766 };
fa2edcfb
PB		 767
768 can0: can@2a70000 {
769 compatible = "fsl,ls1021ar2-flexcan";
770 reg = <0x0 0x2a70000 0x0 0x1000>;
771 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
772 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
773 clock-names = "ipg", "per";
774 big-endian;
775 };
776
777 can1: can@2a80000 {
778 compatible = "fsl,ls1021ar2-flexcan";
779 reg = <0x0 0x2a80000 0x0 0x1000>;
780 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
781 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
782 clock-names = "ipg", "per";
783 big-endian;
784 };
785
786 can2: can@2a90000 {
787 compatible = "fsl,ls1021ar2-flexcan";
788 reg = <0x0 0x2a90000 0x0 0x1000>;
789 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
790 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
791 clock-names = "ipg", "per";
792 big-endian;
793 };
794
795 can3: can@2aa0000 {
796 compatible = "fsl,ls1021ar2-flexcan";
797 reg = <0x0 0x2aa0000 0x0 0x1000>;
798 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
799 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
800 clock-names = "ipg", "per";
801 big-endian;
802 };
35090321
RV		 803
804 ocram1: sram@10000000 {
805 compatible = "mmio-sram";
806 reg = <0x0 0x10000000 0x0 0x10000>;
807 #address-cells = <1>;
808 #size-cells = <1>;
809 ranges = <0x0 0x0 0x10000000 0x10000>;
810 };
811
812 ocram2: sram@10010000 {
813 compatible = "mmio-sram";
814 reg = <0x0 0x10010000 0x0 0x10000>;
815 #address-cells = <1>;
816 #size-cells = <1>;
817 ranges = <0x0 0x0 0x10010000 0x10000>;
818 };
7239280c
JL		 819 };
820};
Linux 6.x block layer and io_uring tree(s)