[linux-2.6-block.git] / arch / arm / boot / dts / imx6qdl-wandboard.dtsi

/*
 * Copyright 2013 Freescale Semiconductor, Inc.
 *
 * Author: Fabio Estevam <fabio.estevam@freescale.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */

#include <dt-bindings/gpio/gpio.h>

/ {
	regulators {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		reg_2p5v: regulator@0 {
			compatible = "regulator-fixed";
			reg = <0>;
			regulator-name = "2P5V";
			regulator-min-microvolt = <2500000>;
			regulator-max-microvolt = <2500000>;
			regulator-always-on;
		};

		reg_3p3v: regulator@1 {
			compatible = "regulator-fixed";
			reg = <1>;
			regulator-name = "3P3V";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			regulator-always-on;
		};
	};

	sound {
		compatible = "fsl,imx6-wandboard-sgtl5000",
			     "fsl,imx-audio-sgtl5000";
		model = "imx6-wandboard-sgtl5000";
		ssi-controller = <&ssi1>;
		audio-codec = <&codec>;
		audio-routing =
			"MIC_IN", "Mic Jack",
			"Mic Jack", "Mic Bias",
			"Headphone Jack", "HP_OUT";
		mux-int-port = <1>;
		mux-ext-port = <3>;
	};

	sound-spdif {
		compatible = "fsl,imx-audio-spdif";
		model = "imx-spdif";
		spdif-controller = <&spdif>;
		spdif-out;
	};
};

&audmux {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_audmux>;
	status = "okay";
};

&hdmi {
	ddc-i2c-bus = <&i2c1>;
	status = "okay";
};

&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";
};

&i2c2 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";

	codec: sgtl5000@0a {
		compatible = "fsl,sgtl5000";
		reg = <0x0a>;
		clocks = <&clks 201>;
		VDDA-supply = <&reg_2p5v>;
		VDDIO-supply = <&reg_3p3v>;
	};
};

&iomuxc {
	pinctrl-names = "default";

	imx6qdl-wandboard {

		pinctrl_audmux: audmuxgrp {
			fsl,pins = <
				MX6QDL_PAD_CSI0_DAT7__AUD3_RXD		0x130b0
				MX6QDL_PAD_CSI0_DAT4__AUD3_TXC		0x130b0
				MX6QDL_PAD_CSI0_DAT5__AUD3_TXD		0x110b0
				MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS		0x130b0
			>;
		};

		pinctrl_enet: enetgrp {
			fsl,pins = <
				MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
				MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b0b0
				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b0b0
				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b0b0
				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b0b0
				MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b0b0
				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b0b0
				MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0
				MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b0b0
				MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b0b0
				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0
				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0
				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b0b0
				MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8
				MX6QDL_PAD_GPIO_6__ENET_IRQ		0x000b1
			>;
		};

		pinctrl_i2c1: i2c1grp {
			fsl,pins = <
				MX6QDL_PAD_EIM_D21__I2C1_SCL 		0x4001b8b1
				MX6QDL_PAD_EIM_D28__I2C1_SDA 		0x4001b8b1
			>;
		};

		pinctrl_i2c2: i2c2grp {
			fsl,pins = <
				MX6QDL_PAD_KEY_COL3__I2C2_SCL		0x4001b8b1
				MX6QDL_PAD_KEY_ROW3__I2C2_SDA		0x4001b8b1
			>;
		};

		pinctrl_spdif: spdifgrp {
			fsl,pins = <
				MX6QDL_PAD_ENET_RXD0__SPDIF_OUT		0x1b0b0
			>;
		};

		pinctrl_uart1: uart1grp {
			fsl,pins = <
				MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA	0x1b0b1
				MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA	0x1b0b1
			>;
		};

		pinctrl_uart3: uart3grp {
			fsl,pins = <
				MX6QDL_PAD_EIM_D24__UART3_TX_DATA	0x1b0b1
				MX6QDL_PAD_EIM_D25__UART3_RX_DATA	0x1b0b1
				MX6QDL_PAD_EIM_D23__UART3_CTS_B		0x1b0b1
				MX6QDL_PAD_EIM_EB3__UART3_RTS_B		0x1b0b1
			>;
		};

		pinctrl_usbotg: usbotggrp {
			fsl,pins = <
				MX6QDL_PAD_GPIO_1__USB_OTG_ID		0x17059
			>;
		};

		pinctrl_usdhc1: usdhc1grp {
			fsl,pins = <
				MX6QDL_PAD_SD1_CMD__SD1_CMD		0x17059
				MX6QDL_PAD_SD1_CLK__SD1_CLK		0x10059
				MX6QDL_PAD_SD1_DAT0__SD1_DATA0		0x17059
				MX6QDL_PAD_SD1_DAT1__SD1_DATA1		0x17059
				MX6QDL_PAD_SD1_DAT2__SD1_DATA2		0x17059
				MX6QDL_PAD_SD1_DAT3__SD1_DATA3		0x17059
			>;
		};

		pinctrl_usdhc2: usdhc2grp {
			fsl,pins = <
				MX6QDL_PAD_SD2_CMD__SD2_CMD		0x17059
				MX6QDL_PAD_SD2_CLK__SD2_CLK		0x10059
				MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x17059
				MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x17059
				MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x17059
				MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x17059
			>;
		};

		pinctrl_usdhc3: usdhc3grp {
			fsl,pins = <
				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059
				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
			>;
		};
	};
};

&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet>;
	phy-mode = "rgmii";
	phy-reset-gpios = <&gpio3 29 0>;
	interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
			      <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
	status = "okay";
};

&spdif {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_spdif>;
	status = "okay";
};

&ssi1 {
	status = "okay";
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
};

&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	fsl,uart-has-rtscts;
	status = "okay";
};

&usbh1 {
	status = "okay";
};

&usbotg {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbotg>;
	disable-over-current;
	dr_mode = "peripheral";
	status = "okay";
};

&usdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc1>;
	cd-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
	status = "okay";
};

&usdhc3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc3>;
	cd-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>;
	status = "okay";
};
Commit	Line	Data
2688a32f FE	1	/*
	2	* Copyright 2013 Freescale Semiconductor, Inc.
	3	*
	4	* Author: Fabio Estevam <fabio.estevam@freescale.com>
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	*/
	11
89c1a8cf DA	12	#include <dt-bindings/gpio/gpio.h>
89c1a8cf DA	13
2688a32f FE	14	/ {
	15	regulators {
	16	compatible = "simple-bus";
56160e33 SG	17	#address-cells = <1>;
56160e33 SG	18	#size-cells = <0>;
2688a32f	19
56160e33	20	reg_2p5v: regulator@0 {
2688a32f	21	compatible = "regulator-fixed";
56160e33	22	reg = <0>;
2688a32f FE	23	regulator-name = "2P5V";
	24	regulator-min-microvolt = <2500000>;
	25	regulator-max-microvolt = <2500000>;
	26	regulator-always-on;
	27	};
	28
56160e33	29	reg_3p3v: regulator@1 {
2688a32f	30	compatible = "regulator-fixed";
56160e33	31	reg = <1>;
2688a32f FE	32	regulator-name = "3P3V";
	33	regulator-min-microvolt = <3300000>;
	34	regulator-max-microvolt = <3300000>;
	35	regulator-always-on;
	36	};
	37	};
	38
	39	sound {
	40	compatible = "fsl,imx6-wandboard-sgtl5000",
	41	"fsl,imx-audio-sgtl5000";
	42	model = "imx6-wandboard-sgtl5000";
	43	ssi-controller = <&ssi1>;
	44	audio-codec = <&codec>;
	45	audio-routing =
	46	"MIC_IN", "Mic Jack",
	47	"Mic Jack", "Mic Bias",
	48	"Headphone Jack", "HP_OUT";
	49	mux-int-port = <1>;
	50	mux-ext-port = <3>;
	51	};
c9d96df2 FE	52
	53	sound-spdif {
	54	compatible = "fsl,imx-audio-spdif";
	55	model = "imx-spdif";
	56	spdif-controller = <&spdif>;
	57	spdif-out;
	58	};
2688a32f FE	59	};
	60
	61	&audmux {
	62	pinctrl-names = "default";
817c27a1	63	pinctrl-0 = <&pinctrl_audmux>;
2688a32f FE	64	status = "okay";
	65	};
	66
fed687c5 FE	67	&hdmi {
	68	ddc-i2c-bus = <&i2c1>;
	69	status = "okay";
	70	};
	71
	72	&i2c1 {
	73	clock-frequency = <100000>;
	74	pinctrl-names = "default";
	75	pinctrl-0 = <&pinctrl_i2c1>;
	76	status = "okay";
	77	};
	78
2688a32f FE	79	&i2c2 {
	80	clock-frequency = <100000>;
	81	pinctrl-names = "default";
817c27a1	82	pinctrl-0 = <&pinctrl_i2c2>;
2688a32f FE	83	status = "okay";
	84
	85	codec: sgtl5000@0a {
	86	compatible = "fsl,sgtl5000";
	87	reg = <0x0a>;
a94f8ecb	88	clocks = <&clks 201>;
2688a32f FE	89	VDDA-supply = <&reg_2p5v>;
	90	VDDIO-supply = <&reg_3p3v>;
	91	};
	92	};
	93
	94	&iomuxc {
	95	pinctrl-names = "default";
2688a32f	96
817c27a1	97	imx6qdl-wandboard {
817c27a1 SG	98
	99	pinctrl_audmux: audmuxgrp {
	100	fsl,pins = <
77112dd5 NC	101	MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
	102	MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
	103	MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
	104	MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
817c27a1 SG	105	>;
	106	};
	107
	108	pinctrl_enet: enetgrp {
	109	fsl,pins = <
	110	MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
	111	MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
	112	MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
	113	MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
	114	MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
	115	MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
	116	MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
	117	MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
	118	MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
	119	MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
	120	MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
	121	MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
	122	MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
	123	MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
	124	MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
	125	MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
9fc77821	126	MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
817c27a1 SG	127	>;
	128	};
	129
fed687c5 FE	130	pinctrl_i2c1: i2c1grp {
	131	fsl,pins = <
	132	MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
	133	MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
	134	>;
	135	};
	136
817c27a1 SG	137	pinctrl_i2c2: i2c2grp {
	138	fsl,pins = <
	139	MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
	140	MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
	141	>;
	142	};
	143
	144	pinctrl_spdif: spdifgrp {
	145	fsl,pins = <
	146	MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1b0b0
	147	>;
	148	};
	149
	150	pinctrl_uart1: uart1grp {
	151	fsl,pins = <
	152	MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
	153	MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
	154	>;
	155	};
	156
	157	pinctrl_uart3: uart3grp {
	158	fsl,pins = <
	159	MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
	160	MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
	161	MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
	162	MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
	163	>;
	164	};
	165
	166	pinctrl_usbotg: usbotggrp {
	167	fsl,pins = <
	168	MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
	169	>;
	170	};
	171
	172	pinctrl_usdhc1: usdhc1grp {
	173	fsl,pins = <
	174	MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
	175	MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
	176	MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
	177	MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
	178	MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
	179	MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
	180	>;
	181	};
	182
	183	pinctrl_usdhc2: usdhc2grp {
	184	fsl,pins = <
	185	MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
	186	MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
	187	MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
	188	MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
	189	MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
	190	MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
	191	>;
	192	};
	193
	194	pinctrl_usdhc3: usdhc3grp {
	195	fsl,pins = <
	196	MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
	197	MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
	198	MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
	199	MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
	200	MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
201	MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
202	>;
203	};
2688a32f FE	204	};
	205	};
	206
	207	&fec {
	208	pinctrl-names = "default";
817c27a1	209	pinctrl-0 = <&pinctrl_enet>;
2688a32f	210	phy-mode = "rgmii";
80121372	211	phy-reset-gpios = <&gpio3 29 0>;
9fc77821 SS	212	interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
9fc77821 SS	213	<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
2688a32f FE	214	status = "okay";
	215	};
	216
c9d96df2 FE	217	&spdif {
c9d96df2 FE	218	pinctrl-names = "default";
817c27a1	219	pinctrl-0 = <&pinctrl_spdif>;
c9d96df2 FE	220	status = "okay";
	221	};
	222
2688a32f	223	&ssi1 {
2688a32f FE	224	status = "okay";
	225	};
	226
	227	&uart1 {
	228	pinctrl-names = "default";
817c27a1	229	pinctrl-0 = <&pinctrl_uart1>;
2688a32f FE	230	status = "okay";
	231	};
	232
	233	&uart3 {
	234	pinctrl-names = "default";
817c27a1	235	pinctrl-0 = <&pinctrl_uart3>;
2688a32f FE	236	fsl,uart-has-rtscts;
	237	status = "okay";
	238	};
	239
	240	&usbh1 {
	241	status = "okay";
	242	};
	243
e9ac890a FE	244	&usbotg {
e9ac890a FE	245	pinctrl-names = "default";
817c27a1	246	pinctrl-0 = <&pinctrl_usbotg>;
e9ac890a FE	247	disable-over-current;
	248	dr_mode = "peripheral";
	249	status = "okay";
	250	};
	251
2688a32f FE	252	&usdhc1 {
2688a32f FE	253	pinctrl-names = "default";
817c27a1	254	pinctrl-0 = <&pinctrl_usdhc1>;
89c1a8cf	255	cd-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
2688a32f FE	256	status = "okay";
	257	};
	258
2688a32f FE	259	&usdhc3 {
2688a32f FE	260	pinctrl-names = "default";
817c27a1	261	pinctrl-0 = <&pinctrl_usdhc3>;
89c1a8cf	262	cd-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>;
2688a32f FE	263	status = "okay";
2688a32f FE	264	};