[linux-2.6-block.git] / arch / arc / mm / tlbex.S

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * TLB Exception Handling for ARC
 *
 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
 *
 * Vineetg: April 2011 :
 *  -MMU v1: moved out legacy code into a seperate file
 *  -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore,
 *      helps avoid a shift when preparing PD0 from PTE
 *
 * Vineetg: July 2009
 *  -For MMU V2, we need not do heuristics at the time of commiting a D-TLB
 *   entry, so that it doesn't knock out it's I-TLB entry
 *  -Some more fine tuning:
 *   bmsk instead of add, asl.cc instead of branch, delay slot utilise etc
 *
 * Vineetg: July 2009
 *  -Practically rewrote the I/D TLB Miss handlers
 *   Now 40 and 135 instructions a peice as compared to 131 and 449 resp.
 *   Hence Leaner by 1.5 K
 *   Used Conditional arithmetic to replace excessive branching
 *   Also used short instructions wherever possible
 *
 * Vineetg: Aug 13th 2008
 *  -Passing ECR (Exception Cause REG) to do_page_fault( ) for printing
 *   more information in case of a Fatality
 *
 * Vineetg: March 25th Bug #92690
 *  -Added Debug Code to check if sw-ASID == hw-ASID

 * Rahul Trivedi, Amit Bhor: Codito Technologies 2004
 */

#include <linux/linkage.h>
#include <asm/entry.h>
#include <asm/mmu.h>
#include <asm/pgtable.h>
#include <asm/arcregs.h>
#include <asm/cache.h>
#include <asm/processor.h>
#include <asm/tlb-mmu1.h>

#ifdef CONFIG_ISA_ARCOMPACT
;-----------------------------------------------------------------
; ARC700 Exception Handling doesn't auto-switch stack and it only provides
; ONE scratch AUX reg "ARC_REG_SCRATCH_DATA0"
;
; For Non-SMP, the scratch AUX reg is repurposed to cache task PGD, so a
; "global" is used to free-up FIRST core reg to be able to code the rest of
; exception prologue (IRQ auto-disabled on Exceptions, so it's IRQ-safe).
; Since the Fast Path TLB Miss handler is coded with 4 regs, the remaining 3
; need to be saved as well by extending the "global" to be 4 words. Hence
;	".size   ex_saved_reg1, 16"
; [All of this dance is to avoid stack switching for each TLB Miss, since we
; only need to save only a handful of regs, as opposed to complete reg file]
;
; For ARC700 SMP, the "global" obviously can't be used for free up the FIRST
; core reg as it will not be SMP safe.
; Thus scratch AUX reg is used (and no longer used to cache task PGD).
; To save the rest of 3 regs - per cpu, the global is made "per-cpu".
; Epilogue thus has to locate the "per-cpu" storage for regs.
; To avoid cache line bouncing the per-cpu global is aligned/sized per
; L1_CACHE_SHIFT, despite fundamentally needing to be 12 bytes only. Hence
;	".size   ex_saved_reg1, (CONFIG_NR_CPUS << L1_CACHE_SHIFT)"

; As simple as that....
;--------------------------------------------------------------------------

; scratch memory to save [r0-r3] used to code TLB refill Handler
ARCFP_DATA ex_saved_reg1
	.align 1 << L1_CACHE_SHIFT
	.type   ex_saved_reg1, @object
#ifdef CONFIG_SMP
	.size   ex_saved_reg1, (CONFIG_NR_CPUS << L1_CACHE_SHIFT)
ex_saved_reg1:
	.zero (CONFIG_NR_CPUS << L1_CACHE_SHIFT)
#else
	.size   ex_saved_reg1, 16
ex_saved_reg1:
	.zero 16
#endif

.macro TLBMISS_FREEUP_REGS
#ifdef CONFIG_SMP
	sr  r0, [ARC_REG_SCRATCH_DATA0]	; freeup r0 to code with
	GET_CPU_ID  r0			; get to per cpu scratch mem,
	asl r0, r0, L1_CACHE_SHIFT	; cache line wide per cpu
	add r0, @ex_saved_reg1, r0
#else
	st    r0, [@ex_saved_reg1]
	mov_s r0, @ex_saved_reg1
#endif
	st_s  r1, [r0, 4]
	st_s  r2, [r0, 8]
	st_s  r3, [r0, 12]

	; VERIFY if the ASID in MMU-PID Reg is same as
	; one in Linux data structures

	tlb_paranoid_check_asm
.endm

.macro TLBMISS_RESTORE_REGS
#ifdef CONFIG_SMP
	GET_CPU_ID  r0			; get to per cpu scratch mem
	asl r0, r0, L1_CACHE_SHIFT	; each is cache line wide
	add r0, @ex_saved_reg1, r0
	ld_s  r3, [r0,12]
	ld_s  r2, [r0, 8]
	ld_s  r1, [r0, 4]
	lr    r0, [ARC_REG_SCRATCH_DATA0]
#else
	mov_s r0, @ex_saved_reg1
	ld_s  r3, [r0,12]
	ld_s  r2, [r0, 8]
	ld_s  r1, [r0, 4]
	ld_s  r0, [r0]
#endif
.endm

#else	/* ARCv2 */

.macro TLBMISS_FREEUP_REGS
	PUSH  r0
	PUSH  r1
	PUSH  r2
	PUSH  r3
.endm

.macro TLBMISS_RESTORE_REGS
	POP   r3
	POP   r2
	POP   r1
	POP   r0
.endm

#endif

;============================================================================
;  Troubleshooting Stuff
;============================================================================

; Linux keeps ASID (Address Space ID) in task->active_mm->context.asid
; When Creating TLB Entries, instead of doing 3 dependent loads from memory,
; we use the MMU PID Reg to get current ASID.
; In bizzare scenrios SW and HW ASID can get out-of-sync which is trouble.
; So we try to detect this in TLB Mis shandler

.macro tlb_paranoid_check_asm

#ifdef CONFIG_ARC_DBG_TLB_PARANOIA

	GET_CURR_TASK_ON_CPU  r3
	ld r0, [r3, TASK_ACT_MM]
	ld r0, [r0, MM_CTXT+MM_CTXT_ASID]
	breq r0, 0, 55f	; Error if no ASID allocated

	lr r1, [ARC_REG_PID]
	and r1, r1, 0xFF

	and r2, r0, 0xFF	; MMU PID bits only for comparison
	breq r1, r2, 5f

55:
	; Error if H/w and S/w ASID don't match, but NOT if in kernel mode
	lr  r2, [erstatus]
	bbit0 r2, STATUS_U_BIT, 5f

	; We sure are in troubled waters, Flag the error, but to do so
	; need to switch to kernel mode stack to call error routine
	GET_TSK_STACK_BASE   r3, sp

	; Call printk to shoutout aloud
	mov r2, 1
	j print_asid_mismatch

5:	; ASIDs match so proceed normally
	nop

#endif

.endm

;============================================================================
;TLB Miss handling Code
;============================================================================

;-----------------------------------------------------------------------------
; This macro does the page-table lookup for the faulting address.
; OUT: r0 = PTE faulted on, r1 = ptr to PTE, r2 = Faulting V-address
.macro LOAD_FAULT_PTE

	lr  r2, [efa]

#ifndef CONFIG_SMP
	lr  r1, [ARC_REG_SCRATCH_DATA0] ; current pgd
#else
	GET_CURR_TASK_ON_CPU  r1
	ld  r1, [r1, TASK_ACT_MM]
	ld  r1, [r1, MM_PGD]
#endif

	lsr     r0, r2, PGDIR_SHIFT     ; Bits for indexing into PGD
	ld.as   r3, [r1, r0]            ; PGD entry corresp to faulting addr
	tst	r3, r3
	bz	do_slow_path_pf         ; if no Page Table, do page fault

#ifdef CONFIG_TRANSPARENT_HUGEPAGE
	and.f	0, r3, _PAGE_HW_SZ	; Is this Huge PMD (thp)
	add2.nz	r1, r1, r0
	bnz.d	2f		; YES: PGD == PMD has THP PTE: stop pgd walk
	mov.nz	r0, r3

#endif
	and	r1, r3, PAGE_MASK

	; Get the PTE entry: The idea is
	; (1) x = addr >> PAGE_SHIFT 	-> masks page-off bits from @fault-addr
	; (2) y = x & (PTRS_PER_PTE - 1) -> to get index
	; (3) z = (pgtbl + y * 4)

#ifdef CONFIG_ARC_HAS_PAE40
#define PTE_SIZE_LOG	3	/* 8 == 2 ^ 3 */
#else
#define PTE_SIZE_LOG	2	/* 4 == 2 ^ 2 */
#endif

	; multiply in step (3) above avoided by shifting lesser in step (1)
	lsr     r0, r2, ( PAGE_SHIFT - PTE_SIZE_LOG )
	and     r0, r0, ( (PTRS_PER_PTE - 1) << PTE_SIZE_LOG )
	ld.aw   r0, [r1, r0]            ; r0: PTE (lower word only for PAE40)
					; r1: PTE ptr

2:

.endm

;-----------------------------------------------------------------
; Convert Linux PTE entry into TLB entry
; A one-word PTE entry is programmed as two-word TLB Entry [PD0:PD1] in mmu
;    (for PAE40, two-words PTE, while three-word TLB Entry [PD0:PD1:PD1HI])
; IN: r0 = PTE, r1 = ptr to PTE

.macro CONV_PTE_TO_TLB
	and    r3, r0, PTE_BITS_RWX	;          r  w  x
	asl    r2, r3, 3		; Kr Kw Kx 0  0  0 (GLOBAL, kernel only)
	and.f  0,  r0, _PAGE_GLOBAL
	or.z   r2, r2, r3		; Kr Kw Kx Ur Uw Ux (!GLOBAL, user page)

	and r3, r0, PTE_BITS_NON_RWX_IN_PD1 ; Extract PFN+cache bits from PTE
	or  r3, r3, r2

	sr  r3, [ARC_REG_TLBPD1]    	; paddr[31..13] | Kr Kw Kx Ur Uw Ux | C
#ifdef	CONFIG_ARC_HAS_PAE40
	ld	r3, [r1, 4]		; paddr[39..32]
	sr	r3, [ARC_REG_TLBPD1HI]
#endif

	and r2, r0, PTE_BITS_IN_PD0 ; Extract other PTE flags: (V)alid, (G)lb

	lr  r3,[ARC_REG_TLBPD0]     ; MMU prepares PD0 with vaddr and asid

	or  r3, r3, r2              ; S | vaddr | {sasid|asid}
	sr  r3,[ARC_REG_TLBPD0]     ; rewrite PD0
.endm

;-----------------------------------------------------------------
; Commit the TLB entry into MMU

.macro COMMIT_ENTRY_TO_MMU
#if (CONFIG_ARC_MMU_VER < 4)

#ifdef CONFIG_EZNPS_MTM_EXT
	/* verify if entry for this vaddr+ASID already exists */
	sr    TLBProbe, [ARC_REG_TLBCOMMAND]
	lr    r0, [ARC_REG_TLBINDEX]
	bbit0 r0, 31, 88f
#endif

	/* Get free TLB slot: Set = computed from vaddr, way = random */
	sr  TLBGetIndex, [ARC_REG_TLBCOMMAND]

	/* Commit the Write */
#if (CONFIG_ARC_MMU_VER >= 2)   /* introduced in v2 */
	sr TLBWriteNI, [ARC_REG_TLBCOMMAND]
#else
	sr TLBWrite, [ARC_REG_TLBCOMMAND]
#endif

#else
	sr TLBInsertEntry, [ARC_REG_TLBCOMMAND]
#endif

88:
.endm


ARCFP_CODE	;Fast Path Code, candidate for ICCM

;-----------------------------------------------------------------------------
; I-TLB Miss Exception Handler
;-----------------------------------------------------------------------------

ENTRY(EV_TLBMissI)

	TLBMISS_FREEUP_REGS

	;----------------------------------------------------------------
	; Get the PTE corresponding to V-addr accessed, r2 is setup with EFA
	LOAD_FAULT_PTE

	;----------------------------------------------------------------
	; VERIFY_PTE: Check if PTE permissions approp for executing code
	cmp_s   r2, VMALLOC_START
	mov_s   r2, (_PAGE_PRESENT | _PAGE_EXECUTE)
	or.hs   r2, r2, _PAGE_GLOBAL

	and     r3, r0, r2  ; Mask out NON Flag bits from PTE
	xor.f   r3, r3, r2  ; check ( ( pte & flags_test ) == flags_test )
	bnz     do_slow_path_pf

	; Let Linux VM know that the page was accessed
	or      r0, r0, _PAGE_ACCESSED  ; set Accessed Bit
	st_s    r0, [r1]                ; Write back PTE

	CONV_PTE_TO_TLB
	COMMIT_ENTRY_TO_MMU
	TLBMISS_RESTORE_REGS
EV_TLBMissI_fast_ret:	; additional label for VDK OS-kit instrumentation
	rtie

END(EV_TLBMissI)

;-----------------------------------------------------------------------------
; D-TLB Miss Exception Handler
;-----------------------------------------------------------------------------

ENTRY(EV_TLBMissD)

	TLBMISS_FREEUP_REGS

	;----------------------------------------------------------------
	; Get the PTE corresponding to V-addr accessed
	; If PTE exists, it will setup, r0 = PTE, r1 = Ptr to PTE, r2 = EFA
	LOAD_FAULT_PTE

	;----------------------------------------------------------------
	; VERIFY_PTE: Chk if PTE permissions approp for data access (R/W/R+W)

	cmp_s	r2, VMALLOC_START
	mov_s   r2, _PAGE_PRESENT	; common bit for K/U PTE
	or.hs	r2, r2, _PAGE_GLOBAL	; kernel PTE only

	; Linux PTE [RWX] bits are semantically overloaded:
	; -If PAGE_GLOBAL set, they refer to kernel-only flags (vmalloc)
	; -Otherwise they are user-mode permissions, and those are exactly
	;  same for kernel mode as well (e.g. copy_(to|from)_user)

	lr      r3, [ecr]
	btst_s  r3, ECR_C_BIT_DTLB_LD_MISS	; Read Access
	or.nz   r2, r2, _PAGE_READ      	; chk for Read flag in PTE
	btst_s  r3, ECR_C_BIT_DTLB_ST_MISS	; Write Access
	or.nz   r2, r2, _PAGE_WRITE     	; chk for Write flag in PTE
	; Above laddering takes care of XCHG access (both R and W)

	; By now, r2 setup with all the Flags we need to check in PTE
	and     r3, r0, r2              ; Mask out NON Flag bits from PTE
	brne.d  r3, r2, do_slow_path_pf ; is ((pte & flags_test) == flags_test)

	;----------------------------------------------------------------
	; UPDATE_PTE: Let Linux VM know that page was accessed/dirty
	lr      r3, [ecr]
	or      r0, r0, _PAGE_ACCESSED        ; Accessed bit always
	btst_s  r3,  ECR_C_BIT_DTLB_ST_MISS   ; See if it was a Write Access ?
	or.nz   r0, r0, _PAGE_DIRTY           ; if Write, set Dirty bit as well
	st_s    r0, [r1]                      ; Write back PTE

	CONV_PTE_TO_TLB

#if (CONFIG_ARC_MMU_VER == 1)
	; MMU with 2 way set assoc J-TLB, needs some help in pathetic case of
	; memcpy where 3 parties contend for 2 ways, ensuing a livelock.
	; But only for old MMU or one with Metal Fix
	TLB_WRITE_HEURISTICS
#endif

	COMMIT_ENTRY_TO_MMU
	TLBMISS_RESTORE_REGS
EV_TLBMissD_fast_ret:	; additional label for VDK OS-kit instrumentation
	rtie

;-------- Common routine to call Linux Page Fault Handler -----------
do_slow_path_pf:

#ifdef CONFIG_ISA_ARCV2
	; Set Z flag if exception in U mode. Hardware micro-ops do this on any
	; taken interrupt/exception, and thus is already the case at the entry
	; above, but ensuing code would have already clobbered.
	; EXCEPTION_PROLOGUE called in slow path, relies on correct Z flag set

	lr	r2, [erstatus]
	and	r2, r2, STATUS_U_MASK
	bxor.f	0, r2, STATUS_U_BIT
#endif

	; Restore the 4-scratch regs saved by fast path miss handler
	TLBMISS_RESTORE_REGS

	; Slow path TLB Miss handled as a regular ARC Exception
	; (stack switching / save the complete reg-file).
	b  call_do_page_fault
END(EV_TLBMissD)
Commit	Line	Data
d2912cb1	1	/* SPDX-License-Identifier: GPL-2.0-only */
cc562d2e VG	2	/*
	3	* TLB Exception Handling for ARC
	4	*
	5	* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
	6	*
cc562d2e VG	7	* Vineetg: April 2011 :
	8	* -MMU v1: moved out legacy code into a seperate file
	9	* -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore,
	10	* helps avoid a shift when preparing PD0 from PTE
	11	*
	12	* Vineetg: July 2009
	13	* -For MMU V2, we need not do heuristics at the time of commiting a D-TLB
	14	* entry, so that it doesn't knock out it's I-TLB entry
	15	* -Some more fine tuning:
	16	* bmsk instead of add, asl.cc instead of branch, delay slot utilise etc
	17	*
	18	* Vineetg: July 2009
	19	* -Practically rewrote the I/D TLB Miss handlers
	20	* Now 40 and 135 instructions a peice as compared to 131 and 449 resp.
	21	* Hence Leaner by 1.5 K
	22	* Used Conditional arithmetic to replace excessive branching
	23	* Also used short instructions wherever possible
	24	*
	25	* Vineetg: Aug 13th 2008
	26	* -Passing ECR (Exception Cause REG) to do_page_fault( ) for printing
	27	* more information in case of a Fatality
	28	*
	29	* Vineetg: March 25th Bug #92690
	30	* -Added Debug Code to check if sw-ASID == hw-ASID
	31
	32	* Rahul Trivedi, Amit Bhor: Codito Technologies 2004
	33	*/
	34
cc562d2e VG	35	#include <linux/linkage.h>
cc562d2e VG	36	#include <asm/entry.h>
da1677b0	37	#include <asm/mmu.h>
cc562d2e VG	38	#include <asm/pgtable.h>
	39	#include <asm/arcregs.h>
	40	#include <asm/cache.h>
	41	#include <asm/processor.h>
cc562d2e	42	#include <asm/tlb-mmu1.h>
cc562d2e	43
d7a512bf	44	#ifdef CONFIG_ISA_ARCOMPACT
4b06ff35 VG	45	;-----------------------------------------------------------------
	46	; ARC700 Exception Handling doesn't auto-switch stack and it only provides
	47	; ONE scratch AUX reg "ARC_REG_SCRATCH_DATA0"
	48	;
	49	; For Non-SMP, the scratch AUX reg is repurposed to cache task PGD, so a
	50	; "global" is used to free-up FIRST core reg to be able to code the rest of
	51	; exception prologue (IRQ auto-disabled on Exceptions, so it's IRQ-safe).
	52	; Since the Fast Path TLB Miss handler is coded with 4 regs, the remaining 3
	53	; need to be saved as well by extending the "global" to be 4 words. Hence
	54	; ".size ex_saved_reg1, 16"
	55	; [All of this dance is to avoid stack switching for each TLB Miss, since we
	56	; only need to save only a handful of regs, as opposed to complete reg file]
	57	;
	58	; For ARC700 SMP, the "global" obviously can't be used for free up the FIRST
	59	; core reg as it will not be SMP safe.
	60	; Thus scratch AUX reg is used (and no longer used to cache task PGD).
	61	; To save the rest of 3 regs - per cpu, the global is made "per-cpu".
	62	; Epilogue thus has to locate the "per-cpu" storage for regs.
	63	; To avoid cache line bouncing the per-cpu global is aligned/sized per
	64	; L1_CACHE_SHIFT, despite fundamentally needing to be 12 bytes only. Hence
	65	; ".size ex_saved_reg1, (CONFIG_NR_CPUS << L1_CACHE_SHIFT)"
	66
	67	; As simple as that....
cc562d2e VG	68	;--------------------------------------------------------------------------
cc562d2e VG	69
4b06ff35	70	; scratch memory to save [r0-r3] used to code TLB refill Handler
8b5850f8	71	ARCFP_DATA ex_saved_reg1
4b06ff35	72	.align 1 << L1_CACHE_SHIFT
cc562d2e	73	.type ex_saved_reg1, @object
41195d23 VG	74	#ifdef CONFIG_SMP
	75	.size ex_saved_reg1, (CONFIG_NR_CPUS << L1_CACHE_SHIFT)
	76	ex_saved_reg1:
	77	.zero (CONFIG_NR_CPUS << L1_CACHE_SHIFT)
	78	#else
cc562d2e VG	79	.size ex_saved_reg1, 16
	80	ex_saved_reg1:
	81	.zero 16
41195d23	82	#endif
cc562d2e	83
4b06ff35 VG	84	.macro TLBMISS_FREEUP_REGS
	85	#ifdef CONFIG_SMP
	86	sr r0, [ARC_REG_SCRATCH_DATA0] ; freeup r0 to code with
	87	GET_CPU_ID r0 ; get to per cpu scratch mem,
a6416f57	88	asl r0, r0, L1_CACHE_SHIFT ; cache line wide per cpu
4b06ff35 VG	89	add r0, @ex_saved_reg1, r0
	90	#else
	91	st r0, [@ex_saved_reg1]
	92	mov_s r0, @ex_saved_reg1
	93	#endif
	94	st_s r1, [r0, 4]
	95	st_s r2, [r0, 8]
	96	st_s r3, [r0, 12]
	97
	98	; VERIFY if the ASID in MMU-PID Reg is same as
	99	; one in Linux data structures
	100
5bd87adf	101	tlb_paranoid_check_asm
4b06ff35 VG	102	.endm
	103
	104	.macro TLBMISS_RESTORE_REGS
	105	#ifdef CONFIG_SMP
	106	GET_CPU_ID r0 ; get to per cpu scratch mem
a6416f57	107	asl r0, r0, L1_CACHE_SHIFT ; each is cache line wide
4b06ff35 VG	108	add r0, @ex_saved_reg1, r0
	109	ld_s r3, [r0,12]
	110	ld_s r2, [r0, 8]
	111	ld_s r1, [r0, 4]
	112	lr r0, [ARC_REG_SCRATCH_DATA0]
	113	#else
	114	mov_s r0, @ex_saved_reg1
	115	ld_s r3, [r0,12]
	116	ld_s r2, [r0, 8]
	117	ld_s r1, [r0, 4]
	118	ld_s r0, [r0]
	119	#endif
	120	.endm
	121
d7a512bf VG	122	#else /* ARCv2 */
	123
	124	.macro TLBMISS_FREEUP_REGS
	125	PUSH r0
	126	PUSH r1
	127	PUSH r2
	128	PUSH r3
	129	.endm
	130
	131	.macro TLBMISS_RESTORE_REGS
	132	POP r3
	133	POP r2
	134	POP r1
	135	POP r0
	136	.endm
	137
	138	#endif
	139
cc562d2e VG	140	;============================================================================
	141	; Troubleshooting Stuff
	142	;============================================================================
	143
	144	; Linux keeps ASID (Address Space ID) in task->active_mm->context.asid
	145	; When Creating TLB Entries, instead of doing 3 dependent loads from memory,
	146	; we use the MMU PID Reg to get current ASID.
	147	; In bizzare scenrios SW and HW ASID can get out-of-sync which is trouble.
	148	; So we try to detect this in TLB Mis shandler
	149
5bd87adf	150	.macro tlb_paranoid_check_asm
cc562d2e VG	151
	152	#ifdef CONFIG_ARC_DBG_TLB_PARANOIA
	153
cc562d2e VG	154	GET_CURR_TASK_ON_CPU r3
	155	ld r0, [r3, TASK_ACT_MM]
	156	ld r0, [r0, MM_CTXT+MM_CTXT_ASID]
947bf103	157	breq r0, 0, 55f ; Error if no ASID allocated
cc562d2e VG	158
	159	lr r1, [ARC_REG_PID]
	160	and r1, r1, 0xFF
5bd87adf	161
947bf103 VG	162	and r2, r0, 0xFF ; MMU PID bits only for comparison
947bf103 VG	163	breq r1, r2, 5f
cc562d2e	164
947bf103	165	55:
cc562d2e	166	; Error if H/w and S/w ASID don't match, but NOT if in kernel mode
5bd87adf VG	167	lr r2, [erstatus]
5bd87adf VG	168	bbit0 r2, STATUS_U_BIT, 5f
cc562d2e VG	169
	170	; We sure are in troubled waters, Flag the error, but to do so
	171	; need to switch to kernel mode stack to call error routine
	172	GET_TSK_STACK_BASE r3, sp
	173
	174	; Call printk to shoutout aloud
5bd87adf	175	mov r2, 1
cc562d2e VG	176	j print_asid_mismatch
cc562d2e VG	177
5bd87adf	178	5: ; ASIDs match so proceed normally
cc562d2e VG	179	nop
	180
	181	#endif
	182
	183	.endm
	184
	185	;============================================================================
	186	;TLB Miss handling Code
	187	;============================================================================
	188
	189	;-----------------------------------------------------------------------------
	190	; This macro does the page-table lookup for the faulting address.
	191	; OUT: r0 = PTE faulted on, r1 = ptr to PTE, r2 = Faulting V-address
	192	.macro LOAD_FAULT_PTE
	193
	194	lr r2, [efa]
	195
41195d23	196	#ifndef CONFIG_SMP
cc562d2e	197	lr r1, [ARC_REG_SCRATCH_DATA0] ; current pgd
41195d23 VG	198	#else
	199	GET_CURR_TASK_ON_CPU r1
	200	ld r1, [r1, TASK_ACT_MM]
	201	ld r1, [r1, MM_PGD]
	202	#endif
cc562d2e VG	203
cc562d2e VG	204	lsr r0, r2, PGDIR_SHIFT ; Bits for indexing into PGD
fe6c1b86 VG	205	ld.as r3, [r1, r0] ; PGD entry corresp to faulting addr
	206	tst r3, r3
	207	bz do_slow_path_pf ; if no Page Table, do page fault
	208
	209	#ifdef CONFIG_TRANSPARENT_HUGEPAGE
	210	and.f 0, r3, _PAGE_HW_SZ ; Is this Huge PMD (thp)
	211	add2.nz r1, r1, r0
	212	bnz.d 2f ; YES: PGD == PMD has THP PTE: stop pgd walk
	213	mov.nz r0, r3
	214
	215	#endif
	216	and r1, r3, PAGE_MASK
cc562d2e VG	217
	218	; Get the PTE entry: The idea is
	219	; (1) x = addr >> PAGE_SHIFT -> masks page-off bits from @fault-addr
	220	; (2) y = x & (PTRS_PER_PTE - 1) -> to get index
25d46418	221	; (3) z = (pgtbl + y * 4)
cc562d2e	222
5a364c2a VG	223	#ifdef CONFIG_ARC_HAS_PAE40
	224	#define PTE_SIZE_LOG 3 /* 8 == 2 ^ 3 */
	225	#else
25d46418	226	#define PTE_SIZE_LOG 2 /* 4 == 2 ^ 2 */
5a364c2a	227	#endif
25d46418 VG	228
	229	; multiply in step (3) above avoided by shifting lesser in step (1)
	230	lsr r0, r2, ( PAGE_SHIFT - PTE_SIZE_LOG )
	231	and r0, r0, ( (PTRS_PER_PTE - 1) << PTE_SIZE_LOG )
5a364c2a	232	ld.aw r0, [r1, r0] ; r0: PTE (lower word only for PAE40)
25d46418	233	; r1: PTE ptr
fe6c1b86 VG	234
	235	2:
	236
cc562d2e VG	237	.endm
	238
	239	;-----------------------------------------------------------------
	240	; Convert Linux PTE entry into TLB entry
	241	; A one-word PTE entry is programmed as two-word TLB Entry [PD0:PD1] in mmu
5a364c2a	242	; (for PAE40, two-words PTE, while three-word TLB Entry [PD0:PD1:PD1HI])
cc562d2e VG	243	; IN: r0 = PTE, r1 = ptr to PTE
	244
	245	.macro CONV_PTE_TO_TLB
25d46418	246	and r3, r0, PTE_BITS_RWX ; r w x
a6416f57	247	asl r2, r3, 3 ; Kr Kw Kx 0 0 0 (GLOBAL, kernel only)
64b703ef	248	and.f 0, r0, _PAGE_GLOBAL
25d46418	249	or.z r2, r2, r3 ; Kr Kw Kx Ur Uw Ux (!GLOBAL, user page)
64b703ef VG	250
	251	and r3, r0, PTE_BITS_NON_RWX_IN_PD1 ; Extract PFN+cache bits from PTE
	252	or r3, r3, r2
	253
25d46418	254	sr r3, [ARC_REG_TLBPD1] ; paddr[31..13] \| Kr Kw Kx Ur Uw Ux \| C
5a364c2a VG	255	#ifdef CONFIG_ARC_HAS_PAE40
	256	ld r3, [r1, 4] ; paddr[39..32]
	257	sr r3, [ARC_REG_TLBPD1HI]
	258	#endif
cc562d2e VG	259
cc562d2e VG	260	and r2, r0, PTE_BITS_IN_PD0 ; Extract other PTE flags: (V)alid, (G)lb
cc562d2e VG	261
	262	lr r3,[ARC_REG_TLBPD0] ; MMU prepares PD0 with vaddr and asid
	263
	264	or r3, r3, r2 ; S \| vaddr \| {sasid\|asid}
	265	sr r3,[ARC_REG_TLBPD0] ; rewrite PD0
	266	.endm
	267
	268	;-----------------------------------------------------------------
	269	; Commit the TLB entry into MMU
	270
	271	.macro COMMIT_ENTRY_TO_MMU
d7a512bf	272	#if (CONFIG_ARC_MMU_VER < 4)
cc562d2e	273
30b7af25 NC	274	#ifdef CONFIG_EZNPS_MTM_EXT
	275	/* verify if entry for this vaddr+ASID already exists */
	276	sr TLBProbe, [ARC_REG_TLBCOMMAND]
	277	lr r0, [ARC_REG_TLBINDEX]
	278	bbit0 r0, 31, 88f
	279	#endif
	280
cc562d2e VG	281	/* Get free TLB slot: Set = computed from vaddr, way = random */
	282	sr TLBGetIndex, [ARC_REG_TLBCOMMAND]
	283
	284	/* Commit the Write */
	285	#if (CONFIG_ARC_MMU_VER >= 2) /* introduced in v2 */
	286	sr TLBWriteNI, [ARC_REG_TLBCOMMAND]
	287	#else
	288	sr TLBWrite, [ARC_REG_TLBCOMMAND]
	289	#endif
d7a512bf VG	290
	291	#else
	292	sr TLBInsertEntry, [ARC_REG_TLBCOMMAND]
	293	#endif
30b7af25 NC	294
30b7af25 NC	295	88:
cc562d2e VG	296	.endm
cc562d2e VG	297
cc562d2e	298
8b5850f8	299	ARCFP_CODE ;Fast Path Code, candidate for ICCM
cc562d2e VG	300
	301	;-----------------------------------------------------------------------------
	302	; I-TLB Miss Exception Handler
	303	;-----------------------------------------------------------------------------
	304
ec7ac6af	305	ENTRY(EV_TLBMissI)
cc562d2e VG	306
	307	TLBMISS_FREEUP_REGS
	308
	309	;----------------------------------------------------------------
dc81df24	310	; Get the PTE corresponding to V-addr accessed, r2 is setup with EFA
cc562d2e VG	311	LOAD_FAULT_PTE
	312
	313	;----------------------------------------------------------------
	314	; VERIFY_PTE: Check if PTE permissions approp for executing code
	315	cmp_s r2, VMALLOC_START
64b703ef VG	316	mov_s r2, (_PAGE_PRESENT \| _PAGE_EXECUTE)
64b703ef VG	317	or.hs r2, r2, _PAGE_GLOBAL
cc562d2e VG	318
	319	and r3, r0, r2 ; Mask out NON Flag bits from PTE
	320	xor.f r3, r3, r2 ; check ( ( pte & flags_test ) == flags_test )
	321	bnz do_slow_path_pf
	322
	323	; Let Linux VM know that the page was accessed
c3e757a7 VG	324	or r0, r0, _PAGE_ACCESSED ; set Accessed Bit
c3e757a7 VG	325	st_s r0, [r1] ; Write back PTE
cc562d2e VG	326
	327	CONV_PTE_TO_TLB
	328	COMMIT_ENTRY_TO_MMU
	329	TLBMISS_RESTORE_REGS
2924cd18	330	EV_TLBMissI_fast_ret: ; additional label for VDK OS-kit instrumentation
cc562d2e VG	331	rtie
cc562d2e VG	332
ec7ac6af	333	END(EV_TLBMissI)
cc562d2e VG	334
	335	;-----------------------------------------------------------------------------
	336	; D-TLB Miss Exception Handler
	337	;-----------------------------------------------------------------------------
	338
ec7ac6af	339	ENTRY(EV_TLBMissD)
cc562d2e VG	340
	341	TLBMISS_FREEUP_REGS
	342
	343	;----------------------------------------------------------------
	344	; Get the PTE corresponding to V-addr accessed
dc81df24	345	; If PTE exists, it will setup, r0 = PTE, r1 = Ptr to PTE, r2 = EFA
cc562d2e VG	346	LOAD_FAULT_PTE
	347
	348	;----------------------------------------------------------------
	349	; VERIFY_PTE: Chk if PTE permissions approp for data access (R/W/R+W)
	350
64b703ef VG	351	cmp_s r2, VMALLOC_START
	352	mov_s r2, _PAGE_PRESENT ; common bit for K/U PTE
	353	or.hs r2, r2, _PAGE_GLOBAL ; kernel PTE only
	354
	355	; Linux PTE [RWX] bits are semantically overloaded:
	356	; -If PAGE_GLOBAL set, they refer to kernel-only flags (vmalloc)
	357	; -Otherwise they are user-mode permissions, and those are exactly
	358	; same for kernel mode as well (e.g. copy_(to\|from)_user)
	359
cc562d2e VG	360	lr r3, [ecr]
cc562d2e VG	361	btst_s r3, ECR_C_BIT_DTLB_LD_MISS ; Read Access
64b703ef	362	or.nz r2, r2, _PAGE_READ ; chk for Read flag in PTE
cc562d2e	363	btst_s r3, ECR_C_BIT_DTLB_ST_MISS ; Write Access
64b703ef VG	364	or.nz r2, r2, _PAGE_WRITE ; chk for Write flag in PTE
64b703ef VG	365	; Above laddering takes care of XCHG access (both R and W)
cc562d2e VG	366
	367	; By now, r2 setup with all the Flags we need to check in PTE
	368	and r3, r0, r2 ; Mask out NON Flag bits from PTE
	369	brne.d r3, r2, do_slow_path_pf ; is ((pte & flags_test) == flags_test)
	370
	371	;----------------------------------------------------------------
	372	; UPDATE_PTE: Let Linux VM know that page was accessed/dirty
	373	lr r3, [ecr]
c3e757a7	374	or r0, r0, _PAGE_ACCESSED ; Accessed bit always
cc562d2e	375	btst_s r3, ECR_C_BIT_DTLB_ST_MISS ; See if it was a Write Access ?
129cbed5	376	or.nz r0, r0, _PAGE_DIRTY ; if Write, set Dirty bit as well
cc562d2e VG	377	st_s r0, [r1] ; Write back PTE
	378
	379	CONV_PTE_TO_TLB
	380
	381	#if (CONFIG_ARC_MMU_VER == 1)
	382	; MMU with 2 way set assoc J-TLB, needs some help in pathetic case of
	383	; memcpy where 3 parties contend for 2 ways, ensuing a livelock.
	384	; But only for old MMU or one with Metal Fix
	385	TLB_WRITE_HEURISTICS
	386	#endif
	387
	388	COMMIT_ENTRY_TO_MMU
	389	TLBMISS_RESTORE_REGS
2924cd18	390	EV_TLBMissD_fast_ret: ; additional label for VDK OS-kit instrumentation
cc562d2e VG	391	rtie
	392
	393	;-------- Common routine to call Linux Page Fault Handler -----------
	394	do_slow_path_pf:
	395
23c0cbd0 VG	396	#ifdef CONFIG_ISA_ARCV2
	397	; Set Z flag if exception in U mode. Hardware micro-ops do this on any
	398	; taken interrupt/exception, and thus is already the case at the entry
	399	; above, but ensuing code would have already clobbered.
	400	; EXCEPTION_PROLOGUE called in slow path, relies on correct Z flag set
	401
	402	lr r2, [erstatus]
	403	and r2, r2, STATUS_U_MASK
	404	bxor.f 0, r2, STATUS_U_BIT
	405	#endif
	406
cc562d2e VG	407	; Restore the 4-scratch regs saved by fast path miss handler
	408	TLBMISS_RESTORE_REGS
	409
	410	; Slow path TLB Miss handled as a regular ARC Exception
	411	; (stack switching / save the complete reg-file).
a615b47d	412	b call_do_page_fault
ec7ac6af	413	END(EV_TLBMissD)