[linux-2.6-block.git] / arch / arc / mm / dma.c

/*
 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

/*
 * DMA Coherent API Notes
 *
 * I/O is inherently non-coherent on ARC. So a coherent DMA buffer is
 * implemented by accessintg it using a kernel virtual address, with
 * Cache bit off in the TLB entry.
 *
 * The default DMA address == Phy address which is 0x8000_0000 based.
 */

#include <linux/dma-mapping.h>
#include <linux/dma-debug.h>
#include <linux/export.h>
#include <asm/cacheflush.h>

/*
 * Helpers for Coherent DMA API.
 */
void *dma_alloc_noncoherent(struct device *dev, size_t size,
			    dma_addr_t *dma_handle, gfp_t gfp)
{
	void *paddr;

	/* This is linear addr (0x8000_0000 based) */
	paddr = alloc_pages_exact(size, gfp);
	if (!paddr)
		return NULL;

	/* This is bus address, platform dependent */
	*dma_handle = (dma_addr_t)paddr;

	return paddr;
}
EXPORT_SYMBOL(dma_alloc_noncoherent);

void dma_free_noncoherent(struct device *dev, size_t size, void *vaddr,
			  dma_addr_t dma_handle)
{
	free_pages_exact((void *)dma_handle, size);
}
EXPORT_SYMBOL(dma_free_noncoherent);

void *dma_alloc_coherent(struct device *dev, size_t size,
			 dma_addr_t *dma_handle, gfp_t gfp)
{
	void *paddr, *kvaddr;

	/* This is linear addr (0x8000_0000 based) */
	paddr = alloc_pages_exact(size, gfp);
	if (!paddr)
		return NULL;

	/* This is kernel Virtual address (0x7000_0000 based) */
	kvaddr = ioremap_nocache((unsigned long)paddr, size);
	if (kvaddr == NULL)
		return NULL;

	/* This is bus address, platform dependent */
	*dma_handle = (dma_addr_t)paddr;

	/*
	 * Evict any existing L1 and/or L2 lines for the backing page
	 * in case it was used earlier as a normal "cached" page.
	 * Yeah this bit us - STAR 9000898266
	 *
	 * Although core does call flush_cache_vmap(), it gets kvaddr hence
	 * can't be used to efficiently flush L1 and/or L2 which need paddr
	 * Currently flush_cache_vmap nukes the L1 cache completely which
	 * will be optimized as a separate commit
	 */
	dma_cache_wback_inv((unsigned long)paddr, size);

	return kvaddr;
}
EXPORT_SYMBOL(dma_alloc_coherent);

void dma_free_coherent(struct device *dev, size_t size, void *kvaddr,
		       dma_addr_t dma_handle)
{
	iounmap((void __force __iomem *)kvaddr);

	free_pages_exact((void *)dma_handle, size);
}
EXPORT_SYMBOL(dma_free_coherent);

/*
 * Helper for streaming DMA...
 */
void __arc_dma_cache_sync(unsigned long paddr, size_t size,
			  enum dma_data_direction dir)
{
	__inline_dma_cache_sync(paddr, size, dir);
}
EXPORT_SYMBOL(__arc_dma_cache_sync);
Commit	Line	Data
1162b070 VG	1	/*
	2	* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*/
	8
	9	/*
	10	* DMA Coherent API Notes
	11	*
	12	* I/O is inherently non-coherent on ARC. So a coherent DMA buffer is
	13	* implemented by accessintg it using a kernel virtual address, with
	14	* Cache bit off in the TLB entry.
	15	*
	16	* The default DMA address == Phy address which is 0x8000_0000 based.
1162b070 VG	17	*/
	18
	19	#include <linux/dma-mapping.h>
	20	#include <linux/dma-debug.h>
	21	#include <linux/export.h>
	22	#include <asm/cacheflush.h>
	23
	24	/*
	25	* Helpers for Coherent DMA API.
	26	*/
	27	void dma_alloc_noncoherent(struct device dev, size_t size,
	28	dma_addr_t *dma_handle, gfp_t gfp)
	29	{
	30	void *paddr;
	31
	32	/* This is linear addr (0x8000_0000 based) */
	33	paddr = alloc_pages_exact(size, gfp);
	34	if (!paddr)
	35	return NULL;
	36
	37	/* This is bus address, platform dependent */
454bfda9	38	*dma_handle = (dma_addr_t)paddr;
1162b070 VG	39
	40	return paddr;
	41	}
	42	EXPORT_SYMBOL(dma_alloc_noncoherent);
	43
	44	void dma_free_noncoherent(struct device dev, size_t size, void vaddr,
	45	dma_addr_t dma_handle)
	46	{
454bfda9	47	free_pages_exact((void *)dma_handle, size);
1162b070 VG	48	}
	49	EXPORT_SYMBOL(dma_free_noncoherent);
	50
	51	void dma_alloc_coherent(struct device dev, size_t size,
	52	dma_addr_t *dma_handle, gfp_t gfp)
	53	{
	54	void paddr, kvaddr;
	55
	56	/* This is linear addr (0x8000_0000 based) */
	57	paddr = alloc_pages_exact(size, gfp);
	58	if (!paddr)
	59	return NULL;
	60
	61	/* This is kernel Virtual address (0x7000_0000 based) */
	62	kvaddr = ioremap_nocache((unsigned long)paddr, size);
f718c2ef VG	63	if (kvaddr == NULL)
f718c2ef VG	64	return NULL;
1162b070 VG	65
1162b070 VG	66	/* This is bus address, platform dependent */
454bfda9	67	*dma_handle = (dma_addr_t)paddr;
1162b070	68
795f4558 VG	69	/*
	70	* Evict any existing L1 and/or L2 lines for the backing page
	71	* in case it was used earlier as a normal "cached" page.
	72	* Yeah this bit us - STAR 9000898266
	73	*
	74	* Although core does call flush_cache_vmap(), it gets kvaddr hence
	75	* can't be used to efficiently flush L1 and/or L2 which need paddr
	76	* Currently flush_cache_vmap nukes the L1 cache completely which
	77	* will be optimized as a separate commit
	78	*/
	79	dma_cache_wback_inv((unsigned long)paddr, size);
	80
1162b070 VG	81	return kvaddr;
	82	}
	83	EXPORT_SYMBOL(dma_alloc_coherent);
	84
	85	void dma_free_coherent(struct device dev, size_t size, void kvaddr,
	86	dma_addr_t dma_handle)
	87	{
	88	iounmap((void __force __iomem *)kvaddr);
	89
454bfda9	90	free_pages_exact((void *)dma_handle, size);
1162b070 VG	91	}
	92	EXPORT_SYMBOL(dma_free_coherent);
	93
	94	/*
	95	* Helper for streaming DMA...
	96	*/
	97	void __arc_dma_cache_sync(unsigned long paddr, size_t size,
	98	enum dma_data_direction dir)
	99	{
	100	__inline_dma_cache_sync(paddr, size, dir);
	101	}
	102	EXPORT_SYMBOL(__arc_dma_cache_sync);