[fio.git] / arch / arch-ppc.h

#ifndef ARCH_PPC_H
#define ARCH_PPC_H

#include <unistd.h>
#include <stdlib.h>
#include <sys/types.h>
#include <sys/wait.h>

#define FIO_ARCH	(arch_ppc)

#define nop	do { } while (0)

#ifdef __powerpc64__
#define read_barrier()	__asm__ __volatile__ ("lwsync" : : : "memory")
#else
#define read_barrier()	__asm__ __volatile__ ("sync" : : : "memory")
#endif

#define write_barrier()	__asm__ __volatile__ ("sync" : : : "memory")

#ifdef __powerpc64__
#define PPC_CNTLZL "cntlzd"
#else
#define PPC_CNTLZL "cntlzw"
#endif

static inline int __ilog2(unsigned long bitmask)
{
	int lz;

	asm (PPC_CNTLZL " %0,%1" : "=r" (lz) : "r" (bitmask));
	return BITS_PER_LONG - 1 - lz;
}

static inline int arch_ffz(unsigned long bitmask)
{
	if ((bitmask = ~bitmask) == 0)
		return BITS_PER_LONG;
	return  __ilog2(bitmask & -bitmask);
}

static inline unsigned int mfspr(unsigned int reg)
{
	unsigned int val;

	asm volatile("mfspr %0,%1": "=r" (val) : "K" (reg));
	return val;
}

#define SPRN_TBRL  0x10C /* Time Base Register Lower */
#define SPRN_TBRU  0x10D /* Time Base Register Upper */
#define SPRN_ATBL  0x20E /* Alternate Time Base Lower */
#define SPRN_ATBU  0x20F /* Alternate Time Base Upper */

#ifdef __powerpc64__
static inline unsigned long long get_cpu_clock(void)
{
	unsigned long long rval;

	asm volatile(
		"90:	mfspr %0, %1;\n"
		"	cmpwi %0,0;\n"
		"	beq-  90b;\n"
	: "=r" (rval)
	: "i" (SPRN_TBRL)
	: "cr0");

	return rval;
}
#else
static inline unsigned long long get_cpu_clock(void)
{
	unsigned int tbl, tbu0, tbu1;
	unsigned long long ret;

	do {
		if (arch_flags & ARCH_FLAG_1) {
			tbu0 = mfspr(SPRN_ATBU);
			tbl = mfspr(SPRN_ATBL);
			tbu1 = mfspr(SPRN_ATBU);
		} else {
			tbu0 = mfspr(SPRN_TBRU);
			tbl = mfspr(SPRN_TBRL);
			tbu1 = mfspr(SPRN_TBRU);
		}
	} while (tbu0 != tbu1);

	ret = (((unsigned long long)tbu0) << 32) | tbl;
	return ret;
}
#endif

#if 0
static void atb_child(void)
{
	arch_flags |= ARCH_FLAG_1;
	get_cpu_clock();
	_exit(0);
}

static void atb_clocktest(void)
{
	pid_t pid;

	pid = fork();
	if (!pid)
		atb_child();
	else if (pid != -1) {
		int status;

		pid = wait(&status);
		if (pid == -1 || !WIFEXITED(status))
			arch_flags &= ~ARCH_FLAG_1;
		else
			arch_flags |= ARCH_FLAG_1;
	}
}
#endif

#define ARCH_HAVE_INIT
extern bool tsc_reliable;

static inline int arch_init(char *envp[])
{
#if 0
	tsc_reliable = true;
	atb_clocktest();
#endif
	return 0;
}

#define ARCH_HAVE_FFZ

/*
 * We don't have it on all platforms, lets comment this out until we
 * can handle it more intelligently.
 *
 * #define ARCH_HAVE_CPU_CLOCK
 */

/*
 * Let's have it defined for ppc64
 */

#ifdef __powerpc64__
#define ARCH_HAVE_CPU_CLOCK
#endif

#endif
Commit	Line	Data
ebac4655	1	#ifndef ARCH_PPC_H
9ddf9439	2	#define ARCH_PPC_H
ebac4655	3
4247d1a9 JA	4	#include <unistd.h>
	5	#include <stdlib.h>
	6	#include <sys/types.h>
	7	#include <sys/wait.h>
	8
cca84643	9	#define FIO_ARCH (arch_ppc)
ebac4655	10
ebac4655 JA	11	#define nop do { } while (0)
ebac4655 JA	12
db6defc7	13	#ifdef __powerpc64__
44c47feb	14	#define read_barrier() __asm__ __volatile__ ("lwsync" : : : "memory")
db6defc7	15	#else
44c47feb	16	#define read_barrier() __asm__ __volatile__ ("sync" : : : "memory")
db6defc7 JA	17	#endif
db6defc7 JA	18
44c47feb JA	19	#define write_barrier() __asm__ __volatile__ ("sync" : : : "memory")
44c47feb JA	20
92060d6c CR	21	#ifdef __powerpc64__
	22	#define PPC_CNTLZL "cntlzd"
	23	#else
	24	#define PPC_CNTLZL "cntlzw"
	25	#endif
	26
8f7e39dd JA	27	static inline int __ilog2(unsigned long bitmask)
	28	{
	29	int lz;
	30
92060d6c CR	31	asm (PPC_CNTLZL " %0,%1" : "=r" (lz) : "r" (bitmask));
92060d6c CR	32	return BITS_PER_LONG - 1 - lz;
8f7e39dd JA	33	}
	34
	35	static inline int arch_ffz(unsigned long bitmask)
	36	{
	37	if ((bitmask = ~bitmask) == 0)
92060d6c	38	return BITS_PER_LONG;
8f7e39dd JA	39	return __ilog2(bitmask & -bitmask);
8f7e39dd JA	40	}
5f39d8f7	41
4247d1a9 JA	42	static inline unsigned int mfspr(unsigned int reg)
	43	{
	44	unsigned int val;
	45
	46	asm volatile("mfspr %0,%1": "=r" (val) : "K" (reg));
	47	return val;
	48	}
	49
	50	#define SPRN_TBRL 0x10C /* Time Base Register Lower */
	51	#define SPRN_TBRU 0x10D /* Time Base Register Upper */
	52	#define SPRN_ATBL 0x20E /* Alternate Time Base Lower */
	53	#define SPRN_ATBU 0x20F /* Alternate Time Base Upper */
	54
1c73ebea LZ	55	#ifdef __powerpc64__
	56	static inline unsigned long long get_cpu_clock(void)
	57	{
	58	unsigned long long rval;
	59
	60	asm volatile(
	61	"90: mfspr %0, %1;\n"
	62	" cmpwi %0,0;\n"
	63	" beq- 90b;\n"
	64	: "=r" (rval)
e8bf784a OH	65	: "i" (SPRN_TBRL)
e8bf784a OH	66	: "cr0");
1c73ebea LZ	67
	68	return rval;
	69	}
	70	#else
5f39d8f7 CC	71	static inline unsigned long long get_cpu_clock(void)
5f39d8f7 CC	72	{
2995607f JA	73	unsigned int tbl, tbu0, tbu1;
2995607f JA	74	unsigned long long ret;
5f39d8f7	75
2995607f	76	do {
4247d1a9 JA	77	if (arch_flags & ARCH_FLAG_1) {
	78	tbu0 = mfspr(SPRN_ATBU);
	79	tbl = mfspr(SPRN_ATBL);
	80	tbu1 = mfspr(SPRN_ATBU);
	81	} else {
f2dc46ad SN	82	tbu0 = mfspr(SPRN_TBRU);
	83	tbl = mfspr(SPRN_TBRL);
	84	tbu1 = mfspr(SPRN_TBRU);
4247d1a9	85	}
2995607f	86	} while (tbu0 != tbu1);
5f39d8f7	87
2995607f JA	88	ret = (((unsigned long long)tbu0) << 32) \| tbl;
2995607f JA	89	return ret;
5f39d8f7	90	}
1c73ebea	91	#endif
5f39d8f7	92
1b4f8c7f	93	#if 0
4247d1a9 JA	94	static void atb_child(void)
	95	{
	96	arch_flags \|= ARCH_FLAG_1;
	97	get_cpu_clock();
	98	_exit(0);
	99	}
	100
	101	static void atb_clocktest(void)
	102	{
	103	pid_t pid;
	104
	105	pid = fork();
	106	if (!pid)
	107	atb_child();
62443342	108	else if (pid != -1) {
4247d1a9 JA	109	int status;
4247d1a9 JA	110
62443342 JA	111	pid = wait(&status);
62443342 JA	112	if (pid == -1 \|\| !WIFEXITED(status))
4247d1a9 JA	113	arch_flags &= ~ARCH_FLAG_1;
	114	else
	115	arch_flags \|= ARCH_FLAG_1;
	116	}
	117	}
1b4f8c7f	118	#endif
4247d1a9	119
1b745f55	120	#define ARCH_HAVE_INIT
24575392	121	extern bool tsc_reliable;
4247d1a9	122
1b745f55 JA	123	static inline int arch_init(char *envp[])
1b745f55 JA	124	{
ddc0cc31	125	#if 0
24575392	126	tsc_reliable = true;
4247d1a9	127	atb_clocktest();
ddc0cc31	128	#endif
d20b2ca6	129	return 0;
1b745f55 JA	130	}
1b745f55 JA	131
8f7e39dd	132	#define ARCH_HAVE_FFZ
d2d982d3 JA	133
	134	/*
	135	* We don't have it on all platforms, lets comment this out until we
	136	* can handle it more intelligently.
	137	*
	138	* #define ARCH_HAVE_CPU_CLOCK
	139	*/
8f7e39dd	140
1c73ebea LZ	141	/*
	142	* Let's have it defined for ppc64
	143	*/
	144
	145	#ifdef __powerpc64__
	146	#define ARCH_HAVE_CPU_CLOCK
	147	#endif
	148
ebac4655	149	#endif