projects / linux-2.6-block.git / search
| 2024-05-13 | Anup Patel | of: property: Add fw_devlink support for interrupt... Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2024-04-14 | Anup Patel | irqchip/riscv-imsic: Fix boot time update effective... Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2024-03-26 | Anup Patel | RISC-V: KVM: Fix APLIC in_clrip[x] read emulation Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2024-03-25 | Anup Patel | MAINTAINERS: Add entry for RISC-V AIA drivers Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2024-03-25 | Anup Patel | RISC-V: Select APLIC and IMSIC drivers Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2024-03-25 | Anup Patel | irqchip/riscv-aplic: Add support for MSI-mode Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2024-03-25 | Anup Patel | irqchip: Add RISC-V advanced PLIC driver for direct... Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2024-03-25 | Anup Patel | dt-bindings: interrupt-controller: Add RISC-V advanced... Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2024-03-25 | Anup Patel | irqchip/riscv-imsic: Add device MSI domain support... Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2024-03-25 | Anup Patel | irqchip/riscv-imsic: Add device MSI domain support... Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2024-03-25 | Anup Patel | irqchip: Add RISC-V incoming MSI controller early driver Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2024-03-25 | Anup Patel | dt-bindings: interrupt-controller: Add RISC-V incoming... Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2024-03-25 | Anup Patel | RISC-V: KVM: Fix APLIC setipnum_le/be write emulation Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2024-03-06 | Anup Patel | KVM: riscv: selftests: Add Zacas extension to get-reg... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2024-03-06 | Anup Patel | RISC-V: KVM: Allow Zacas extension for Guest/VM Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2024-03-06 | Anup Patel | KVM: riscv: selftests: Add Ztso extension to get-reg... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2024-03-06 | Anup Patel | RISC-V: KVM: Allow Ztso extension for Guest/VM Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2024-03-06 | Anup Patel | RISC-V: KVM: Forward SEED CSR access to user space Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2024-02-27 | Anup Patel | irqchip/riscv-intc: Fix low-level interrupt handler... Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2024-02-23 | Anup Patel | irqchip/riscv-intc: Add support for RISC-V AIA Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2024-02-23 | Anup Patel | irqchip/sifive-plic: Improve locking safety by using... Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2024-02-23 | Anup Patel | irqchip/sifive-plic: Parse number of interrupts and... Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2024-02-23 | Anup Patel | irqchip/sifive-plic: Cleanup PLIC contexts upon irqdomain... Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2024-02-23 | Anup Patel | irqchip/sifive-plic: Use riscv_get_intc_hwnode() to... Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2024-02-23 | Anup Patel | irqchip/sifive-plic: Use devm_xyz() for managed allocation Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2024-02-23 | Anup Patel | irqchip/sifive-plic: Use dev_xyz() in-place of pr_xyz() Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2024-02-23 | Anup Patel | irqchip/sifive-plic: Convert PLIC driver into a platform... Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2024-01-19 | Anup Patel | KVM: riscv: selftests: Add Zfa extension to get-reg... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2024-01-19 | Anup Patel | RISC-V: KVM: Allow Zfa extension for Guest/VM Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2024-01-19 | Anup Patel | KVM: riscv: selftests: Add Zvfh[min] extensions to... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2024-01-19 | Anup Patel | RISC-V: KVM: Allow Zvfh[min] extensions for Guest/VM Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2024-01-19 | Anup Patel | KVM: riscv: selftests: Add Zihintntl extension to get... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2024-01-19 | Anup Patel | RISC-V: KVM: Allow Zihintntl extension for Guest/VM Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2024-01-19 | Anup Patel | KVM: riscv: selftests: Add Zfh[min] extensions to get... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2024-01-19 | Anup Patel | RISC-V: KVM: Allow Zfh[min] extensions for Guest/VM Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2024-01-19 | Anup Patel | KVM: riscv: selftests: Add vector crypto extensions... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2024-01-19 | Anup Patel | RISC-V: KVM: Allow vector crypto extensions for Guest/VM Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2024-01-19 | Anup Patel | KVM: riscv: selftests: Add scaler crypto extensions... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2024-01-19 | Anup Patel | RISC-V: KVM: Allow scalar crypto extensions for Guest/VM Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2024-01-19 | Anup Patel | KVM: riscv: selftests: Add Zbc extension to get-reg... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2024-01-19 | Anup Patel | RISC-V: KVM: Allow Zbc extension for Guest/VM Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2024-01-10 | Anup Patel | RISC-V: Enable SBI based earlycon support Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2024-01-10 | Anup Patel | tty/serial: Add RISC-V SBI debug console based earlycon Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2024-01-10 | Anup Patel | RISC-V: Add SBI debug console helper routines Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2024-01-10 | Anup Patel | RISC-V: Add stubs for sbi_console_putchar/getchar() Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2023-12-29 | Anup Patel | RISC-V: KVM: Fix indentation in kvm_riscv_vcpu_set_reg_csr() Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-12-29 | Anup Patel | KVM: riscv: selftests: Generate ISA extension reg_list... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-11-09 | Anup Patel | of: property: Add fw_devlink support for msi-parent Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2023-11-09 | Anup Patel | RISC-V: Don't fail in riscv_of_parent_hartid() for... Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2023-11-01 | Anup Patel | clocksource: timer-riscv: Increase rating of clock_event_dev... Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2023-11-01 | Anup Patel | clocksource: timer-riscv: Don't enable/disable timer... Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2023-10-27 | Anup Patel | irqchip/sifive-plic: Fix syscore registration for multi... Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2023-10-20 | Anup Patel | KVM: riscv: selftests: Add SBI DBCN extension to get... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-10-20 | Anup Patel | RISC-V: KVM: Forward SBI DBCN extension to user-space Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-10-20 | Anup Patel | RISC-V: KVM: Allow some SBI extensions to be disabled... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-10-20 | Anup Patel | RISC-V: KVM: Change the SBI specification version to... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-10-20 | Anup Patel | RISC-V: Add defines for SBI debug console extension Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-10-12 | Anup Patel | KVM: riscv: selftests: Add condops extensions to get... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-10-12 | Anup Patel | KVM: riscv: selftests: Add smstateen registers to get... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-10-12 | Anup Patel | KVM: riscv: selftests: Add senvcfg register to get... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-10-12 | Anup Patel | RISC-V: KVM: Allow Zicond extension for Guest/VM Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-10-12 | Anup Patel | dt-bindings: riscv: Add Zicond extension entry Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-10-12 | Anup Patel | RISC-V: Detect Zicond from ISA string Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-10-07 | Anup Patel | irqchip/riscv-intc: Mark all INTC nodes as initialized Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2023-09-21 | Anup Patel | KVM: riscv: selftests: Selectively filter-out AIA registers Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-09-21 | Anup Patel | KVM: riscv: selftests: Fix ISA_EXT register handling... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-09-21 | Anup Patel | RISC-V: KVM: Fix riscv_vcpu_get_isa_ext_single() for... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-09-21 | Anup Patel | RISC-V: KVM: Fix KVM_GET_REG_LIST API for ISA_EXT registers Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-08-08 | Anup Patel | RISC-V: KVM: Sort ISA extensions alphabetically in... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-08-08 | Anup Patel | RISC-V: KVM: Allow Zicntr, Zicsr, Zifencei, and Zihpm... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-08-08 | Anup Patel | RISC-V: KVM: Allow Zba and Zbs extensions for Guest/VM Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-08-08 | Anup Patel | RISC-V: KVM: Extend ONE_REG to enable/disable multiple... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-08-08 | Anup Patel | RISC-V: KVM: Factor-out ONE_REG related code to its... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-06-20 | Anup Patel | RISC-V: KVM: Allow Svnapot extension for Guest/VM Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-06-19 | Anup Patel | RISC-V: KVM: Expose IMSIC registers as attributes of... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-06-19 | Anup Patel | RISC-V: KVM: Add in-kernel virtualization of AIA IMSIC Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-06-18 | Anup Patel | RISC-V: KVM: Expose APLIC registers as attributes of... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-06-18 | Anup Patel | RISC-V: KVM: Add in-kernel emulation of AIA APLIC Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-06-18 | Anup Patel | RISC-V: KVM: Implement device interface for AIA irqchip Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-06-18 | Anup Patel | RISC-V: KVM: Skeletal in-kernel AIA irqchip support Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-06-18 | Anup Patel | RISC-V: KVM: Set kvm_riscv_aia_nr_hgei to zero Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-06-18 | Anup Patel | RISC-V: KVM: Add APLIC related defines Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-06-18 | Anup Patel | RISC-V: KVM: Add IMSIC related defines Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-06-18 | Anup Patel | RISC-V: KVM: Implement guest external interrupt line... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-04-21 | Anup Patel | RISC-V: KVM: Virtualize per-HART AIA CSRs Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-04-21 | Anup Patel | RISC-V: KVM: Use bitmap for irqs_pending and irqs_pending_mask Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-04-21 | Anup Patel | RISC-V: KVM: Add ONE_REG interface for AIA CSRs Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-04-21 | Anup Patel | RISC-V: KVM: Implement subtype for CSR ONE_REG interface Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-04-21 | Anup Patel | RISC-V: KVM: Initial skeletal support for AIA Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-04-21 | Anup Patel | RISC-V: KVM: Drop the _MASK suffix from hgatp.VMID... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-04-21 | Anup Patel | RISC-V: Detect AIA CSRs from ISA string Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-04-21 | Anup Patel | RISC-V: Add AIA related CSR defines Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-04-21 | Anup Patel | RISC-V: KVM: Allow Zbb extension for Guest/VM Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-04-21 | Anup Patel | RISC-V: KVM: Add ONE_REG interface to enable/disable... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-04-08 | Anup Patel | irqchip/riscv-intc: Add empty irq_eoi() for chained... Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2023-04-08 | Anup Patel | RISC-V: Use IPIs for remote icache flush when possible Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2023-04-08 | Anup Patel | RISC-V: Use IPIs for remote TLB flush when possible Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2023-04-08 | Anup Patel | RISC-V: Allow marking IPIs as suitable for remote FENCEs Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2023-04-08 | Anup Patel | RISC-V: Treat IPIs as normal Linux IRQs Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2023-04-08 | Anup Patel | irqchip/riscv-intc: Allow drivers to directly discover... Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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