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drm/i915: s/INTEL_OUTPUT_DISPLAYPORT/INTEL_OUTPUT_DP/
2016-07-07 Ville Syrjälädrm/i915: s/INTEL_OUTPUT_DISPLAYPORT/INTEL_OUTPUT_DP/
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2016-07-07 Ville Syrjälädrm/i915: Replace some open coded intel_crtc_has_dp_encoder()s
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2016-07-07 Ville Syrjälädrm/i915: Kill has_dp_encoder from pipe_config
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2016-07-07 Ville Syrjälädrm/i915: Replace manual lvds and sdvo/hdmi counting...
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2016-07-07 Ville Syrjälädrm/i915: Unify intel_pipe_has_type() and intel_pipe_will_ha...
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2016-07-07 Ville Syrjälädrm/i915: Add output_types bitmask into the crtc state
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2016-07-07 Ville Syrjälädrm/i915: Remove encoder type checks from MST suspend...
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2016-07-07 Ville Syrjälädrm/i915: Don't mark eDP encoders as MST capable
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2016-06-22 Ville Syrjälädrm/i915: Refresh cached DP port register value on...
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2016-06-07 David Weinehalldrm/i915: only disable memory self-refresh on GMCH
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2016-06-07 Ville Syrjälädrm/i915: Check VBT for port presence in addition to...
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2016-06-02 Ville Syrjälädrm/i915: Extract physical display dimensions from VBT
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2016-05-30 Ville Syrjälädrm/i915: kill STANDARD/CURSOR plane screams
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2016-05-30 Ville Syrjälädrm/i915: Give encoders useful names
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2016-05-30 Ville Syrjälädrm/i915: Give meaningful names to all the planes
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2016-05-30 Ville Syrjälädrm/i915: Don't leak primary/cursor planes on crtc...
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2016-05-30 Ville Syrjälädrm/i915: Set crtc->name to "pipe A", "pipe B", etc.
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2016-05-30 Ville Syrjälädrm/i915: Use plane->name in debug prints
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2016-05-30 Ville Syrjälädrm/i915: Use crtc->name in debug messages
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2016-05-27 Ville Syrjälädrm/i915: Reject modeset if the dotclock is too high
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2016-05-23 Ville Syrjälädrm/i915: Assert the dbuf is enabled when disabling...
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2016-05-23 Ville Syrjälädrm/i915: Set BXT cdclk to minimum initially
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2016-05-23 Ville Syrjälädrm/i915: Replace bxt_verify_cdclk_state() with a more...
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2016-05-23 Ville Syrjälädrm/i915: Make bxt_set_cdclk() operate in terms of...
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2016-05-23 Ville Syrjälädrm/i915: Rewrite broxton_get_display_clock_speed(...
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2016-05-23 Ville Syrjälädrm/i915: Update cached cdclk state from broxton_init_cdclk()
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2016-05-23 Ville Syrjälädrm/i915: Store BXT DE PLL vco and ref clocks in dev_priv
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2016-05-23 Ville Syrjälädrm/i915: Extract bxt DE PLL enable/disable from broxton_set...
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2016-05-23 Ville Syrjälädrm/i915: Store cdclk PLL reference clock under dev_priv
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2016-05-23 Ville Syrjälädrm/i915: Rename skl_vco_freq to cdclk_pll.vco
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2016-05-23 Ville Syrjälädrm/i915: Make 308 and 671 MHz cdclks more accurate...
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2016-05-23 Ville Syrjälädrm/i915: Move SKL+ DBUF enable/disable to display...
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2016-05-23 Ville Syrjälädrm/i915: Unify SKL cdclk init paths
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2016-05-23 Ville Syrjälädrm/i915: Beef up skl_sanitize_cdclk() a bit
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2016-05-23 Ville Syrjälädrm/i915: Keep track of preferred cdclk vco frequency...
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2016-05-23 Ville Syrjälädrm/i915: Allow enable/disable of DPLL0 around cdclk...
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2016-05-23 Ville Syrjälädrm/i915: Report the current DPLL0 vco on SKL/KBL
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2016-05-23 Ville Syrjälädrm/i915: Actually read out DPLL0 vco on skl from hardware
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2016-05-23 Ville Syrjälädrm/i915: Extract skl_calc_cdclk()
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2016-05-23 Ville Syrjälädrm/i915: Move the SKL DPLL0 VCO computation into intel_dp_c...
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2016-05-23 Clint Taylordrm/i915/skl: SKL CDCLK change on modeset tracking VCO
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2016-05-23 Ville Syrjälädrm/i915: Fix BXT min_pixclk after state readout
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2016-05-23 Ville Syrjälädrm/i915: Enable GSE interrupt on BDW+
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2016-05-13 Ville Syrjälädrm/i915: Eliminate the CDCLK_CTL RMW on BXT
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2016-05-13 Ville Syrjälädrm/i915: Program BXT_CDCLK_CD2X_PIPE
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2016-05-13 Ville Syrjälädrm/i915: s/required_vco/vco/ in skl cdclk code
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2016-05-13 Ville Syrjälädrm/i915: s/freq/cdclk/
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2016-05-13 Ville Syrjälädrm/i915: Kill off dead code from skl_dpll0_enable()
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2016-05-13 Ville Syrjälädrm/i915: Extract skl_dpll0_disable()
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2016-05-13 Ville Syrjälädrm/i915: Remove 10% cdclk guardband on BXT
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2016-05-13 Ville Syrjälädrm/i915: Use skl_cdclk_decimal() on bxt
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2016-05-13 Ville Syrjälädrm/i915: Use ilk_max_pixel_rate() for BXT cdclk calculation
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2016-05-13 Ville Syrjälädrm/i915: Don't pass dev_priv to broxton_calc_cdclk()
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2016-05-13 Ville Syrjälädrm/i915: Untangle .fdi_link_train and cdclk vfunc...
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2016-05-13 Ville Syrjälädrm/i915: Extract broadwell_calc_cdclk()
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2016-05-13 Ville Syrjälädrm/i915: Drop checks for max_pixclk failures in cdclk...
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2016-05-12 Ville Syrjälädrm/i915: s/DPPL/DPLL/ for SKL DPLLs
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2016-05-10 Ville Syrjälädrm/i915: Re-enable GGTT earlier during resume on pre...
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2016-05-09 Ville Syrjälädrm/i915: Add a FIXME about crtc !active vs. watermarks
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2016-05-09 Ville Syrjälädrm/i915: Calculate IPS linetime watermark based on...
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2016-05-09 Ville Syrjälädrm/i915: Determine DP++ type 1 DVI adaptor presence...
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2016-05-09 Ville Syrjälädrm/i915: Enable/disable TMDS output buffers in DP...
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2016-05-09 Ville Syrjälädrm/i915: Respect DP++ adaptor TMDS clock limit
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2016-05-09 Ville Syrjälädrm: Add helper for DP++ adaptors
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2016-04-28 Ville Syrjälädrm/i915: Fix comments about GMBUSFREQ register
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2016-04-28 Ville Syrjälädrm/i915: Use cached cdclk value in i915_audio_component_get...
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2016-04-28 Ville Syrjälädrm/i915: Update CDCLK_FREQ register on BDW after changing...
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2016-04-27 Ville Syrjälädrm/i915: Update RAWCLK_FREQ register on VLV/CHV
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2016-04-27 Ville Syrjälädrm/i915: Unify VLV/CHV DPOunit clock gating disable...
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2016-04-22 Ville Syrjälädrm/i915: Make RPS EI/thresholds multiple of 25 on...
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2016-04-22 Shashank Sharmadrm/i915: Fake HDMI live status
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2016-04-20 Mika Kaholadrm/i915: Fix eDP low vswing for Broadwell
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2016-04-19 Ville Syrjälädrm/i915: Wait for power cycle delay after turning...
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2016-04-19 Ville Syrjälädrm/i915: Define HSW/BDW display power domains the...
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2016-04-19 Ville Syrjälädrm/i915: Define VLV/CHV display power well domains...
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2016-04-19 Ville Syrjälädrm/i915: Set .domains=POWER_DOMAIN_MASK for the always...
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2016-04-19 Ville Syrjälädrm/i915: Fix oops in vlv_force_pll_on()
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2016-04-18 Ville Syrjälädrm/i915: Replace nondescript 'WARN_ON(!lret)' with...
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2016-04-15 Ville Syrjälädrm/i915: Reject 'Center' scaling mode for eDP/DSI...
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2016-04-15 Ville Syrjälädrm/i915: Hook up pfit for DSI
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2016-04-15 Ville Syrjälädrm/i915: Eliminate {vlv,bxt}_configure_dsi_pll()
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2016-04-15 Ville Syrjälädrm/i915: Compute DSI PLL parameters during .compute_config()
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2016-04-15 Ville Syrjälädrm/i915: Setup DPLL/DPLLMD for DSI too on VLV/CHV
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2016-04-14 Ville Syrjälädrm/i915: Use fw_domains_put_with_fifo() on HSW
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2016-04-14 Ville Syrjälädrm/i915: Split gen8_gt_irq_handler into ack+handle
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2016-04-14 Ville Syrjälädrm/i915: Eliminate passing dev+dev_priv to {snb,ilk...
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2016-04-14 Ville Syrjälädrm/i915: Move gt/pm irq handling out from irq disabled...
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2016-04-14 Ville Syrjälädrm/i915: Split VLV/CVH PIPESTAT handling into ack...
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2016-04-14 Ville Syrjälädrm/i915: Split PORT_HOTPLUG_STAT ack out from i9xx_hpd_irq_...
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2016-04-14 Ville Syrjälädrm/i915: Move variables to narrower scope in VLV/CHV...
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2016-04-14 Ville Syrjälädrm/i915: Eliminate loop from VLV irq handler
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2016-04-14 Ville Syrjälädrm/i915: Clear VLV_IER around irq processing
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2016-04-14 Ville Syrjälädrm/i915: Clear VLV_MASTER_IER around irq processing
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2016-04-14 Ville Syrjälädrm/i915: Clear VLV_IIR after PIPESTAT
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2016-04-14 Ville Syrjälädrm/i915: Set up VLV_MASTER_IER consistently
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2016-04-14 Ville Syrjälädrm/i915: Use GEN8_MASTER_IRQ_CONTROL consistently
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2016-04-14 Ville Syrjälädrm/i915: Ignore GTFIFODBG FIFO free entry fields on CHV
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2016-04-12 Ville Syrjälädrm/i915: Don't read out port_clock on CHV when DPLL...
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2016-04-12 Ville Syrjälädrm/i915: Dump pfit PGM_RATIOS as hex
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2016-04-12 Ville Syrjälädrm/i915: Fix CHV DSI PLL refclk during state readout
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