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powerpc/64s/exception: consolidate maskable and non-maskable prologs
authorNicholas Piggin <npiggin@gmail.com>
Sat, 22 Jun 2019 13:15:16 +0000 (23:15 +1000)
committerMichael Ellerman <mpe@ellerman.id.au>
Tue, 2 Jul 2019 10:24:42 +0000 (20:24 +1000)
Conditionally expand the soft-masking test if a mask is passed in.

No generated code change.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
arch/powerpc/include/asm/exception-64s.h patch | blob | blame | history
arch/powerpc/kernel/exceptions-64s.S patch | blob | blame | history

diff --git a/arch/powerpc/include/asm/exception-64s.h b/arch/powerpc/include/asm/exception-64s.h
index 0a29bf2db19801f39a51bb61a8cd09f491a03b52..4111888e04d71683549037e8bae597dea31d2c69 100644 (file)
--- a/arch/powerpc/include/asm/exception-64s.h
+++ b/arch/powerpc/include/asm/exception-64s.h
@@ -238,7 +238,7 @@
 #define EXCEPTION_RELON_PROLOG(area, label, hsrr, kvm, vec)            \
        SET_SCRATCH0(r13);              /* save r13 */                  \
        EXCEPTION_PROLOG_0(area);                                       \
-       EXCEPTION_PROLOG_1 hsrr, area, kvm, vec ;                       \
+       EXCEPTION_PROLOG_1 hsrr, area, kvm, vec, 0 ;                    \
        EXCEPTION_PROLOG_2_VIRT label, hsrr
 
 /* Exception register prefixes */
@@ -309,73 +309,51 @@ END_FTR_SECTION_NESTED(ftr,ftr,943)
        std     r10,area+EX_R10(r13);   /* save r10 - r12 */            \
        OPT_GET_SPR(r10, SPRN_CFAR, CPU_FTR_CFAR)
 
-#define __EXCEPTION_PROLOG_1_PRE(area)                                 \
-       OPT_SAVE_REG_TO_PACA(area+EX_PPR, r9, CPU_FTR_HAS_PPR);         \
-       OPT_SAVE_REG_TO_PACA(area+EX_CFAR, r10, CPU_FTR_CFAR);          \
-       INTERRUPT_TO_KERNEL;                                            \
-       SAVE_CTR(r10, area);                                            \
+.macro EXCEPTION_PROLOG_1 hsrr, area, kvm, vec, bitmask
+       OPT_SAVE_REG_TO_PACA(\area\()+EX_PPR, r9, CPU_FTR_HAS_PPR)
+       OPT_SAVE_REG_TO_PACA(\area\()+EX_CFAR, r10, CPU_FTR_CFAR)
+       INTERRUPT_TO_KERNEL
+       SAVE_CTR(r10, \area\())
        mfcr    r9
-
-#define __EXCEPTION_PROLOG_1_POST(area)                                        \
-       std     r11,area+EX_R11(r13);                                   \
-       std     r12,area+EX_R12(r13);                                   \
-       GET_SCRATCH0(r10);                                              \
-       std     r10,area+EX_R13(r13)
-
-/*
- * This version of the EXCEPTION_PROLOG_1 will carry
- * addition parameter called "bitmask" to support
- * checking of the interrupt maskable level.
- * Intended to be used in MASKABLE_EXCPETION_* macros.
- */
-.macro MASKABLE_EXCEPTION_PROLOG_1 hsrr, area, kvm, vec, bitmask
-       __EXCEPTION_PROLOG_1_PRE(\area\())
        .if \kvm
                KVMTEST \hsrr \vec
        .endif
 
-       lbz     r10,PACAIRQSOFTMASK(r13)
-       andi.   r10,r10,\bitmask
-       /* This associates vector numbers with bits in paca->irq_happened */
-       .if \vec == 0x500 || \vec == 0xea0
-       li      r10,PACA_IRQ_EE
-       .elseif \vec == 0x900
-       li      r10,PACA_IRQ_DEC
-       .elseif \vec == 0xa00 || \vec == 0xe80
-       li      r10,PACA_IRQ_DBELL
-       .elseif \vec == 0xe60
-       li      r10,PACA_IRQ_HMI
-       .elseif \vec == 0xf00
-       li      r10,PACA_IRQ_PMI
-       .else
-       .abort "Bad maskable vector"
-       .endif
-
-       .if \hsrr
-       bne     masked_Hinterrupt
-       .else
-       bne     masked_interrupt
+       .if \bitmask
+               lbz     r10,PACAIRQSOFTMASK(r13)
+               andi.   r10,r10,\bitmask
+               /* Associate vector numbers with bits in paca->irq_happened */
+               .if \vec == 0x500 || \vec == 0xea0
+               li      r10,PACA_IRQ_EE
+               .elseif \vec == 0x900
+               li      r10,PACA_IRQ_DEC
+               .elseif \vec == 0xa00 || \vec == 0xe80
+               li      r10,PACA_IRQ_DBELL
+               .elseif \vec == 0xe60
+               li      r10,PACA_IRQ_HMI
+               .elseif \vec == 0xf00
+               li      r10,PACA_IRQ_PMI
+               .else
+               .abort "Bad maskable vector"
+               .endif
+
+               .if \hsrr
+               bne     masked_Hinterrupt
+               .else
+               bne     masked_interrupt
+               .endif
        .endif
 
-       __EXCEPTION_PROLOG_1_POST(\area\())
-.endm
-
-/*
- * This version of the EXCEPTION_PROLOG_1 is intended
- * to be used in STD_EXCEPTION* macros
- */
-.macro EXCEPTION_PROLOG_1 hsrr, area, kvm, vec
-       __EXCEPTION_PROLOG_1_PRE(\area\())
-       .if \kvm
-               KVMTEST \hsrr \vec
-       .endif
-       __EXCEPTION_PROLOG_1_POST(\area\())
+       std     r11,\area\()+EX_R11(r13)
+       std     r12,\area\()+EX_R12(r13)
+       GET_SCRATCH0(r10)
+       std     r10,\area\()+EX_R13(r13)
 .endm
 
 #define EXCEPTION_PROLOG(area, label, hsrr, kvm, vec)                  \
        SET_SCRATCH0(r13);              /* save r13 */                  \
        EXCEPTION_PROLOG_0(area);                                       \
-       EXCEPTION_PROLOG_1 hsrr, area, kvm, vec ;                       \
+       EXCEPTION_PROLOG_1 hsrr, area, kvm, vec, 0 ;                    \
        EXCEPTION_PROLOG_2_REAL label, hsrr, 1
 
 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
@@ -444,7 +422,7 @@ END_FTR_SECTION_NESTED(ftr,ftr,943)
 /* Do not enable RI */
 #define EXCEPTION_PROLOG_NORI(area, label, hsrr, kvm, vec)             \
        EXCEPTION_PROLOG_0(area);                                       \
-       EXCEPTION_PROLOG_1 hsrr, area, kvm, vec ;                       \
+       EXCEPTION_PROLOG_1 hsrr, area, kvm, vec, 0 ;                    \
        EXCEPTION_PROLOG_2_REAL label, hsrr, 0
 
 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
@@ -599,14 +577,14 @@ END_FTR_SECTION_NESTED(ftr,ftr,943)
        b hdlr
 
 #define STD_EXCEPTION_OOL(vec, label)                          \
-       EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, vec ;        \
+       EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, vec, 0 ;     \
        EXCEPTION_PROLOG_2_REAL label, EXC_STD, 1
 
 #define STD_EXCEPTION_HV(loc, vec, label)                      \
        EXCEPTION_PROLOG(PACA_EXGEN, label, EXC_HV, 1, vec)
 
 #define STD_EXCEPTION_HV_OOL(vec, label)                       \
-       EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, vec ;         \
+       EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, vec, 0 ;      \
        EXCEPTION_PROLOG_2_REAL label, EXC_HV, 1
 
 #define STD_RELON_EXCEPTION(loc, vec, label)           \
@@ -614,54 +592,54 @@ END_FTR_SECTION_NESTED(ftr,ftr,943)
        EXCEPTION_RELON_PROLOG(PACA_EXGEN, label, EXC_STD, 0, vec)
 
 #define STD_RELON_EXCEPTION_OOL(vec, label)                    \
-       EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, vec ;        \
+       EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, vec, 0 ;     \
        EXCEPTION_PROLOG_2_VIRT label, EXC_STD
 
 #define STD_RELON_EXCEPTION_HV(loc, vec, label)                        \
        EXCEPTION_RELON_PROLOG(PACA_EXGEN, label, EXC_HV, 1, vec)
 
 #define STD_RELON_EXCEPTION_HV_OOL(vec, label)                 \
-       EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, vec;          \
+       EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, vec, 0 ;      \
        EXCEPTION_PROLOG_2_VIRT label, EXC_HV
 
 #define __MASKABLE_EXCEPTION(vec, label, hsrr, kvm, bitmask)           \
        SET_SCRATCH0(r13);    /* save r13 */                            \
        EXCEPTION_PROLOG_0(PACA_EXGEN);                                 \
-       MASKABLE_EXCEPTION_PROLOG_1 hsrr, PACA_EXGEN, kvm, vec, bitmask ; \
+       EXCEPTION_PROLOG_1 hsrr, PACA_EXGEN, kvm, vec, bitmask ;        \
        EXCEPTION_PROLOG_2_REAL label, hsrr, 1
 
 #define MASKABLE_EXCEPTION(vec, label, bitmask)                                \
        __MASKABLE_EXCEPTION(vec, label, EXC_STD, 1, bitmask)
 
 #define MASKABLE_EXCEPTION_OOL(vec, label, bitmask)                    \
-       MASKABLE_EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, vec, bitmask ; \
+       EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, vec, bitmask ;       \
        EXCEPTION_PROLOG_2_REAL label, EXC_STD, 1
 
 #define MASKABLE_EXCEPTION_HV(vec, label, bitmask)                     \
        __MASKABLE_EXCEPTION(vec, label, EXC_HV, 1, bitmask)
 
 #define MASKABLE_EXCEPTION_HV_OOL(vec, label, bitmask)                 \
-       MASKABLE_EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, vec, bitmask ; \
+       EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, vec, bitmask ;        \
        EXCEPTION_PROLOG_2_REAL label, EXC_HV, 1
 
 #define __MASKABLE_RELON_EXCEPTION(vec, label, hsrr, kvm, bitmask)     \
        SET_SCRATCH0(r13);    /* save r13 */                            \
        EXCEPTION_PROLOG_0(PACA_EXGEN);                                 \
-       MASKABLE_EXCEPTION_PROLOG_1 hsrr, PACA_EXGEN, kvm, vec, bitmask ; \
+       EXCEPTION_PROLOG_1 hsrr, PACA_EXGEN, kvm, vec, bitmask ;        \
        EXCEPTION_PROLOG_2_VIRT label, hsrr
 
 #define MASKABLE_RELON_EXCEPTION(vec, label, bitmask)                  \
        __MASKABLE_RELON_EXCEPTION(vec, label, EXC_STD, 0, bitmask)
 
 #define MASKABLE_RELON_EXCEPTION_OOL(vec, label, bitmask)              \
-       MASKABLE_EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, vec, bitmask ; \
+       EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, vec, bitmask ;       \
        EXCEPTION_PROLOG_2_REAL label, EXC_STD, 1
 
 #define MASKABLE_RELON_EXCEPTION_HV(vec, label, bitmask)               \
        __MASKABLE_RELON_EXCEPTION(vec, label, EXC_HV, 1, bitmask)
 
 #define MASKABLE_RELON_EXCEPTION_HV_OOL(vec, label, bitmask)           \
-       MASKABLE_EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, vec, bitmask ; \
+       EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, vec, bitmask ;        \
        EXCEPTION_PROLOG_2_VIRT label, EXC_HV
 
 /*
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index 23f5c39063edff7bb2ebca76a42bbcba63e8d55d..cc356a31d5cc0af92e1d5b573630deb688369fa9 100644 (file)
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -275,7 +275,7 @@ ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
 EXC_REAL_END(machine_check, 0x200, 0x100)
 EXC_VIRT_NONE(0x4200, 0x100)
 TRAMP_REAL_BEGIN(machine_check_common_early)
-       EXCEPTION_PROLOG_1 EXC_STD, PACA_EXMC, 0, 0x200
+       EXCEPTION_PROLOG_1 EXC_STD, PACA_EXMC, 0, 0x200, 0
        /*
         * Register contents:
         * R13          = PACA
@@ -360,7 +360,7 @@ BEGIN_FTR_SECTION
        b       machine_check_common_early
 END_FTR_SECTION_IFCLR(CPU_FTR_HVMODE)
 machine_check_pSeries_0:
-       EXCEPTION_PROLOG_1 EXC_STD, PACA_EXMC, 1, 0x200
+       EXCEPTION_PROLOG_1 EXC_STD, PACA_EXMC, 1, 0x200, 0
        /*
         * MSR_RI is not enabled, because PACA_EXMC is being used, so a
         * nested machine check corrupts it. machine_check_common enables
@@ -598,7 +598,7 @@ EXCEPTION_PROLOG_0(PACA_EXGEN)
 EXC_REAL_END(data_access, 0x300, 0x80)
 
 TRAMP_REAL_BEGIN(tramp_real_data_access)
-EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, 0x300
+EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, 0x300, 0
        /*
         * DAR/DSISR must be read before setting MSR[RI], because
         * a d-side MCE will clobber those registers so is not
@@ -613,7 +613,7 @@ EXCEPTION_PROLOG_2_REAL data_access_common, EXC_STD, 1
 EXC_VIRT_BEGIN(data_access, 0x4300, 0x80)
 SET_SCRATCH0(r13)              /* save r13 */
 EXCEPTION_PROLOG_0(PACA_EXGEN)
-EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, 0x300
+EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, 0x300, 0
        mfspr   r10,SPRN_DAR
        mfspr   r11,SPRN_DSISR
        std     r10,PACA_EXGEN+EX_DAR(r13)
@@ -652,7 +652,7 @@ EXCEPTION_PROLOG_0(PACA_EXSLB)
 EXC_REAL_END(data_access_slb, 0x380, 0x80)
 
 TRAMP_REAL_BEGIN(tramp_real_data_access_slb)
-EXCEPTION_PROLOG_1 EXC_STD, PACA_EXSLB, 1, 0x380
+EXCEPTION_PROLOG_1 EXC_STD, PACA_EXSLB, 1, 0x380, 0
        mfspr   r10,SPRN_DAR
        std     r10,PACA_EXSLB+EX_DAR(r13)
 EXCEPTION_PROLOG_2_REAL data_access_slb_common, EXC_STD, 1
@@ -660,7 +660,7 @@ EXCEPTION_PROLOG_2_REAL data_access_slb_common, EXC_STD, 1
 EXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x80)
 SET_SCRATCH0(r13)              /* save r13 */
 EXCEPTION_PROLOG_0(PACA_EXSLB)
-EXCEPTION_PROLOG_1 EXC_STD, PACA_EXSLB, 0, 0x380
+EXCEPTION_PROLOG_1 EXC_STD, PACA_EXSLB, 0, 0x380, 0
        mfspr   r10,SPRN_DAR
        std     r10,PACA_EXSLB+EX_DAR(r13)
 EXCEPTION_PROLOG_2_VIRT data_access_slb_common, EXC_STD
@@ -779,7 +779,7 @@ EXC_COMMON_ASYNC(hardware_interrupt_common, 0x500, do_IRQ)
 EXC_REAL_BEGIN(alignment, 0x600, 0x100)
 SET_SCRATCH0(r13)              /* save r13 */
 EXCEPTION_PROLOG_0(PACA_EXGEN)
-EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, 0x600
+EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, 0x600, 0
        mfspr   r10,SPRN_DAR
        mfspr   r11,SPRN_DSISR
        std     r10,PACA_EXGEN+EX_DAR(r13)
@@ -790,7 +790,7 @@ EXC_REAL_END(alignment, 0x600, 0x100)
 EXC_VIRT_BEGIN(alignment, 0x4600, 0x100)
 SET_SCRATCH0(r13)              /* save r13 */
 EXCEPTION_PROLOG_0(PACA_EXGEN)
-EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, 0x600
+EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, 0x600, 0
        mfspr   r10,SPRN_DAR
        mfspr   r11,SPRN_DSISR
        std     r10,PACA_EXGEN+EX_DAR(r13)
@@ -1119,7 +1119,7 @@ __TRAMP_REAL_OOL_MASKABLE_HV(hmi_exception, 0xe60, IRQS_DISABLED)
 EXC_VIRT_NONE(0x4e60, 0x20)
 TRAMP_KVM_HV(PACA_EXGEN, 0xe60)
 TRAMP_REAL_BEGIN(hmi_exception_early)
-       EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, 0xe60
+       EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, 0xe60, 0
        mr      r10,r1                  /* Save r1 */
        ld      r1,PACAEMERGSP(r13)     /* Use emergency stack for realmode */
        subi    r1,r1,INT_FRAME_SIZE    /* alloc stack frame            */
@@ -1321,7 +1321,7 @@ EXC_VIRT_NONE(0x5400, 0x100)
 EXC_REAL_BEGIN(denorm_exception_hv, 0x1500, 0x100)
        mtspr   SPRN_SPRG_HSCRATCH0,r13
        EXCEPTION_PROLOG_0(PACA_EXGEN)
-       EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 0, 0x1500
+       EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 0, 0x1500, 0
 
 #ifdef CONFIG_PPC_DENORMALISATION
        mfspr   r10,SPRN_HSRR1
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