IB/mlx4: Fix reading SL field out of cqe->sl_vid
authorRoland Dreier <rolandd@cisco.com>
Tue, 30 Dec 2008 23:30:26 +0000 (15:30 -0800)
committerRoland Dreier <rolandd@cisco.com>
Tue, 30 Dec 2008 23:30:26 +0000 (15:30 -0800)
Commit f780a9f1 ("mlx4_core: Add ethernet fields to CQE struct")
introduced a bug in how wc->sl is set in mlx4_ib_poll_one() -- since
cqe->sl_vid is a big-endian value, the shift must be done after
converting to host endianness.

This bug was found using sparse endianness checking.

Signed-off-by: Roland Dreier <rolandd@cisco.com>
drivers/infiniband/hw/mlx4/cq.c

index 8415ecce5c4c0ba5e646bea4e943f12ddcb94bdb..a3c5af1d7ec0afa72ae6d5f64bfaa21ee90e00ad 100644 (file)
@@ -699,7 +699,7 @@ repoll:
                }
 
                wc->slid           = be16_to_cpu(cqe->rlid);
-               wc->sl             = be16_to_cpu(cqe->sl_vid >> 12);
+               wc->sl             = be16_to_cpu(cqe->sl_vid) >> 12;
                g_mlpath_rqpn      = be32_to_cpu(cqe->g_mlpath_rqpn);
                wc->src_qp         = g_mlpath_rqpn & 0xffffff;
                wc->dlid_path_bits = (g_mlpath_rqpn >> 24) & 0x7f;