Merge tag 'iommu-updates-v3.12' of git://git.kernel.org/pub/scm/linux/kernel/git...

Pull IOMMU Updates from Joerg Roedel:
 "This round the updates contain:

   - A new driver for the Freescale PAMU IOMMU from Varun Sethi.

     This driver has cooked for a while and required changes to the
     IOMMU-API and infrastructure that were already merged before.

   - Updates for the ARM-SMMU driver from Will Deacon

   - Various fixes, the most important one is probably a fix from Alex
     Williamson for a memory leak in the VT-d page-table freeing code

  In summary not all that much.  The biggest part in the diffstat is the
  new PAMU driver"

* tag 'iommu-updates-v3.12' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu:
  intel-iommu: Fix leaks in pagetable freeing
  iommu/amd: Fix resource leak in iommu_init_device()
  iommu/amd: Clean up unnecessary MSI/MSI-X capability find
  iommu/arm-smmu: Simplify VMID and ASID allocation
  iommu/arm-smmu: Don't use VMIDs for stage-1 translations
  iommu/arm-smmu: Tighten up global fault reporting
  iommu/arm-smmu: Remove broken big-endian check
  iommu/fsl: Remove unnecessary 'fsl-pamu' prefixes
  iommu/fsl: Fix whitespace problems noticed by git-am
  iommu/fsl: Freescale PAMU driver and iommu implementation.
  iommu/fsl: Add additional iommu attributes required by the PAMU driver.
  powerpc: Add iommu domain pointer to device archdata
  iommu/exynos: Remove dead code (set_prefbuf)

diff --combined arch/powerpc/sysdev/fsl_pci.h
index defc422a375f1083703c47962c4a245b48284061,1e01291d060e39e7ce4af50e07c4d818cc9c604c..8d455df584711c84c004468be1656fd4b55e36eb
--- 1/arch/powerpc/sysdev/fsl_pci.h
--- 2/arch/powerpc/sysdev/fsl_pci.h
+++ b/arch/powerpc/sysdev/fsl_pci.h
@@@ -16,6 -16,11 +16,11 @@@
  
  struct platform_device;
  
+ 
+ /* FSL PCI controller BRR1 register */
+ #define PCI_FSL_BRR1      0xbf8
+ #define PCI_FSL_BRR1_VER 0xffff
+ 
  #define PCIE_LTSSM    0x0404          /* PCIE Link Training and Status */
  #define PCIE_LTSSM_L0 0x16            /* L0 state */
  #define PCIE_IP_REV_2_2               0x02080202 /* PCIE IP block version Rev2.2 */
@@@ -126,11 -131,5 +131,11 @@@ static inline int mpc85xx_pci_err_probe
  }
  #endif
  
 +#ifdef CONFIG_FSL_PCI
 +extern int fsl_pci_mcheck_exception(struct pt_regs *);
 +#else
 +static inline int fsl_pci_mcheck_exception(struct pt_regs *regs) {return 0; }
 +#endif
 +
  #endif /* __POWERPC_FSL_PCI_H */
  #endif /* __KERNEL__ */