mtd: spi-nor: add a quad_enable callback in struct flash_info

Some manufacturers may use different bit to set QE on different
memories.

The GD25Q256 from GigaDevice is an example, which uses S6(bit 6
of the Status Register-1) to set QE, which is different with
other supported memories from GigaDevice that use S9(bit 1 of
the Status Register-2). This makes it is impossible to select
the quad enable method by distinguishing the MFR. This patch
introduce a quad_enable function which can be set per memory
in the flash_info list table.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@wedev4u.fr>

diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 61fdd3c1a2bc16cb04d4f144efcfad6f9bcb60b0..a50ea46298e6297f3675c4c874c74a5a58283c46 100644 (file)
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -89,6 +89,8 @@ struct flash_info {
 #define NO_CHIP_ERASE          BIT(12) /* Chip does not support chip erase */
 #define SPI_NOR_SKIP_SFDP      BIT(13) /* Skip parsing of SFDP tables */
 #define USE_CLSR               BIT(14) /* use CLSR command */
+
+       int     (*quad_enable)(struct spi_nor *nor);
 };
 
 #define JEDEC_MFR(info)        ((info)->id[0])
@@ -2426,6 +2428,15 @@ static int spi_nor_init_params(struct spi_nor *nor,
                        params->quad_enable = spansion_quad_enable;
                        break;
                }
+
+               /*
+                * Some manufacturer like GigaDevice may use different
+                * bit to set QE on different memories, so the MFR can't
+                * indicate the quad_enable method for this case, we need
+                * set it in flash info list.
+                */
+               if (info->quad_enable)
+                       params->quad_enable = info->quad_enable;
        }
 
        /* Override the parameters with data read from SFDP tables. */