else
newmode.misc_output |= 0x80;
- rc = CalcStateExt(&par->riva, &newmode.ext, bpp, width,
+ rc = CalcStateExt(&par->riva, &newmode.ext, par->pdev, bpp, width,
hDisplaySize, height, dotClock);
if (rc)
goto out;
unsigned int chipset = par->Chipset;
struct pci_dev* dev;
u32 amt;
+ int domain = pci_domain_nr(par->pdev->bus);
switch (chip->Architecture) {
case NV_ARCH_03:
case NV_ARCH_30:
if(chipset == NV_CHIP_IGEFORCE2) {
- dev = pci_get_bus_and_slot(0, 1);
+ dev = pci_get_domain_bus_and_slot(domain, 0, 1);
pci_read_config_dword(dev, 0x7C, &amt);
pci_dev_put(dev);
memlen = (((amt >> 6) & 31) + 1) * 1024;
} else if (chipset == NV_CHIP_0x01F0) {
- dev = pci_get_bus_and_slot(0, 1);
+ dev = pci_get_domain_bus_and_slot(domain, 0, 1);
pci_read_config_dword(dev, 0x84, &amt);
pci_dev_put(dev);
memlen = (((amt >> 4) & 127) + 1) * 1024;
}
par->riva.flatPanel = (par->FlatPanel > 0) ? TRUE : FALSE;
- RivaGetConfig(&par->riva, par->Chipset);
+ RivaGetConfig(&par->riva, par->pdev, par->Chipset);
}
unsigned pixelDepth,
unsigned *burst,
unsigned *lwm,
- RIVA_HW_INST *chip
+ RIVA_HW_INST *chip,
+ struct pci_dev *pdev
)
{
nv10_fifo_info fifo_data;
unsigned int M, N, P, pll, MClk, NVClk;
unsigned int uMClkPostDiv;
struct pci_dev *dev;
+ int domain = pci_domain_nr(pdev->bus);
- dev = pci_get_bus_and_slot(0, 3);
+ dev = pci_get_domain_bus_and_slot(domain, 0, 3);
pci_read_config_dword(dev, 0x6C, &uMClkPostDiv);
pci_dev_put(dev);
uMClkPostDiv = (uMClkPostDiv >> 8) & 0xf;
sim_data.enable_video = 0;
sim_data.enable_mp = 0;
- dev = pci_get_bus_and_slot(0, 1);
+ dev = pci_get_domain_bus_and_slot(domain, 0, 1);
pci_read_config_dword(dev, 0x7C, &sim_data.memory_type);
pci_dev_put(dev);
sim_data.memory_type = (sim_data.memory_type >> 12) & 1;
(
RIVA_HW_INST *chip,
RIVA_HW_STATE *state,
+ struct pci_dev *pdev,
int bpp,
int width,
int hDisplaySize,
pixelDepth * 8,
&(state->arbitration0),
&(state->arbitration1),
- chip);
+ chip, pdev);
} else {
nv10UpdateArbitrationSettings(VClk,
pixelDepth * 8,
static void nv10GetConfig
(
RIVA_HW_INST *chip,
+ struct pci_dev *pdev,
unsigned int chipset
)
{
struct pci_dev* dev;
+ int domain = pci_domain_nr(pdev->bus);
u32 amt;
#ifdef __BIG_ENDIAN
* Fill in chip configuration.
*/
if(chipset == NV_CHIP_IGEFORCE2) {
- dev = pci_get_bus_and_slot(0, 1);
+ dev = pci_get_domain_bus_and_slot(domain, 0, 1);
pci_read_config_dword(dev, 0x7C, &amt);
pci_dev_put(dev);
chip->RamAmountKBytes = (((amt >> 6) & 31) + 1) * 1024;
} else if(chipset == NV_CHIP_0x01F0) {
- dev = pci_get_bus_and_slot(0, 1);
+ dev = pci_get_domain_bus_and_slot(domain, 0, 1);
pci_read_config_dword(dev, 0x84, &amt);
pci_dev_put(dev);
chip->RamAmountKBytes = (((amt >> 4) & 127) + 1) * 1024;
int RivaGetConfig
(
RIVA_HW_INST *chip,
+ struct pci_dev *pdev,
unsigned int chipset
)
{
case NV_ARCH_10:
case NV_ARCH_20:
case NV_ARCH_30:
- nv10GetConfig(chip, chipset);
+ nv10GetConfig(chip, pdev, chipset);
break;
default:
return (-1);