drm/radeon: Enable sdma preemption

This patch adds to radeon the enablement of sdma preemption.
This is needed to support HWS of SDMA user-mode queues.

Signed-off-by: Ben Goz <ben.goz@amd.com>
Signed-off-by: Oded Gabbay <oded.gabbay@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/radeon/cik_sdma.c b/drivers/gpu/drm/radeon/cik_sdma.c
index dde5c7e29eb200b6dc78f1fad46197e43e0013ed..1f4ded181662fa1774f57367c950e63e0d1470a9 100644 (file)
--- a/drivers/gpu/drm/radeon/cik_sdma.c
+++ b/drivers/gpu/drm/radeon/cik_sdma.c
@@ -282,6 +282,33 @@ static void cik_sdma_rlc_stop(struct radeon_device *rdev)
        /* XXX todo */
 }
 
+/**
+ * cik_sdma_ctx_switch_enable - enable/disable sdma engine preemption
+ *
+ * @rdev: radeon_device pointer
+ * @enable: enable/disable preemption.
+ *
+ * Halt or unhalt the async dma engines (CIK).
+ */
+void cik_sdma_ctx_switch_enable(struct radeon_device *rdev, bool enable)
+{
+       uint32_t reg_offset, value;
+       int i;
+
+       for (i = 0; i < 2; i++) {
+               if (i == 0)
+                       reg_offset = SDMA0_REGISTER_OFFSET;
+               else
+                       reg_offset = SDMA1_REGISTER_OFFSET;
+               value = RREG32(SDMA0_CNTL + reg_offset);
+               if (enable)
+                       value |= AUTO_CTXSW_ENABLE;
+               else
+                       value &= ~AUTO_CTXSW_ENABLE;
+               WREG32(SDMA0_CNTL + reg_offset, value);
+       }
+}
+
 /**
  * cik_sdma_enable - stop the async dma engines
  *
@@ -312,6 +339,8 @@ void cik_sdma_enable(struct radeon_device *rdev, bool enable)
                        me_cntl |= SDMA_HALT;
                WREG32(SDMA0_ME_CNTL + reg_offset, me_cntl);
        }
+
+       cik_sdma_ctx_switch_enable(rdev, enable);
 }
 
 /**