drm/amd/powerplay: add mode2 reset callback for pp_smu_mgr

Also define reset modes (0, 1 and 2)

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 07fd64aad2aed6872d5374cf670608399a397037..abeff15702778f46c951e9c214b8114930bb1ef8 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -189,6 +189,14 @@ struct phm_vce_clock_voltage_dependency_table {
        struct phm_vce_clock_voltage_dependency_record entries[1];
 };
 
+
+enum SMU_ASIC_RESET_MODE
+{
+    SMU_ASIC_RESET_MODE_0,
+    SMU_ASIC_RESET_MODE_1,
+    SMU_ASIC_RESET_MODE_2,
+};
+
 struct pp_smumgr_func {
        char *name;
        int (*smu_init)(struct pp_hwmgr  *hwmgr);
@@ -345,6 +353,7 @@ struct pp_hwmgr_func {
        int (*get_ppfeature_status)(struct pp_hwmgr *hwmgr, char *buf);
        int (*set_ppfeature_status)(struct pp_hwmgr *hwmgr, uint64_t ppfeature_masks);
        int (*set_mp1_state)(struct pp_hwmgr *hwmgr, enum pp_mp1_state mp1_state);
+       int (*asic_reset)(struct pp_hwmgr *hwmgr, enum SMU_ASIC_RESET_MODE mode);
 };
 
 struct pp_table_func {