Merge branch 'x86-pti-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
authorLinus Torvalds <torvalds@linux-foundation.org>
Thu, 15 Feb 2018 01:02:15 +0000 (17:02 -0800)
committerLinus Torvalds <torvalds@linux-foundation.org>
Thu, 15 Feb 2018 01:02:15 +0000 (17:02 -0800)
Pull x86 PTI and Spectre related fixes and updates from Ingo Molnar:
 "Here's the latest set of Spectre and PTI related fixes and updates:

  Spectre:
   - Add entry code register clearing to reduce the Spectre attack
     surface
   - Update the Spectre microcode blacklist
   - Inline the KVM Spectre helpers to get close to v4.14 performance
     again.
   - Fix indirect_branch_prediction_barrier()
   - Fix/improve Spectre related kernel messages
   - Fix array_index_nospec_mask() asm constraint
   - KVM: fix two MSR handling bugs

  PTI:
   - Fix a paranoid entry PTI CR3 handling bug
   - Fix comments

  objtool:
   - Fix paranoid_entry() frame pointer warning
   - Annotate WARN()-related UD2 as reachable
   - Various fixes
   - Add Add Peter Zijlstra as objtool co-maintainer

  Misc:
   - Various x86 entry code self-test fixes
   - Improve/simplify entry code stack frame generation and handling
     after recent heavy-handed PTI and Spectre changes. (There's two
     more WIP improvements expected here.)
   - Type fix for cache entries

  There's also some low risk non-fix changes I've included in this
  branch to reduce backporting conflicts:

   - rename a confusing x86_cpu field name
   - de-obfuscate the naming of single-TLB flushing primitives"

* 'x86-pti-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (41 commits)
  x86/entry/64: Fix CR3 restore in paranoid_exit()
  x86/cpu: Change type of x86_cache_size variable to unsigned int
  x86/spectre: Fix an error message
  x86/cpu: Rename cpu_data.x86_mask to cpu_data.x86_stepping
  selftests/x86/mpx: Fix incorrect bounds with old _sigfault
  x86/mm: Rename flush_tlb_single() and flush_tlb_one() to __flush_tlb_one_[user|kernel]()
  x86/speculation: Add <asm/msr-index.h> dependency
  nospec: Move array_index_nospec() parameter checking into separate macro
  x86/speculation: Fix up array_index_nospec_mask() asm constraint
  x86/debug: Use UD2 for WARN()
  x86/debug, objtool: Annotate WARN()-related UD2 as reachable
  objtool: Fix segfault in ignore_unreachable_insn()
  selftests/x86: Disable tests requiring 32-bit support on pure 64-bit systems
  selftests/x86: Do not rely on "int $0x80" in single_step_syscall.c
  selftests/x86: Do not rely on "int $0x80" in test_mremap_vdso.c
  selftests/x86: Fix build bug caused by the 5lvl test which has been moved to the VM directory
  selftests/x86/pkeys: Remove unused functions
  selftests/x86: Clean up and document sscanf() usage
  selftests/x86: Fix vDSO selftest segfault for vsyscall=none
  x86/entry/64: Remove the unused 'icebp' macro
  ...

18 files changed:
1  2 
MAINTAINERS
arch/x86/entry/entry_64.S
arch/x86/include/asm/acpi.h
arch/x86/include/asm/processor.h
arch/x86/kernel/cpu/amd.c
arch/x86/kernel/cpu/centaur.c
arch/x86/kernel/cpu/intel_rdt.c
arch/x86/kernel/mpparse.c
arch/x86/kvm/mmu.c
arch/x86/kvm/vmx.c
arch/x86/mm/init_64.c
arch/x86/mm/tlb.c
arch/x86/platform/uv/tlb_uv.c
drivers/cpufreq/longhaul.c
drivers/hwmon/coretemp.c
drivers/hwmon/k10temp.c
tools/objtool/check.c
tools/testing/selftests/x86/Makefile

diff --cc MAINTAINERS
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index 30c8c5344c4a5dcfeb96d0711a322e50de33d324,4fd9044e72e7857a549f04894153c386081d783b..8971bd64d515c5bb4a9b95108fd802b8418764f2
@@@ -688,13 -656,8 +656,12 @@@ GLOBAL(restore_regs_and_return_to_kerne
        ud2
  1:
  #endif
-       POP_EXTRA_REGS
-       POP_C_REGS
+       POP_REGS
        addq    $8, %rsp        /* skip regs->orig_ax */
 +      /*
 +       * ARCH_HAS_MEMBARRIER_SYNC_CORE rely on IRET core serialization
 +       * when returning from IPI handler.
 +       */
        INTERRUPT_RETURN
  
  ENTRY(native_iret)
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index f427723dc7db34fab153b4faecbbb767b48f7e06,91e3539cba024b910b4f3d23b726838e6060228f..3dec126aa3022eb11f49d5de695d3658183a48ee
@@@ -10136,7 -10127,12 +10136,10 @@@ static void nested_get_vmcs12_pages(str
                        (unsigned long)(vmcs12->posted_intr_desc_addr &
                        (PAGE_SIZE - 1)));
        }
-       if (!nested_vmx_prepare_msr_bitmap(vcpu, vmcs12))
 -      if (cpu_has_vmx_msr_bitmap() &&
 -          nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS) &&
 -          nested_vmx_merge_msr_bitmap(vcpu, vmcs12))
++      if (nested_vmx_prepare_msr_bitmap(vcpu, vmcs12))
+               vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
+                             CPU_BASED_USE_MSR_BITMAPS);
+       else
                vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
                                CPU_BASED_USE_MSR_BITMAPS);
  }
@@@ -10224,14 -10220,9 +10227,14 @@@ static inline bool nested_vmx_prepare_m
         *    updated to reflect this when L1 (or its L2s) actually write to
         *    the MSR.
         */
-       bool pred_cmd = msr_write_intercepted_l01(vcpu, MSR_IA32_PRED_CMD);
-       bool spec_ctrl = msr_write_intercepted_l01(vcpu, MSR_IA32_SPEC_CTRL);
+       bool pred_cmd = !msr_write_intercepted_l01(vcpu, MSR_IA32_PRED_CMD);
+       bool spec_ctrl = !msr_write_intercepted_l01(vcpu, MSR_IA32_SPEC_CTRL);
  
 +      /* Nothing to do if the MSR bitmap is not in use.  */
 +      if (!cpu_has_vmx_msr_bitmap() ||
 +          !nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
 +              return false;
 +
        if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
            !pred_cmd && !spec_ctrl)
                return false;
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index 10ca46df144921ee3bdc60aa6974802dfffa77e8,aa6e2d7f6a1fdc36e397a4cf5d43bc65068b6c13..d744991c0f4f44d56bda208ad3039ad81500f303
@@@ -23,30 -33,16 +33,28 @@@ BINARIES_64 := $(patsubst %,$(OUTPUT)/%
  
  CFLAGS := -O2 -g -std=gnu99 -pthread -Wall -no-pie
  
- UNAME_M := $(shell uname -m)
- CAN_BUILD_I386 := $(shell ./check_cc.sh $(CC) trivial_32bit_program.c -m32)
- CAN_BUILD_X86_64 := $(shell ./check_cc.sh $(CC) trivial_64bit_program.c)
 +define gen-target-rule-32
 +$(1) $(1)_32: $(OUTPUT)/$(1)_32
 +.PHONY: $(1) $(1)_32
 +endef
 +
 +define gen-target-rule-64
 +$(1) $(1)_64: $(OUTPUT)/$(1)_64
 +.PHONY: $(1) $(1)_64
 +endef
 +
  ifeq ($(CAN_BUILD_I386),1)
  all: all_32
  TEST_PROGS += $(BINARIES_32)
+ EXTRA_CFLAGS += -DCAN_BUILD_32
 +$(foreach t,$(TARGETS_C_32BIT_ALL),$(eval $(call gen-target-rule-32,$(t))))
  endif
  
  ifeq ($(CAN_BUILD_X86_64),1)
  all: all_64
  TEST_PROGS += $(BINARIES_64)
+ EXTRA_CFLAGS += -DCAN_BUILD_64
 +$(foreach t,$(TARGETS_C_64BIT_ALL),$(eval $(call gen-target-rule-64,$(t))))
  endif
  
  all_32: $(BINARIES_32)