drm/amd/powerplay: add feature check in unforce_dpm_levels function (v2)
authorKevin Wang <kevin1.wang@amd.com>
Mon, 17 Jun 2019 05:05:00 +0000 (13:05 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 25 Jun 2019 18:54:32 +0000 (13:54 -0500)
if not check dpm feature is enabled, it will cause show smc send message
failed log in dmesg log.
eg:
echo "auto" > power_dpm_force_performance_level

v2: whitespace fix (Alex)

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Rui Teng <rui.teng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/powerplay/navi10_ppt.c

index 953209b7c3eb5be5c036f2ea034466b012a5e9c7..d1246981e3ac0ab9741d412eaaa7209a922fbb94 100644 (file)
@@ -815,14 +815,21 @@ static int navi10_unforce_dpm_levels(struct smu_context *smu) {
        uint32_t min_freq, max_freq;
        enum smu_clk_type clk_type;
 
-       enum smu_clk_type clks[] = {
-               SMU_GFXCLK,
-               SMU_MCLK,
-               SMU_SOCCLK,
+       struct clk_feature_map {
+               enum smu_clk_type clk_type;
+               uint32_t        feature;
+       } clk_feature_map[] = {
+               {SMU_GFXCLK, SMU_FEATURE_DPM_GFXCLK_BIT},
+               {SMU_MCLK,   SMU_FEATURE_DPM_UCLK_BIT},
+               {SMU_SOCCLK, SMU_FEATURE_DPM_SOCCLK_BIT},
        };
 
-       for (i = 0; i < ARRAY_SIZE(clks); i++) {
-               clk_type = clks[i];
+       for (i = 0; i < ARRAY_SIZE(clk_feature_map); i++) {
+               if (!smu_feature_is_enabled(smu, clk_feature_map[i].feature))
+                       continue;
+
+               clk_type = clk_feature_map[i].clk_type;
+
                ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq);
                if (ret)
                        return ret;