ARM: dts: ls1021: Fix SGMII PCS link remaining down after PHY disconnect
authorVladimir Oltean <olteanv@gmail.com>
Thu, 11 Apr 2019 23:23:14 +0000 (02:23 +0300)
committerShawn Guo <shawnguo@kernel.org>
Sun, 21 Apr 2019 07:51:28 +0000 (15:51 +0800)
Each eTSEC MAC has its own TBI (SGMII) PCS and private MDIO bus.
But due to a DTS oversight, both SGMII-compatible MACs of the LS1021 SoC
are pointing towards the same internal PCS. Therefore nobody is
controlling the internal PCS of eTSEC0.

Upon initial ndo_open, the SGMII link is ok by virtue of U-boot
initialization. But upon an ifdown/ifup sequence, the code path from
ndo_open -> init_phy -> gfar_configure_serdes does not get executed for
the PCS of eTSEC0 (and is executed twice for MAC eTSEC1). So the SGMII
link remains down for eTSEC0. On the LS1021A-TWR board, to signal this
failure condition, the PHY driver keeps printing
'803x_aneg_done: SGMII link is not ok'.

Also, it changes compatible of mdio0 to "fsl,etsec2-mdio" to match
mdio1 device.

Fixes: 055223d4d22d ("ARM: dts: ls1021a: Enable the eTSEC ports on QDS and TWR")
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Reviewed-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Acked-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
arch/arm/boot/dts/ls1021a-twr.dts
arch/arm/boot/dts/ls1021a.dtsi

index 97e1fb7ea932430bc127475d18f288086d3f8e10..9b1fe99d55b1e677a393665aafbefe2d91f8d601 100644 (file)
 };
 
 &enet0 {
-       tbi-handle = <&tbi1>;
+       tbi-handle = <&tbi0>;
        phy-handle = <&sgmii_phy2>;
        phy-connection-type = "sgmii";
        status = "okay";
        sgmii_phy2: ethernet-phy@2 {
                reg = <0x2>;
        };
+       tbi0: tbi-phy@1f {
+               reg = <0x1f>;
+               device_type = "tbi-phy";
+       };
+};
+
+&mdio1 {
        tbi1: tbi-phy@1f {
                reg = <0x1f>;
                device_type = "tbi-phy";
index b4f2723ecd8632ae17cfb56511d388c2c4468d1b..89eab1fd1f7f2416e3b5dc2f522854748c7694a6 100644 (file)
                };
 
                mdio0: mdio@2d24000 {
-                       compatible = "gianfar";
+                       compatible = "fsl,etsec2-mdio";
                        device_type = "mdio";
                        #address-cells = <1>;
                        #size-cells = <0>;
                              <0x0 0x2d10030 0x0 0x4>;
                };
 
+               mdio1: mdio@2d64000 {
+                       compatible = "fsl,etsec2-mdio";
+                       device_type = "mdio";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x0 0x2d64000 0x0 0x4000>,
+                             <0x0 0x2d50030 0x0 0x4>;
+               };
+
                ptp_clock@2d10e00 {
                        compatible = "fsl,etsec-ptp";
                        reg = <0x0 0x2d10e00 0x0 0xb0>;