pwm: img: Test clock rate to avoid division by 0

The clk API may return 0 on clk_get_rate(), so we should check the
result before using it as a divisor.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>

diff --git a/drivers/pwm/pwm-img.c b/drivers/pwm/pwm-img.c
index 8a029f9bc18cb0f0c2c95bc7ea4d9167164326be..2fb30deee3457017a22c1cea394cfd2e6e1cab77 100644 (file)
--- a/drivers/pwm/pwm-img.c
+++ b/drivers/pwm/pwm-img.c
@@ -237,6 +237,11 @@ static int img_pwm_probe(struct platform_device *pdev)
        }
 
        clk_rate = clk_get_rate(pwm->pwm_clk);
+       if (!clk_rate) {
+               dev_err(&pdev->dev, "pwm clock has no frequency\n");
+               ret = -EINVAL;
+               goto disable_pwmclk;
+       }
 
        /* The maximum input clock divider is 512 */
        val = (u64)NSEC_PER_SEC * 512 * pwm->data->max_timebase;