MIPS: DEC: Update CPU overrides

Update CPU overrides for the DEC port with the recent additions, shaving
off some effectively dead code:

   text    data      bss      dec     hex filename
5586952  233132  5990368 11810452  b43694 vmlinux.32-old
5581248  233140  5990368 11804756  b42054 vmlinux.32-new

   text    data      bss      dec     hex filename
6036936  356648 10756544 17150128 105b0b0 vmlinux.64-old
6029896  360752 10756544 17147192 105a538 vmlinux.64-new

The data size increase is due to the special alignment requirement of
`init_thread_union' aka `.data..init_task' moving it up to the nearest
page boundary and making the amount of padding at its front rely on how
far within a page text ends.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10197/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h b/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h
index bdf045fb00c8001de485b98a7720de19789aa8b8..21eae03d752aa695bb841c755e31f20a5ca8a972 100644 (file)
--- a/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h
@@ -14,6 +14,13 @@
 
 /* Generic ones first.  */
 #define cpu_has_tlb                    1
+#define cpu_has_tlbinv                 0
+#define cpu_has_segments               0
+#define cpu_has_eva                    0
+#define cpu_has_htw                    0
+#define cpu_has_rixiex                 0
+#define cpu_has_maar                   0
+#define cpu_has_rw_llb                 0
 #define cpu_has_tx39_cache             0
 #define cpu_has_divec                  0
 #define cpu_has_prefetch               0
@@ -24,6 +31,7 @@
 #define cpu_has_mips3d                 0
 #define cpu_has_smartmips              0
 #define cpu_has_rixi                   0
+#define cpu_has_xpa                    0
 #define cpu_has_vtag_icache            0
 #define cpu_has_ic_fills_f_dc          0
 #define cpu_has_pindexed_dcache                0
@@ -36,11 +44,18 @@
 #define cpu_has_mips64r1               0
 #define cpu_has_mips64r2               0
 #define cpu_has_dsp                    0
+#define cpu_has_dsp2                   0
 #define cpu_has_mipsmt                 0
 #define cpu_has_userlocal              0
+#define cpu_hwrena_impl_bits           0
+#define cpu_has_perf_cntr_intr_bit     0
+#define cpu_has_vz                     0
+#define cpu_has_fre                    0
+#define cpu_has_cdmm                   0
 
 /* R3k-specific ones.  */
 #ifdef CONFIG_CPU_R3000
+#define cpu_has_3kex                   1
 #define cpu_has_4kex                   0
 #define cpu_has_3k_cache               1
 #define cpu_has_4k_cache               0
@@ -63,6 +78,7 @@
 
 /* R4k-specific ones.  */
 #ifdef CONFIG_CPU_R4X00
+#define cpu_has_3kex                   0
 #define cpu_has_4kex                   1
 #define cpu_has_3k_cache               0
 #define cpu_has_4k_cache               1