staging: mt7621-pci: use BIT macro in preprocessor definitions

Some preprocessor definitions are using a custom implementation of
BIT macro. Just use linux kernel BIT macro instead.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Tested-by: NeilBrown <neil@brown.name>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 972a8024a1ae3b2e2ee3381810555657f94dd113..c288b26db16d734fd56474028d7ac4ef8e749cdc 100644 (file)
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -62,17 +62,17 @@
  * devices.
  */
 
-#define RALINK_PCIE0_CLK_EN            (1<<24)
-#define RALINK_PCIE1_CLK_EN            (1<<25)
-#define RALINK_PCIE2_CLK_EN            (1<<26)
+#define RALINK_PCIE0_CLK_EN            BIT(24)
+#define RALINK_PCIE1_CLK_EN            BIT(25)
+#define RALINK_PCIE2_CLK_EN            BIT(26)
 
 #define RALINK_PCI_CONFIG_ADDR         0x20
 #define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG     0x24
 #define RALINK_PCI_MEMBASE             0x28
 #define RALINK_PCI_IOBASE              0x2C
-#define RALINK_PCIE0_RST               (1<<24)
-#define RALINK_PCIE1_RST               (1<<25)
-#define RALINK_PCIE2_RST               (1<<26)
+#define RALINK_PCIE0_RST               BIT(24)
+#define RALINK_PCIE1_RST               BIT(25)
+#define RALINK_PCIE2_RST               BIT(26)
 
 #define RALINK_PCI_PCICFG_ADDR         0x0000
 #define RALINK_PCI_PCIMSK_ADDR         0x000C
@@ -115,11 +115,11 @@
 #define RALINK_PCIE_CLK_GEN            0x7c
 #define RALINK_PCIE_CLK_GEN1           0x80
 //RALINK_RSTCTRL bit
-#define RALINK_PCIE_RST                        (1<<23)
-#define RALINK_PCI_RST                 (1<<24)
+#define RALINK_PCIE_RST                        BIT(23)
+#define RALINK_PCI_RST                 BIT(24)
 //RALINK_CLKCFG1 bit
-#define RALINK_PCI_CLK_EN              (1<<19)
-#define RALINK_PCIE_CLK_EN             (1<<21)
+#define RALINK_PCI_CLK_EN              BIT(19)
+#define RALINK_PCIE_CLK_EN             BIT(21)
 
 #define MEMORY_BASE 0x0
 static int pcie_link_status = 0;