drm/nouveau/disp/tu102: rename implementation from tu104
authorBen Skeggs <bskeggs@redhat.com>
Thu, 17 Jan 2019 02:10:06 +0000 (12:10 +1000)
committerBen Skeggs <bskeggs@redhat.com>
Tue, 19 Feb 2019 22:59:58 +0000 (08:59 +1000)
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
17 files changed:
drivers/gpu/drm/nouveau/dispnv50/core.c
drivers/gpu/drm/nouveau/dispnv50/curs.c
drivers/gpu/drm/nouveau/dispnv50/wimm.c
drivers/gpu/drm/nouveau/dispnv50/wndw.c
drivers/gpu/drm/nouveau/include/nvif/class.h
drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h
drivers/gpu/drm/nouveau/nvif/disp.c
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/Kbuild
drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.h
drivers/gpu/drm/nouveau/nvkm/engine/disp/roottu102.c [new file with mode: 0644]
drivers/gpu/drm/nouveau/nvkm/engine/disp/roottu104.c [deleted file]
drivers/gpu/drm/nouveau/nvkm/engine/disp/sortu102.c [new file with mode: 0644]
drivers/gpu/drm/nouveau/nvkm/engine/disp/sortu104.c [deleted file]
drivers/gpu/drm/nouveau/nvkm/engine/disp/tu102.c [new file with mode: 0644]
drivers/gpu/drm/nouveau/nvkm/engine/disp/tu104.c [deleted file]

index c25e0ebe3c92e92a724068fec1a818b171322abf..27ea3f34706d4fbdc218ca04cdf339c28d99850b 100644 (file)
@@ -42,7 +42,7 @@ nv50_core_new(struct nouveau_drm *drm, struct nv50_core **pcore)
                int version;
                int (*new)(struct nouveau_drm *, s32, struct nv50_core **);
        } cores[] = {
-               { TU104_DISP_CORE_CHANNEL_DMA, 0, corec57d_new },
+               { TU102_DISP_CORE_CHANNEL_DMA, 0, corec57d_new },
                { GV100_DISP_CORE_CHANNEL_DMA, 0, corec37d_new },
                { GP102_DISP_CORE_CHANNEL_DMA, 0, core917d_new },
                { GP100_DISP_CORE_CHANNEL_DMA, 0, core917d_new },
index cb6e4d2b1b4508fcf9e74048285a2149fe700f63..121c24a18f111ccee5d5240d0824fde6777139f6 100644 (file)
@@ -31,7 +31,7 @@ nv50_curs_new(struct nouveau_drm *drm, int head, struct nv50_wndw **pwndw)
                int version;
                int (*new)(struct nouveau_drm *, int, s32, struct nv50_wndw **);
        } curses[] = {
-               { TU104_DISP_CURSOR, 0, cursc37a_new },
+               { TU102_DISP_CURSOR, 0, cursc37a_new },
                { GV100_DISP_CURSOR, 0, cursc37a_new },
                { GK104_DISP_CURSOR, 0, curs907a_new },
                { GF110_DISP_CURSOR, 0, curs907a_new },
index bc9eeaf212ae0b9ca63c478ff3cc303a4ef7f616..a1ac153d5e9844fc35c76b292888ae8c17a752c9 100644 (file)
@@ -31,7 +31,7 @@ nv50_wimm_init(struct nouveau_drm *drm, struct nv50_wndw *wndw)
                int version;
                int (*init)(struct nouveau_drm *, s32, struct nv50_wndw *);
        } wimms[] = {
-               { TU104_DISP_WINDOW_IMM_CHANNEL_DMA, 0, wimmc37b_init },
+               { TU102_DISP_WINDOW_IMM_CHANNEL_DMA, 0, wimmc37b_init },
                { GV100_DISP_WINDOW_IMM_CHANNEL_DMA, 0, wimmc37b_init },
                {}
        };
index ba9eea2ff16bb2dbfac5606c3f1a566777d7abbc..b95181027b3177610edf8f91c4ba97be6d7314be 100644 (file)
@@ -626,7 +626,7 @@ nv50_wndw_new(struct nouveau_drm *drm, enum drm_plane_type type, int index,
                int (*new)(struct nouveau_drm *, enum drm_plane_type,
                           int, s32, struct nv50_wndw **);
        } wndws[] = {
-               { TU104_DISP_WINDOW_CHANNEL_DMA, 0, wndwc57e_new },
+               { TU102_DISP_WINDOW_CHANNEL_DMA, 0, wndwc57e_new },
                { GV100_DISP_WINDOW_CHANNEL_DMA, 0, wndwc37e_new },
                {}
        };
index 1d82cbf70cf448784e388e3e2909f5e33d568daa..214cb6ff93cd91219a2cc1f0f127edda2f4a3102 100644 (file)
@@ -84,7 +84,7 @@
 #define GP100_DISP                                    /* cl5070.h */ 0x00009770
 #define GP102_DISP                                    /* cl5070.h */ 0x00009870
 #define GV100_DISP                                    /* cl5070.h */ 0x0000c370
-#define TU104_DISP                                    /* cl5070.h */ 0x0000c570
+#define TU102_DISP                                    /* cl5070.h */ 0x0000c570
 
 #define NV31_MPEG                                                    0x00003174
 #define G82_MPEG                                                     0x00008274
@@ -97,7 +97,7 @@
 #define GF110_DISP_CURSOR                             /* cl507a.h */ 0x0000907a
 #define GK104_DISP_CURSOR                             /* cl507a.h */ 0x0000917a
 #define GV100_DISP_CURSOR                             /* cl507a.h */ 0x0000c37a
-#define TU104_DISP_CURSOR                             /* cl507a.h */ 0x0000c57a
+#define TU102_DISP_CURSOR                             /* cl507a.h */ 0x0000c57a
 
 #define NV50_DISP_OVERLAY                             /* cl507b.h */ 0x0000507b
 #define G82_DISP_OVERLAY                              /* cl507b.h */ 0x0000827b
 #define GK104_DISP_OVERLAY                            /* cl507b.h */ 0x0000917b
 
 #define GV100_DISP_WINDOW_IMM_CHANNEL_DMA             /* clc37b.h */ 0x0000c37b
-#define TU104_DISP_WINDOW_IMM_CHANNEL_DMA             /* clc37b.h */ 0x0000c57b
+#define TU102_DISP_WINDOW_IMM_CHANNEL_DMA             /* clc37b.h */ 0x0000c57b
 
 #define NV50_DISP_BASE_CHANNEL_DMA                    /* cl507c.h */ 0x0000507c
 #define G82_DISP_BASE_CHANNEL_DMA                     /* cl507c.h */ 0x0000827c
 #define GP100_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000977d
 #define GP102_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000987d
 #define GV100_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000c37d
-#define TU104_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000c57d
+#define TU102_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000c57d
 
 #define NV50_DISP_OVERLAY_CHANNEL_DMA                 /* cl507e.h */ 0x0000507e
 #define G82_DISP_OVERLAY_CHANNEL_DMA                  /* cl507e.h */ 0x0000827e
 #define GK104_DISP_OVERLAY_CONTROL_DMA                /* cl507e.h */ 0x0000917e
 
 #define GV100_DISP_WINDOW_CHANNEL_DMA                 /* clc37e.h */ 0x0000c37e
-#define TU104_DISP_WINDOW_CHANNEL_DMA                 /* clc37e.h */ 0x0000c57e
+#define TU102_DISP_WINDOW_CHANNEL_DMA                 /* clc37e.h */ 0x0000c57e
 
 #define NV50_TESLA                                                   0x00005097
 #define G82_TESLA                                                    0x00008297
index 5ca86e178bb98f5eb857d4cd2624efa533a2457c..3026b22d44fb9a284f96410f0cdf3259b6f938bf 100644 (file)
@@ -36,5 +36,5 @@ int gm200_disp_new(struct nvkm_device *, int, struct nvkm_disp **);
 int gp100_disp_new(struct nvkm_device *, int, struct nvkm_disp **);
 int gp102_disp_new(struct nvkm_device *, int, struct nvkm_disp **);
 int gv100_disp_new(struct nvkm_device *, int, struct nvkm_disp **);
-int tu104_disp_new(struct nvkm_device *, int, struct nvkm_disp **);
+int tu102_disp_new(struct nvkm_device *, int, struct nvkm_disp **);
 #endif
index ef97dd223a32f1e33091a01cc6793d6a6359a018..61638b3b9d3d66be5769e38061e3df4ab85ffe0e 100644 (file)
@@ -34,7 +34,7 @@ int
 nvif_disp_ctor(struct nvif_device *device, s32 oclass, struct nvif_disp *disp)
 {
        static const struct nvif_mclass disps[] = {
-               { TU104_DISP, -1 },
+               { TU102_DISP, -1 },
                { GV100_DISP, -1 },
                { GP102_DISP, -1 },
                { GP100_DISP, -1 },
index 2f3d8da4f090d1b172557f46caafaf24db6fb21b..856f5a2c3a4b399ac7c834f88caa8b7c34971565 100644 (file)
@@ -2461,7 +2461,7 @@ nv162_chipset = {
        .ce[2] = tu104_ce_new,
        .ce[3] = tu104_ce_new,
        .ce[4] = tu104_ce_new,
-       .disp = tu104_disp_new,
+       .disp = tu102_disp_new,
        .dma = gv100_dma_new,
        .fifo = tu104_fifo_new,
 };
@@ -2493,7 +2493,7 @@ nv164_chipset = {
        .ce[2] = tu104_ce_new,
        .ce[3] = tu104_ce_new,
        .ce[4] = tu104_ce_new,
-       .disp = tu104_disp_new,
+       .disp = tu102_disp_new,
        .dma = gv100_dma_new,
        .fifo = tu104_fifo_new,
 };
@@ -2525,7 +2525,7 @@ nv166_chipset = {
        .ce[2] = tu104_ce_new,
        .ce[3] = tu104_ce_new,
        .ce[4] = tu104_ce_new,
-       .disp = tu104_disp_new,
+       .disp = tu102_disp_new,
        .dma = gv100_dma_new,
        .fifo = tu104_fifo_new,
 };
index c6a257ba43476dec8f43d3d431f765a792ed6abc..2c28a5e747cccf2af89b8a6ddcea11dce74c5dfa 100644 (file)
@@ -15,7 +15,7 @@ nvkm-y += nvkm/engine/disp/gm200.o
 nvkm-y += nvkm/engine/disp/gp100.o
 nvkm-y += nvkm/engine/disp/gp102.o
 nvkm-y += nvkm/engine/disp/gv100.o
-nvkm-y += nvkm/engine/disp/tu104.o
+nvkm-y += nvkm/engine/disp/tu102.o
 nvkm-y += nvkm/engine/disp/vga.o
 
 nvkm-y += nvkm/engine/disp/head.o
@@ -39,7 +39,7 @@ nvkm-y += nvkm/engine/disp/sorgk104.o
 nvkm-y += nvkm/engine/disp/sorgm107.o
 nvkm-y += nvkm/engine/disp/sorgm200.o
 nvkm-y += nvkm/engine/disp/sorgv100.o
-nvkm-y += nvkm/engine/disp/sortu104.o
+nvkm-y += nvkm/engine/disp/sortu102.o
 
 nvkm-y += nvkm/engine/disp/outp.o
 nvkm-y += nvkm/engine/disp/dp.o
@@ -71,7 +71,7 @@ nvkm-y += nvkm/engine/disp/rootgm200.o
 nvkm-y += nvkm/engine/disp/rootgp100.o
 nvkm-y += nvkm/engine/disp/rootgp102.o
 nvkm-y += nvkm/engine/disp/rootgv100.o
-nvkm-y += nvkm/engine/disp/roottu104.o
+nvkm-y += nvkm/engine/disp/roottu102.o
 
 nvkm-y += nvkm/engine/disp/channv50.o
 nvkm-y += nvkm/engine/disp/changf119.o
index 790e42f460fdc78a2e83cc249cf373b84ee72bd3..1681ddccd298ce8354a20a0d7de963bdd50c659e 100644 (file)
@@ -201,5 +201,5 @@ int gm200_sor_new(struct nvkm_disp *, int);
 int gv100_sor_cnt(struct nvkm_disp *, unsigned long *);
 int gv100_sor_new(struct nvkm_disp *, int);
 
-int tu104_sor_new(struct nvkm_disp *, int);
+int tu102_sor_new(struct nvkm_disp *, int);
 #endif
index 97de928cbde131b4a4a7176361f24fd964006f8c..aee9822a7a87c045054696dbca189da150c01cbe 100644 (file)
@@ -37,5 +37,5 @@ extern const struct nvkm_disp_oclass gm200_disp_root_oclass;
 extern const struct nvkm_disp_oclass gp100_disp_root_oclass;
 extern const struct nvkm_disp_oclass gp102_disp_root_oclass;
 extern const struct nvkm_disp_oclass gv100_disp_root_oclass;
-extern const struct nvkm_disp_oclass tu104_disp_root_oclass;
+extern const struct nvkm_disp_oclass tu102_disp_root_oclass;
 #endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/roottu102.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/roottu102.c
new file mode 100644 (file)
index 0000000..579a5d0
--- /dev/null
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2018 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+#include "rootnv50.h"
+#include "channv50.h"
+
+#include <nvif/class.h>
+
+static const struct nv50_disp_root_func
+tu102_disp_root = {
+       .user = {
+               {{0,0,TU102_DISP_CURSOR                }, gv100_disp_curs_new },
+               {{0,0,TU102_DISP_WINDOW_IMM_CHANNEL_DMA}, gv100_disp_wimm_new },
+               {{0,0,TU102_DISP_CORE_CHANNEL_DMA      }, gv100_disp_core_new },
+               {{0,0,TU102_DISP_WINDOW_CHANNEL_DMA    }, gv100_disp_wndw_new },
+               {}
+       },
+};
+
+static int
+tu102_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass,
+                   void *data, u32 size, struct nvkm_object **pobject)
+{
+       return nv50_disp_root_new_(&tu102_disp_root, disp, oclass,
+                                  data, size, pobject);
+}
+
+const struct nvkm_disp_oclass
+tu102_disp_root_oclass = {
+       .base.oclass = TU102_DISP,
+       .base.minver = -1,
+       .base.maxver = -1,
+       .ctor = tu102_disp_root_new,
+};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/roottu104.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/roottu104.c
deleted file mode 100644 (file)
index ad438c6..0000000
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * Copyright 2018 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-#include "rootnv50.h"
-#include "channv50.h"
-
-#include <nvif/class.h>
-
-static const struct nv50_disp_root_func
-tu104_disp_root = {
-       .user = {
-               {{0,0,TU104_DISP_CURSOR                }, gv100_disp_curs_new },
-               {{0,0,TU104_DISP_WINDOW_IMM_CHANNEL_DMA}, gv100_disp_wimm_new },
-               {{0,0,TU104_DISP_CORE_CHANNEL_DMA      }, gv100_disp_core_new },
-               {{0,0,TU104_DISP_WINDOW_CHANNEL_DMA    }, gv100_disp_wndw_new },
-               {}
-       },
-};
-
-static int
-tu104_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass,
-                   void *data, u32 size, struct nvkm_object **pobject)
-{
-       return nv50_disp_root_new_(&tu104_disp_root, disp, oclass,
-                                  data, size, pobject);
-}
-
-const struct nvkm_disp_oclass
-tu104_disp_root_oclass = {
-       .base.oclass = TU104_DISP,
-       .base.minver = -1,
-       .base.maxver = -1,
-       .ctor = tu104_disp_root_new,
-};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sortu102.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sortu102.c
new file mode 100644 (file)
index 0000000..d57b73a
--- /dev/null
@@ -0,0 +1,97 @@
+/*
+ * Copyright 2018 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+#include "ior.h"
+
+#include <subdev/timer.h>
+
+static void
+tu102_sor_dp_vcpi(struct nvkm_ior *sor, int head,
+                 u8 slot, u8 slot_nr, u16 pbn, u16 aligned)
+{
+       struct nvkm_device *device = sor->disp->engine.subdev.device;
+       const u32 hoff = head * 0x800;
+
+       nvkm_mask(device, 0x61657c + hoff, 0xffffffff, (aligned << 16) | pbn);
+       nvkm_mask(device, 0x616578 + hoff, 0x00003f3f, (slot_nr << 8) | slot);
+}
+
+static int
+tu102_sor_dp_links(struct nvkm_ior *sor, struct nvkm_i2c_aux *aux)
+{
+       struct nvkm_device *device = sor->disp->engine.subdev.device;
+       const u32 soff = nv50_ior_base(sor);
+       const u32 loff = nv50_sor_link(sor);
+       u32 dpctrl = 0x00000000;
+       u32 clksor = 0x00000000;
+
+       clksor |= sor->dp.bw << 18;
+       dpctrl |= ((1 << sor->dp.nr) - 1) << 16;
+       if (sor->dp.mst)
+               dpctrl |= 0x40000000;
+       if (sor->dp.ef)
+               dpctrl |= 0x00004000;
+
+       nvkm_mask(device, 0x612300 + soff, 0x007c0000, clksor);
+
+       /*XXX*/
+       nvkm_msec(device, 40, NVKM_DELAY);
+       nvkm_mask(device, 0x612300 + soff, 0x00030000, 0x00010000);
+       nvkm_mask(device, 0x61c10c + loff, 0x00000003, 0x00000001);
+
+       nvkm_mask(device, 0x61c10c + loff, 0x401f4000, dpctrl);
+       return 0;
+}
+
+static const struct nvkm_ior_func
+tu102_sor = {
+       .route = {
+               .get = gm200_sor_route_get,
+               .set = gm200_sor_route_set,
+       },
+       .state = gv100_sor_state,
+       .power = nv50_sor_power,
+       .clock = gf119_sor_clock,
+       .hdmi = {
+               .ctrl = gv100_hdmi_ctrl,
+       },
+       .dp = {
+               .lanes = { 0, 1, 2, 3 },
+               .links = tu102_sor_dp_links,
+               .power = g94_sor_dp_power,
+               .pattern = gm107_sor_dp_pattern,
+               .drive = gm200_sor_dp_drive,
+               .vcpi = tu102_sor_dp_vcpi,
+               .audio = gv100_sor_dp_audio,
+               .audio_sym = gv100_sor_dp_audio_sym,
+               .watermark = gv100_sor_dp_watermark,
+       },
+       .hda = {
+               .hpd = gf119_hda_hpd,
+               .eld = gf119_hda_eld,
+       },
+};
+
+int
+tu102_sor_new(struct nvkm_disp *disp, int id)
+{
+       return nvkm_ior_new_(&tu102_sor, disp, SOR, id);
+}
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sortu104.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sortu104.c
deleted file mode 100644 (file)
index df026a5..0000000
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- * Copyright 2018 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-#include "ior.h"
-
-#include <subdev/timer.h>
-
-static void
-tu104_sor_dp_vcpi(struct nvkm_ior *sor, int head,
-                 u8 slot, u8 slot_nr, u16 pbn, u16 aligned)
-{
-       struct nvkm_device *device = sor->disp->engine.subdev.device;
-       const u32 hoff = head * 0x800;
-
-       nvkm_mask(device, 0x61657c + hoff, 0xffffffff, (aligned << 16) | pbn);
-       nvkm_mask(device, 0x616578 + hoff, 0x00003f3f, (slot_nr << 8) | slot);
-}
-
-static int
-tu104_sor_dp_links(struct nvkm_ior *sor, struct nvkm_i2c_aux *aux)
-{
-       struct nvkm_device *device = sor->disp->engine.subdev.device;
-       const u32 soff = nv50_ior_base(sor);
-       const u32 loff = nv50_sor_link(sor);
-       u32 dpctrl = 0x00000000;
-       u32 clksor = 0x00000000;
-
-       clksor |= sor->dp.bw << 18;
-       dpctrl |= ((1 << sor->dp.nr) - 1) << 16;
-       if (sor->dp.mst)
-               dpctrl |= 0x40000000;
-       if (sor->dp.ef)
-               dpctrl |= 0x00004000;
-
-       nvkm_mask(device, 0x612300 + soff, 0x007c0000, clksor);
-
-       /*XXX*/
-       nvkm_msec(device, 40, NVKM_DELAY);
-       nvkm_mask(device, 0x612300 + soff, 0x00030000, 0x00010000);
-       nvkm_mask(device, 0x61c10c + loff, 0x00000003, 0x00000001);
-
-       nvkm_mask(device, 0x61c10c + loff, 0x401f4000, dpctrl);
-       return 0;
-}
-
-static const struct nvkm_ior_func
-tu104_sor = {
-       .route = {
-               .get = gm200_sor_route_get,
-               .set = gm200_sor_route_set,
-       },
-       .state = gv100_sor_state,
-       .power = nv50_sor_power,
-       .clock = gf119_sor_clock,
-       .hdmi = {
-               .ctrl = gv100_hdmi_ctrl,
-       },
-       .dp = {
-               .lanes = { 0, 1, 2, 3 },
-               .links = tu104_sor_dp_links,
-               .power = g94_sor_dp_power,
-               .pattern = gm107_sor_dp_pattern,
-               .drive = gm200_sor_dp_drive,
-               .vcpi = tu104_sor_dp_vcpi,
-               .audio = gv100_sor_dp_audio,
-               .audio_sym = gv100_sor_dp_audio_sym,
-               .watermark = gv100_sor_dp_watermark,
-       },
-       .hda = {
-               .hpd = gf119_hda_hpd,
-               .eld = gf119_hda_eld,
-       },
-};
-
-int
-tu104_sor_new(struct nvkm_disp *disp, int id)
-{
-       return nvkm_ior_new_(&tu104_sor, disp, SOR, id);
-}
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/tu102.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/tu102.c
new file mode 100644 (file)
index 0000000..883ae41
--- /dev/null
@@ -0,0 +1,152 @@
+/*
+ * Copyright 2018 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+#include "nv50.h"
+#include "head.h"
+#include "ior.h"
+#include "channv50.h"
+#include "rootnv50.h"
+
+#include <core/gpuobj.h>
+#include <subdev/timer.h>
+
+static int
+tu102_disp_init(struct nv50_disp *disp)
+{
+       struct nvkm_device *device = disp->base.engine.subdev.device;
+       struct nvkm_head *head;
+       int i, j;
+       u32 tmp;
+
+       /* Claim ownership of display. */
+       if (nvkm_rd32(device, 0x6254e8) & 0x00000002) {
+               nvkm_mask(device, 0x6254e8, 0x00000001, 0x00000000);
+               if (nvkm_msec(device, 2000,
+                       if (!(nvkm_rd32(device, 0x6254e8) & 0x00000002))
+                               break;
+               ) < 0)
+                       return -EBUSY;
+       }
+
+       /* Lock pin capabilities. */
+       tmp = 0x00000021; /*XXX*/
+       nvkm_wr32(device, 0x640008, tmp);
+
+       /* SOR capabilities. */
+       for (i = 0; i < disp->sor.nr; i++) {
+               tmp = nvkm_rd32(device, 0x61c000 + (i * 0x800));
+               nvkm_mask(device, 0x640000, 0x00000100 << i, 0x00000100 << i);
+               nvkm_wr32(device, 0x640144 + (i * 0x08), tmp);
+       }
+
+       /* Head capabilities. */
+       list_for_each_entry(head, &disp->base.head, head) {
+               const int id = head->id;
+
+               /* RG. */
+               tmp = nvkm_rd32(device, 0x616300 + (id * 0x800));
+               nvkm_wr32(device, 0x640048 + (id * 0x020), tmp);
+
+               /* POSTCOMP. */
+               for (j = 0; j < 5 * 4; j += 4) {
+                       tmp = nvkm_rd32(device, 0x616140 + (id * 0x800) + j);
+                       nvkm_wr32(device, 0x640680 + (id * 0x20) + j, tmp);
+               }
+       }
+
+       /* Window capabilities. */
+       for (i = 0; i < disp->wndw.nr; i++) {
+               nvkm_mask(device, 0x640004, 1 << i, 1 << i);
+               for (j = 0; j < 6 * 4; j += 4) {
+                       tmp = nvkm_rd32(device, 0x630100 + (i * 0x800) + j);
+                       nvkm_mask(device, 0x640780 + (i * 0x20) + j, 0xffffffff, tmp);
+               }
+               nvkm_mask(device, 0x64000c, 0x00000100, 0x00000100);
+       }
+
+       /* IHUB capabilities. */
+       for (i = 0; i < 3; i++) {
+               tmp = nvkm_rd32(device, 0x62e000 + (i * 0x04));
+               nvkm_wr32(device, 0x640010 + (i * 0x04), tmp);
+       }
+
+       nvkm_mask(device, 0x610078, 0x00000001, 0x00000001);
+
+       /* Setup instance memory. */
+       switch (nvkm_memory_target(disp->inst->memory)) {
+       case NVKM_MEM_TARGET_VRAM: tmp = 0x00000001; break;
+       case NVKM_MEM_TARGET_NCOH: tmp = 0x00000002; break;
+       case NVKM_MEM_TARGET_HOST: tmp = 0x00000003; break;
+       default:
+               break;
+       }
+       nvkm_wr32(device, 0x610010, 0x00000008 | tmp);
+       nvkm_wr32(device, 0x610014, disp->inst->addr >> 16);
+
+       /* CTRL_DISP: AWAKEN, ERROR, SUPERVISOR[1-3]. */
+       nvkm_wr32(device, 0x611cf0, 0x00000187); /* MSK. */
+       nvkm_wr32(device, 0x611db0, 0x00000187); /* EN. */
+
+       /* EXC_OTHER: CURSn, CORE. */
+       nvkm_wr32(device, 0x611cec, disp->head.mask << 16 |
+                                   0x00000001); /* MSK. */
+       nvkm_wr32(device, 0x611dac, 0x00000000); /* EN. */
+
+       /* EXC_WINIM. */
+       nvkm_wr32(device, 0x611ce8, disp->wndw.mask); /* MSK. */
+       nvkm_wr32(device, 0x611da8, 0x00000000); /* EN. */
+
+       /* EXC_WIN. */
+       nvkm_wr32(device, 0x611ce4, disp->wndw.mask); /* MSK. */
+       nvkm_wr32(device, 0x611da4, 0x00000000); /* EN. */
+
+       /* HEAD_TIMING(n): VBLANK. */
+       list_for_each_entry(head, &disp->base.head, head) {
+               const u32 hoff = head->id * 4;
+               nvkm_wr32(device, 0x611cc0 + hoff, 0x00000004); /* MSK. */
+               nvkm_wr32(device, 0x611d80 + hoff, 0x00000000); /* EN. */
+       }
+
+       /* OR. */
+       nvkm_wr32(device, 0x611cf4, 0x00000000); /* MSK. */
+       nvkm_wr32(device, 0x611db4, 0x00000000); /* EN. */
+       return 0;
+}
+
+static const struct nv50_disp_func
+tu102_disp = {
+       .init = tu102_disp_init,
+       .fini = gv100_disp_fini,
+       .intr = gv100_disp_intr,
+       .uevent = &gv100_disp_chan_uevent,
+       .super = gv100_disp_super,
+       .root = &tu102_disp_root_oclass,
+       .wndw = { .cnt = gv100_disp_wndw_cnt },
+       .head = { .cnt = gv100_head_cnt, .new = gv100_head_new },
+       .sor = { .cnt = gv100_sor_cnt, .new = tu102_sor_new },
+       .ramht_size = 0x2000,
+};
+
+int
+tu102_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp)
+{
+       return nv50_disp_new_(&tu102_disp, device, index, pdisp);
+}
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/tu104.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/tu104.c
deleted file mode 100644 (file)
index 13fa214..0000000
+++ /dev/null
@@ -1,152 +0,0 @@
-/*
- * Copyright 2018 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-#include "nv50.h"
-#include "head.h"
-#include "ior.h"
-#include "channv50.h"
-#include "rootnv50.h"
-
-#include <core/gpuobj.h>
-#include <subdev/timer.h>
-
-static int
-tu104_disp_init(struct nv50_disp *disp)
-{
-       struct nvkm_device *device = disp->base.engine.subdev.device;
-       struct nvkm_head *head;
-       int i, j;
-       u32 tmp;
-
-       /* Claim ownership of display. */
-       if (nvkm_rd32(device, 0x6254e8) & 0x00000002) {
-               nvkm_mask(device, 0x6254e8, 0x00000001, 0x00000000);
-               if (nvkm_msec(device, 2000,
-                       if (!(nvkm_rd32(device, 0x6254e8) & 0x00000002))
-                               break;
-               ) < 0)
-                       return -EBUSY;
-       }
-
-       /* Lock pin capabilities. */
-       tmp = 0x00000021; /*XXX*/
-       nvkm_wr32(device, 0x640008, tmp);
-
-       /* SOR capabilities. */
-       for (i = 0; i < disp->sor.nr; i++) {
-               tmp = nvkm_rd32(device, 0x61c000 + (i * 0x800));
-               nvkm_mask(device, 0x640000, 0x00000100 << i, 0x00000100 << i);
-               nvkm_wr32(device, 0x640144 + (i * 0x08), tmp);
-       }
-
-       /* Head capabilities. */
-       list_for_each_entry(head, &disp->base.head, head) {
-               const int id = head->id;
-
-               /* RG. */
-               tmp = nvkm_rd32(device, 0x616300 + (id * 0x800));
-               nvkm_wr32(device, 0x640048 + (id * 0x020), tmp);
-
-               /* POSTCOMP. */
-               for (j = 0; j < 5 * 4; j += 4) {
-                       tmp = nvkm_rd32(device, 0x616140 + (id * 0x800) + j);
-                       nvkm_wr32(device, 0x640680 + (id * 0x20) + j, tmp);
-               }
-       }
-
-       /* Window capabilities. */
-       for (i = 0; i < disp->wndw.nr; i++) {
-               nvkm_mask(device, 0x640004, 1 << i, 1 << i);
-               for (j = 0; j < 6 * 4; j += 4) {
-                       tmp = nvkm_rd32(device, 0x630100 + (i * 0x800) + j);
-                       nvkm_mask(device, 0x640780 + (i * 0x20) + j, 0xffffffff, tmp);
-               }
-               nvkm_mask(device, 0x64000c, 0x00000100, 0x00000100);
-       }
-
-       /* IHUB capabilities. */
-       for (i = 0; i < 3; i++) {
-               tmp = nvkm_rd32(device, 0x62e000 + (i * 0x04));
-               nvkm_wr32(device, 0x640010 + (i * 0x04), tmp);
-       }
-
-       nvkm_mask(device, 0x610078, 0x00000001, 0x00000001);
-
-       /* Setup instance memory. */
-       switch (nvkm_memory_target(disp->inst->memory)) {
-       case NVKM_MEM_TARGET_VRAM: tmp = 0x00000001; break;
-       case NVKM_MEM_TARGET_NCOH: tmp = 0x00000002; break;
-       case NVKM_MEM_TARGET_HOST: tmp = 0x00000003; break;
-       default:
-               break;
-       }
-       nvkm_wr32(device, 0x610010, 0x00000008 | tmp);
-       nvkm_wr32(device, 0x610014, disp->inst->addr >> 16);
-
-       /* CTRL_DISP: AWAKEN, ERROR, SUPERVISOR[1-3]. */
-       nvkm_wr32(device, 0x611cf0, 0x00000187); /* MSK. */
-       nvkm_wr32(device, 0x611db0, 0x00000187); /* EN. */
-
-       /* EXC_OTHER: CURSn, CORE. */
-       nvkm_wr32(device, 0x611cec, disp->head.mask << 16 |
-                                   0x00000001); /* MSK. */
-       nvkm_wr32(device, 0x611dac, 0x00000000); /* EN. */
-
-       /* EXC_WINIM. */
-       nvkm_wr32(device, 0x611ce8, disp->wndw.mask); /* MSK. */
-       nvkm_wr32(device, 0x611da8, 0x00000000); /* EN. */
-
-       /* EXC_WIN. */
-       nvkm_wr32(device, 0x611ce4, disp->wndw.mask); /* MSK. */
-       nvkm_wr32(device, 0x611da4, 0x00000000); /* EN. */
-
-       /* HEAD_TIMING(n): VBLANK. */
-       list_for_each_entry(head, &disp->base.head, head) {
-               const u32 hoff = head->id * 4;
-               nvkm_wr32(device, 0x611cc0 + hoff, 0x00000004); /* MSK. */
-               nvkm_wr32(device, 0x611d80 + hoff, 0x00000000); /* EN. */
-       }
-
-       /* OR. */
-       nvkm_wr32(device, 0x611cf4, 0x00000000); /* MSK. */
-       nvkm_wr32(device, 0x611db4, 0x00000000); /* EN. */
-       return 0;
-}
-
-static const struct nv50_disp_func
-tu104_disp = {
-       .init = tu104_disp_init,
-       .fini = gv100_disp_fini,
-       .intr = gv100_disp_intr,
-       .uevent = &gv100_disp_chan_uevent,
-       .super = gv100_disp_super,
-       .root = &tu104_disp_root_oclass,
-       .wndw = { .cnt = gv100_disp_wndw_cnt },
-       .head = { .cnt = gv100_head_cnt, .new = gv100_head_new },
-       .sor = { .cnt = gv100_sor_cnt, .new = tu104_sor_new },
-       .ramht_size = 0x2000,
-};
-
-int
-tu104_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp)
-{
-       return nv50_disp_new_(&tu104_disp, device, index, pdisp);
-}