arm64: zynqmp: Add phase tags marking
authorMichal Simek <michal.simek@amd.com>
Tue, 2 May 2023 13:35:51 +0000 (15:35 +0200)
committerMichal Simek <michal.simek@amd.com>
Tue, 16 May 2023 12:50:15 +0000 (14:50 +0200)
bootph-all as phase tag was added to dt-schema
(dtschema/schemas/bootph.yaml) to cover U-Boot challenges with DT.
That's why add it also to Linux to be aligned with bootloader requirement.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/48b554aef75d11e6ad2ef7d21f22accb35432112.1683034376.git.michal.simek@amd.com
arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts
arch/arm64/boot/dts/xilinx/zynqmp.dtsi

index 581221fdadf13b58ee57b2732e0b5e44c8deffbc..719ea5d5ae88d6bbebfdc613e27f35ef1cb50403 100644 (file)
 #include <dt-bindings/clock/xlnx-zynqmp-clk.h>
 / {
        pss_ref_clk: pss_ref_clk {
+               bootph-all;
                compatible = "fixed-clock";
                #clock-cells = <0>;
                clock-frequency = <33333333>;
        };
 
        video_clk: video_clk {
+               bootph-all;
                compatible = "fixed-clock";
                #clock-cells = <0>;
                clock-frequency = <27000000>;
        };
 
        pss_alt_ref_clk: pss_alt_ref_clk {
+               bootph-all;
                compatible = "fixed-clock";
                #clock-cells = <0>;
                clock-frequency = <0>;
        };
 
        gt_crx_ref_clk: gt_crx_ref_clk {
+               bootph-all;
                compatible = "fixed-clock";
                #clock-cells = <0>;
                clock-frequency = <108000000>;
        };
 
        aux_ref_clk: aux_ref_clk {
+               bootph-all;
                compatible = "fixed-clock";
                #clock-cells = <0>;
                clock-frequency = <27000000>;
@@ -43,6 +48,7 @@
 
 &zynqmp_firmware {
        zynqmp_clk: clock-controller {
+               bootph-all;
                #clock-cells = <1>;
                compatible = "xlnx,zynqmp-clk";
                clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>,
index 3f8a7a497f3e2b77f87a8caa998c1ad1ea73f2bd..464e28bf078a446d5fe06ba7722407b25102958a 100644 (file)
 
 &i2c1 {
        status = "okay";
+       bootph-all;
        clock-frequency = <400000>;
        scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
        sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
 
        eeprom: eeprom@50 { /* u46 - also at address 0x58 */
+               bootph-all;
                compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */
                reg = <0x50>;
                /* WP pin EE_WP_EN connected to slg7x644092@68 */
        };
 
        eeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */
+               bootph-all;
                compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */
                reg = <0x51>;
        };
index 44e0ab8aae53c8ff1e7ae43d26eb06743f77f949..850b497d7a8122cce9cc531de0569ad6bed800f4 100644 (file)
        };
 
        zynqmp_ipi: zynqmp_ipi {
+               bootph-all;
                compatible = "xlnx,zynqmp-ipi-mailbox";
                interrupt-parent = <&gic>;
                interrupts = <0 35 4>;
                ranges;
 
                ipi_mailbox_pmu1: mailbox@ff9905c0 {
+                       bootph-all;
                        reg = <0x0 0xff9905c0 0x0 0x20>,
                              <0x0 0xff9905e0 0x0 0x20>,
                              <0x0 0xff990e80 0x0 0x20>,
        dcc: dcc {
                compatible = "arm,dcc";
                status = "disabled";
+               bootph-all;
        };
 
        pmu {
                        compatible = "xlnx,zynqmp-firmware";
                        #power-domain-cells = <1>;
                        method = "smc";
+                       bootph-all;
 
                        zynqmp_power: zynqmp-power {
+                               bootph-all;
                                compatible = "xlnx,zynqmp-power";
                                interrupt-parent = <&gic>;
                                interrupts = <0 35 4>;
 
        amba: axi {
                compatible = "simple-bus";
+               bootph-all;
                #address-cells = <2>;
                #size-cells = <2>;
                ranges;
                };
 
                qspi: spi@ff0f0000 {
+                       bootph-all;
                        compatible = "xlnx,zynqmp-qspi-1.0";
                        status = "disabled";
                        clock-names = "ref_clk", "pclk";
                };
 
                sdhci0: mmc@ff160000 {
+                       bootph-all;
                        compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
                        status = "disabled";
                        interrupt-parent = <&gic>;
                };
 
                sdhci1: mmc@ff170000 {
+                       bootph-all;
                        compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
                        status = "disabled";
                        interrupt-parent = <&gic>;
                };
 
                uart0: serial@ff000000 {
+                       bootph-all;
                        compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
                        status = "disabled";
                        interrupt-parent = <&gic>;
                };
 
                uart1: serial@ff010000 {
+                       bootph-all;
                        compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
                        status = "disabled";
                        interrupt-parent = <&gic>;
                };
 
                zynqmp_dpsub: display@fd4a0000 {
+                       bootph-all;
                        compatible = "xlnx,zynqmp-dpsub-1.7";
                        status = "disabled";
                        reg = <0x0 0xfd4a0000 0x0 0x1000>,